EXPERIMENT 1.

AIM:- Introduction to Microwind and Analysis of CMOS 0.25 MICRON technology MOSFET

Fig. 1.1 Schematic diagram of the NMOS transistor

Fig. 1.2 layout design of NMOS transistor

Fig.1.3 Timing diagram of NMOS transistor

Fig 1.4 Graph between Voltage and Time.

Fig1.5 rise time with capacitance of NMOS

Fig1.6 Fall time with capacitance of NMOS

Fig1.7 Power dissipation with capacitance of NMOS

Fig1.8 effect of input voltage rise time of NMOS

Fig1.9 effect of input voltage rise time of NMOS

Fig1.10 effect of input voltage power dissipation of NMOS

EXPERIMENT 2.
AIM:- CMOS 0.25 MICRON technology inverter characteristics and layout in Microwind

Fig. 2.1Circuit set up for analysis to inverter

Fig. 2.2 layout design of inverter gate

Fig. 2.3 graph of the Rise time of inverter gate

Table 2.1 rise time of inverter gate

Fig. 2.3 Graph of the Fall time of inverter gate

Table 2.2 Fall time of inverter gate

Fig. 2.4 Graph of the Power Dissipation inverter gate

Table 2.3 Power dissipation of inverter gate

Fig. 2.5 Graph of the Power Dissipation with temperature variable inverter gate

Table 2.4 Power dissipation with temperature variable of inverter gate

Fig. 2.6 Graph of the Rise time with input voltage variable inverter gate

Table 2.5 Rise time with input voltage variable of inverter gate

Fig. 2.7 Graph of the Fall time with input voltage variable inverter gate

Table 2.6 Fall time with input voltage variable of inverter gate

Fig. 2.8 Graph of the maximum Idd current with input voltage variable inverter gate

Table 2.7 maximum Idd current with input voltage variable inverter gate

Fig. 2.9 Graph of the Power dissipation with input voltage variable inverter gate

Table 2.8 the Power dissipation with input voltage variable inverter gate

EXPERIMENT 3.
AIM:- layout of basic gate and a complex gate using CMOS 0.25 MICRON technology in Microwind

Fig. 3.1 Schematic diagram of NAND gate

Fig.3.2 layout design of NAND gate

Fig. 3.3 graph between time and voltage

Fig.3.4 power dissipation of NAND gate

Table 3.1 power dissipation of NAND gate

Fig. 3.5 Schematic diagram of NOR gate

Fig.3.6 layout design of NOR gate

Complex gate
F=ad +b(cd+ a)

Fig. 3.7 Schematic diagram of complex gate gate

Fig.3.8 layout design of NOR gate

EXPERIMENT4.
AIM:- CMOS 0.25 MICRON technology inverter characteristics and layout in Microwind

Fig 4.1 Schematic of XOR gate

Fig.3.2 layout design of XOR gate

Fig 4.3 Timing diagram of XOR gate.

Fig 4.1 Schematic of XNOR gate

Fig.3.2 layout design of XNOR gate

Fig 4.3 Timing diagram of XNOR gate.

Fig 4.3 propagation delay of XNOR gate.

Fig. 3.1 Schematic diagram of XNOR gate

Fig.3.2 layout design of XNOR gate

Fig 4.6 Graph Voltage and IDD of XNOR gate

Fig 4.7 power dissipation of of XNOR gate

EXPERIMENT 5.
AIM:- Layout of Multiplexer , Demultiplexer CMOS 0.25 MICRON technology in Microwind

Fig. 5.1 Schematic diagram of MUX2*1

Fig.5.2 layout design of MUX2*1

Fig 4.7 voltage VS time graph of of MUX 2*1

Fig 4.7 power dissipation of of MUX 2*1

Fig. 5.1 Schematic diagram of DEMUX

Fig.5.2 layout design of DEMUX

Fig 4.7 voltage VS time graph of of DEMUX

Fig 4.7 power dissipation of of DE MUX

EXPERIMENT 6.
AIM:- Design and implemented of Layout of full adder CMOS 0.25 MICRON technology in Microwind

Fig. 6.1 Schematic diagram of Full adder

Fig.6.2 design of Full adder

EXPERIMENT 8.
AIM:- Design and implemented of Layout of 4*1 MUX CMOS 0.25 MICRON technology in Microwind

Fig. 8.1 Schematic diagram of 4*1 MUX

Fig.8.2 Layout design of4*1 MUX

EXPERIMENT 9.
AIM:- Design and implemented of Layout of RS latch, D-latch CMOS 0.25 MICRON technology in
Microwind

Fig. 9.1 Schematic diagram of Full adder

Fig.9.2 design of Full adder

Fig. 9.3 Schematic diagram of Full adder

Fig.9.4 layout design of Full adder

EXPERIMENT 10.
AIM:- Design and implemented of Layout of synchronous and asynchronous counter CMOS 0.25
MICRON technology in Microwind

Fig. 10.1 Schematic diagram of 4 bit synchronous counter.

Fig.10.2 layout design of 4 bit synchronous counter.

Fig. 103 Schematic diagram of 4 bit asynchronous counter.

Fig.10.2 layout design of 4 bit synchronous counter.