Tutorial Sheet No 2

Computer Architecture (UEC-402)

Q1.Suppose we are considering a change to the instruction set. Assume that the processor has
only loads and stores to memory, and then all operations work on the registers much like the
MIPS processor. Now, assume that you have profiled the code and the instruction mix is
detailed below:
The instruction mix and CPIs of individual instructions
Operation
Frequency
CPI
ALU Operations
43%
1
Loads
21%
2
Stores
12%
2
branches
24%
2
Let us now assume that 25% of the ALU operations directly use a loaded operand from
memory that is not used again. As a designer, you propose adding ALU instructions that have
one source operand in memory. These new \register-memory instructions" have a CPI of 2.
The extended instruction set increases the CPI of branches by 1, but does not affect the clock
cycle time. Would this change improve CPU performance?
Q2. Consider two different implementations, M1 and M2, of the same instruction set. There
are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 80
MHz and M2 has a clock rate of 100 MHz. The average number of cycles for each instruction
class and their frequencies (for a typical program) are as follows:

(a) Calculate the average CPI for each machine, M1, and M2.
(b) Calculate the average MIPS rating for the machines M1 and M2.
Calculate the average CPI for each machine, M1, and M2.
Sol.For Machine M1:
Clocks per Instruction = (60/100)* 1 + (30/100)*2 + (10/100)*4
= 1.6
For Machine M2:
Clocks per Instruction = (60/100)*2 + (30/100)*3 + (10/100)*4
= 2.5
(b) Calculate the average MIPS ratings for each machine, M1 and M2.
For Machine M1:
Average MIPS rating = Clock Rate/(CPI * 106)
= (80 * 106) / (1.6*106)
= 50.0
For Machine M2:

Average MIPS rating = Clock Rate/(CPI * 106)

= (100 * 106) / (2.5*106)
= 40.0
Q3 .Suppose that we can improve the floating point instruction performance of machine by a
factor of 15 (the same floating point instructions run 15 times faster on this new machine).
What percent of the instructions must be floating point to achieve a Speedup of at least 4?
Sol.
We will use Amdahls Law again for this question.
Let x be percentage of floating point instructions. Since the speedup is 4, if the original
program
executed in 100 cycles, the new program runs in 100/4 = 25 cycles.
(100)/4 = (x)/15 + (100 x)
Solving for x, we get:
x = 80.36
The percent of floating point instructions need to be 80.36.

Q3. Assume that a design team is considering enhancing a machine by adding MMX
(multimedia extension instruction) hardware to a processor. When a computation is run in
MMX mode on the MMX hardware, it is 10 times faster than the normal mode of execution.
Call the percentage of time that could be spent using the MMX mode the percentage of media
enhancement.
What percentage of media enhancement is needed to achieve an overall speedup of 2?
What percentage of the run-time is spent in MMX mode if a speedup of 2 is achieved?
(Hint:You will need to calculate the new overall time.)
What percentage of the media enhancement is needed to achieve one-half the maximum
speedup attainable from using the MMX mode?
a) We will use Amdahls Law for this question.
Execution time with Media Enhancement =
(Execution time improved by Media enhancement)/(Amount of Improvement) +
Execution time unaffected
Let x be the percent of media enhancement needed for achieving an overall speedup of
2. Then,
(100)/2 = (x)/10 + (100-x)
Solving for x, we have x = 55.55

b) The new overall time is 100/2 = 50. = 5.55 + 44.45. 5.55 is for media enhancement
using MMX mode. 5.55/(50) = 11.1%
Q4. The design team for a simple, single-issue processor is choosing between a pipelined or
non-pipelined implementation. Here are some design parameters for the two possibilities:
a) For a program with 20% ALU instructions, 10% control instructions and 70% memory
b)instructions, which design will be faster? Give a quantitative CPI average for each case.
For a program with 80% ALU instructions, 10% control instructions and 10% memory
instructions, which design will be faster? Give a quantitative CPI average for each case

a) Average CPI for Pipelined Version = (0.2*1 + 0.1*2 + 0.7*2.7) = 2.29

Average CPI for Non-Pipelined Version = (0.2*1 + 0.1*1 + 0.7*1) = 1.0
CPU execution time for Pipelined version = 2.26/(500 Mhz) = 4.5ns
CPU execution time for Non-Pipelined version = 1.0/(350 Mhz) = 2.8ns
The non-pipelined version is faster
b) Average CPI for Pipelined Version = (0.8*1 + 0.1*2 + 0.1*2.7) = 1.27
Average CPI for Non-Pipelined Version = (0.8*1 + 0.1*1 + 0.1*1) = 1.0
CPU execution time for Pipelined version = 1.27/(500 Mhz) = 2.54ns
CPU execution time for Non-Pipelined version = 1.0/(350 Mhz) = 2.8ns
The pipelined version is faster.