Smart Computing Review, vol. 4, no.

6, December 2014

481

Smart Computing Review

A Review of Manchester,
Miller, and FM0 Encoding
Techniques
Lalitha V and Kathiravan S
Dept. of ECE, Kalaignar Karunanidhi Institute of Technology / Coimbatore, Tamil Nadu, India- 641 402 /
{lalithakvn, kathiravan.sss}@gmail.com
* Corresponding Author: Kathiravan S

Received September 13, 2014; Revised November 23, 2014; Accepted November 30, 2014; Published
December 31, 2014

Abstract: Encoding techniques are becoming more important in communication. Techniques such
as Miller, Manchester, and FM0 encoding can be used in various applications. Each technique has
different operations based on their needs. Each encoding scheme should be used without losing any
of its parameters. The finite state machine can be used for all encodings, because at a time the input
has given the corresponding output can be occurred due to this. So speed can be increased. The
fully-reused VLSI architecture of FM0, Manchester, and Miller encoders has reduced the number
of transistors and maintains the DC balance. The simulation results of Xilinx indicate successful
functions.
Keywords: Manchester encoder, Miller encoder, FM0 encoder, FSM

Introduction

he types of encoding used in communication convert information into a form suitable for transmission. Encoding
techniques can also be used for security purposes. In general, different types of encoding can be used for serial
communication. There are many ways to encode the data such as Miller encoding, Manchester encoding, FM0, NRZ, FM1,
RZ, etc. This type of encoding is used on the transistor level, so it can be used with optical communication [1], minimizing
the critical path, area, delay, and buffer size by adding a minimum number of buffers [2]. A baseband processor such as a
UHF RFID Reader, PIE encoder, FM0 decoder, or Miller decoder are used for encoding and decoding purposes, achieving
higher efficiency and accuracy [3]. But in order to do this, it needs a high frequency clock [4]. The paper is organized as
follows: The description of the Manchester encoding technique is Section II. In Section III, we describe the Miller encoding
techniques. In Section IV, we give a description for FM0. In Section V, we give the results of a simulation of all encoders
with a finite state machine (FSM). In Section V, we talk about applications of these encoders. Finally, in Section VI we
give a conclusion and talk about future work.
DOI: 10.6029/smartcr.2014.06.006

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Encoding Techniques
Description of Manchester Encoding Technique
Manchester encoding is also called phase encoding. It can be used for a higher operating frequency. Manchester encoding
is a very common method and is probably the most commonly used. The signals can be transmitted serially. In Manchester
encoding the average power is always the same, no matter what data is transmitted. Compared to all other encoding
methods, Manchester code follows an algorithm to encode the data. It always produces a transition at the center of the bit. It
contains sufficient information to recover a clock. So if the data rate is twice, sufficient clock information can be recovered
from the data stream so that separate clocks are not needed. As a result, the electrical connection using Manchester code is
easily a galvanic ally isolator (it is the principle of isolating functional sections of electric systems to prevent current flow)
using a network isolator for simple one-to-one isolation transformation. Therefore, while transmitting the data, the number
of wires is minimized, which is used to reduce the noise and transmission power.
Logic 1 represents the transition from HIGH to LOW.
Logic 0 represents the transition from LOW to HIGH.
To obtain a high speed, provide a synchronized data source as the first clock pulse for input data. While transmitting the
data, it is a digital encoding in which data transmission bits are represented by transitions from one logic to another logic.
The length of each bit is set as default, and it consumes the signals as self-clocking. The direction of the transition decides
the state of the bit.
It is sometimes necessary to have a transition in the middle of a bit so that the transition obtained at the beginning
period is disregarded.

Figure 1. Manchester encoding

The operation of the Manchester encoder is an exclusive OR of the signal with the clock signal. Then, the rising edge
will be obtained when the bit value is zero and the falling edge is opposite case. It doesnt take on a zero value.
Table 1. Operation of Manchester encoding
Original data

Clock

XOR Manchester value

The detailed explanation of Manchester encoding is when the input is 0 and the clock is 0. Then, it produces a
corresponding output of zero. If the original data is 0 and the clock is 1, then the output is one. If the original data is given
as 1 and clock is 0, the corresponding output is one. When the original data is given as 1 and the clock is 1, the
corresponding output is zero.
The four states available are 00, 01, 10, and 11. There is also RST. A transition was obtained based on 1 and 0. In the
initial state, reset is 1, and then the next state will be 00. After that reset it will always be 0. When the input is 0 and the
current state is 00, the next state is 01. If the input is 1 and the current state is 00, the next state is 10. When the input is 0,
and the current state is 01, the next state is 01. And if the input is 1, and the current state is 01, next state is 11. When the
input is 0, and the current state is 10, the next state is 11. If the input is 1, and the current state is 10, the next state is 10.
When the input is 0, and the current state is 11, and the next state will be 00. Finally, if the input is 1, and the current state
is 11, the next state is 01.

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Figure 2. FSM for Manchester encoder

Table 2. For state machine diagram of Manchester encoder
Reset

Input

Current State

Next State

00

00

01

00

10

01

01

01

11

10

11

10

10

11

00

11

01

The main advantage is that the signal synchronizes itself, minimizes the error rate, and optimizes the reliability. The
drawbacks to this encoding are that more bits are needed to transmit in the Manchester encoding signal than the original
signal, and it needs more bandwidth.

Description of Miller Encoding Technique

Miller encoding is also known as delay encoding. It can be used for higher operating frequency and it is similar to
Manchester encoding except that the transition occurs in the middle of an interval when the bit is 1. While using the Miller
delay, noise interference can be reduced.
The block diagram has a d flip flop, t flip flop, NOT gate, and XOR gate. Where the input is A_in and CLK, then the
output is a Miller output.For example, if the input is 0 and the clock, given the XOR operation has done that, is A_in CLK ,
therefore 0 plus a positive edge clock produces the output as 0. Given to d flip flop, the clock has inverted, and after that
output is given to t flip flop it inputs asd flip flop output, which is 0. Then the TFF is toggle FF, which produces the Miller
output as 1.
The four states available are 00, 01, 10, 11. There is also RST. Transition is obtained based on 1 and 0. In the initial
state, reset is 1. Then the next state will be 00, and after this reset it will always be 0. When the input is 0, and the current
state is 00, the next state is 10. If the input is 1, and the current state is 00, the next state is 01. If the input is 0, and the
current state is 01, the next state is 10. And if the input is 1, and the current state is 01, the next state is 01. If the input is 0,

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and the current state is 10, the next state will be 11. If the input is 1, and the current state 10, the next state is 00. If the input
is 0, and the current state is 11, the next state will be 01. And if the input is 1, and the current state is 11, the next state is 10.

Figure 3. Block diagram for Miller encoder

Figure 4. FSM for Miller encoder

Table 3. For state machine diagram of Miller encoder
Reset

Input

Current State

Next State

00

00

10

00

01

01

10

01

01

10

11

10

00

11

01

11

10

Description for FM0 Encoding Technique

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FM0 is also known as Biphase space encoding. A transition is present on every bit and an additional transition may
occur in the middle of the bit. Here the data rate is twice. Sufficient clock information can be recovered from the data
stream so that a separate clock is not needed. Therefore, for transmission, the number of wires is minimized.

Logic 0 represents the transition in the center of the bit.

Logic 1 represents there is no transition from the center of bit.

This encoding data contains sufficient information to recover a clock from the data. It has to reach the DC balance and
enhance signal reliability. It is used to reduce noise and transmission power.

Figure 5. Block diagram for FM0 encoding

The block diagram has an XOR gate, DFF, inverter, and MUX. For example, the XOR gate has one input as feedback
that is 0, and another input as 1. This XOR output is given to DFF1, and it also has a CLK signal with an output of 1.
Another DFF2 has an input as 1 and CLK. The output is 1. Both DFF outputs are given to MUX, and also it has a CLK
with it that produces the output based on selection lines. If the selection line is 0, it produces the output as DFF1 as FM0
output. Otherwise, the selection line is 0 and produces an output as DFF2 or FM0 output.

Figure 6. FSM for FM0 encoder

The transition table for the abovementioned state diagram is as Table 4.

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Table 3. For state machine diagram of Miller encoder

Reset

Input

Current State

Next State

00

00

11

00

01

01

10

01

11

10

00

10

11

11

01

11

10

The four states of 00, 01, 10, and 11 are available, along with RST. The transition is obtained based on 1 and 0. The
initial state, reset, is 1. Then the next state will be 00. After the reset it will always be 0. When the input is 0, and the
current state is 00, the next state is 11. If the input is 1, and the current state is 00, the next state is 01. If the input is 0, and
the current state is 01, the next state is 10. If the input is 1, and the current state is 01, the next state is 11. When the input is
0, and the current state is 10, the next state is 00. If the input is 1, and the current state is 10, the next state is 11. If the input
is 0, and the current state 11, the next state is 01. And if the input is 1, and the current state is 11, the next state is 10.

Comparison Table for Manchester, Miller, and FM0 Encoding

Table 4. Comparison for Manchester, Miller, and FM0 encoding
Encoding

Minimum Pulse Width

NO of Transition

Normalized Average

Manchester

Tb/2

11

1/2

Miller

Tb

3.5/8

FM0

Tb/2

12

4.5/8

Figure 5. Block diagram for FM0 encoding

Simulation Results and Schematic Diagram

Figure 7. Simulation results for Miller encoding

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The simulation results for Miller encoding is shown in Figure 7. The input a is 1 and the clk is given as a rising edge which
produces the output as 1.

Figure 8. Manchester encoding

The simulation result for Manchester encoding is shown in Fig 8. The input a is 1 and the clk is given as a rising edge
which produces the output as 0.

Figure 9. FM0 encoding

The simulation result for FM0 encoding is shown in Figure 9. The input a is 0, and the CLK is given as a rising edge
which produces the output as 1.

Figure 10. Technology schematic for Manchester encoding

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Lalitha V et al.: A Review of Manchester, Miller, and FM0 Encoding Techniques

The above schematic is a technology schematic for a Manchester encoder which is used in FPGA. Here LUTS is used to
reduce the power consumption.

Figure 11. RTL schematic for Manchester encoder

The Manchester encoding of the RTL schematic is done in a behavior style using verilog. The function of the schematic
is implemented using the state parameters as clock and input data. The schematic in Figure 11 uses a very low amount of
hardware, and also minimizes the area.

Figure 12. Technology schematic for FM0 encoding

The above result shows the technology schematic for FM0. It is easy to implement and also includes the OBUF and
output. The schematic was obtained from a Xilinx synthesis tool.

Figure 13. RTL schematic for FM0 encoding

The FM0 encoding for the RTL Schematic is done in a behavior style using verilog. The functioning of the schematic is
implemented using the state parameters as clock and input data, gates, FF, and MUX. The above schematic uses very little
hardware and also minimizes the complexity.

Figure 14. Technology schematic for Miller encoding

The above result shows the technology schematic for Miller encoding. The schematic was obtained from Xilinx
synthesis tools. The look-up tables are used to reduce the power.
The Miller encoding of the RTL schematic is done in a behavior style using verilog. The function of the schematic is
implemented using the state parameters as clock and input data, TFF, DFF, and gates. The schematic in Figure 15 has an
easy transition level.

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Figure 15. RTL schematic for Miller encoding

Application
It can be used in many applications like library RFID management systems having advantages like high reliability,
automated materials handling, and long life. Likewise some other applications are E-passports, supermarkets, transportation,
and tracking.

Conclusion
The presented work exploits the design strategies of the entire circuits for Miller, Manchester and FM0 encoders, and a
finite state machine for all three encoders has been designed using verilog hardware description languages. This encoding
concept will be used in various applications as future work.

References
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Lalitha V et al.: A Review of Manchester, Miller, and FM0 Encoding Techniques

Lalitha V was born in Coimbatore, Tamilnadu, in 1991. She received a BE from the Department
of Electronics and Communication Engineering, Anna University Chennai, in 2013. She is
currently pursuing an ME with the department of VLSI DESIGN, Anna University Chennai. Her
areas of interest include VLSI Signal Processing, Wireless Communication, RFID, and Low
Power VLSI Design.

Kathiravan S received his BE in Electronics and Communication Engineering and ME in

Communication Systems Engineering from Anna University, Chennai. He also received his PhD
in Information and Communication Engineering from Anna University Chennai, Tamil Nadu. He
has more than 20 publications to his credit in peer-reviewed international journals and
conferences. His research interests are Super-resolution, Image de-noising, Image Segmentation,
Image Enhancement, VLSI signal Processing, Wireless Communication, RFID, and Low Power
VLSI Design.

Copyrights 2014 KAIS