Fundamentals of Signal and Power Integrity

Fundamentals of
Signal and Power Integrity

Christian Schuster
Distinguished Lecturer for the IEEE EMC Society 2012-13
Institute of Electromagnetic Theory
Hamburg University of Technology (TUHH)
Acknowledgements
Renato Rimolo-Donadio, Xiaomin Duan,
Sebastian Mller, Miroslav Kotzev,
Heinz-Dietrich Brns
Young Kwark, Xiaoxiong Gu, Mark Ritter,

Bruce Archambeault, Dale Becker,
Thomas-Michael Winkel, Hubert Harrer
and many others!
Christian Schuster 2
Abstract
This presentation will give an introduction to the fundamentals of
signal and power integrity engineering for high-speed digital
systems with a focus on packaging aspects. The presentation is
intended for an audience that has little or no formal training in
electromagnetic theory and microwave engineering.
Topics that will be addressed include lumped discontinuities,
transmission line effects, crosstalk, bypassing and decoupling, via
and power plane effects, return current issues, and measurement
techniques for Gbps links.
More information on current research projects at the Institute of
Electromagnetic Theory can be found at:
http://www.tet.tuhh.de/
A Birds Eye View on SI, PI & EMC

Driver
Via
PCB
Power Plane
Ground Plane
DC Power Supply
Receiver
Signal Transmission Issues:

Attenuation, Reflection, Dispersion, Interference, Crosstalk
Signal Transmission Issues:

Attenuation, Reflection, Dispersion, Interference, Crosstalk
Power Delivery Issues:

Voltage Drop, Switching Noise, Crosstalk
Power Delivery Issues:

Voltage Drop, Switching Noise, Crosstalk
Electromagnetic Compatibility Issues:

Near Field Coupling, Radiated Emissions
Electromagnetic Compatibility Issues:

Near Field Coupling, Radiated Emissions
SI + PI + EMC = Electrical Integrity
Outline
(1)
Hamburg and TUHH
(2)
Signal Integrity
(3)
Power Integrity
(4)
Vias and Return Currents
(5)
Measurement Techniques
(6)
Wrapping Up
(1)
Hamburg and TUHH
Hamburg University of Technology

TUHH
Downtown
Founded 1978
Approx. 6000 Students

Approx. 100 Faculty Members
Hamburg University of Technology

TUHH
What We Do at TUHH
B 0
B
E
t
D
H J
t
Maxwells Equations
Printed circuit board layout
(2)
Signal Integrity
Electrical Integrity of Digital Systems
Packaging of Digital Systems
Cable
Daughtercard
Housing / Chassis
IC (Transmitter)
IC (Receiver)
Package / Module
Socket
Connector
Connector
Backplane / Motherboard
Interconnect
(Link)
Connector
Effect of Interconnects
The ideal interconnect will simply delay the signal:
Tx
Rx
t
Any real interconnect will additionally change timing and amplitude:
Rx
Tx
Effect of Interconnects
The deviations in timing and amplitude are in general called:
Timing jitter or simply:
Amplitude noise or simply: NOISE
JITTER
Signal Bandwidth
f max
s(t )
1
0.3 .. 0.5
TR rise time
Maximum Frequency
s / 2
TB
TR
1
0.5
f0
2TB bit period
Fundamental Frequency
Maintaining Signal Integrity

1. Match terminations
2. Manage discontinuities
3. Reduce Coupling
4. Limit attenuation
5. Equalize signals
Effect of Terminations
Lets use the following interconnect (link) model:
Z 0, , l
ZS
u0
Transmitter
ZL
u1
u2
Interconnect
Receiver
??
Transmission Lines in Digital Systems

Microstrip
Line
Z0
87
5.98 h
ln
r 1.41 0.8 w t
(h = height of dielectric,
w = conductor width,
t = conductor thickness)
Stripline
(symmetric)
Z0
60
1.9 h
ln
r
0.8 w t
(h = height of dielectric,
w = conductor width,
t = conductor thickness)
Metal
Dielectric
Transmission Lines in Digital Systems

Typical trace length
5 75 cm
Velocity of propagation
150 000 km/s
Operating frequency
5 GHz
Corrsponding wavelength
3 cm
Delay 5 ns
up to 25 wavelengths on a trace!
Printed circuit board layout
Lets use the following interconnect (link) model:
Z 0, , l
ZS
u0
ZL
u1
u2
u2
const. and max. !
u0
??
Z0
a
ZS Z0
Z 0, , l
ZS
ZL
input acceptance
H exp( l )
Z 0, , l
ZS
ZL
input acceptance
TL transfer function
ZL Z0
rL
ZL Z0
Z 0, , l
ZS
t L 1 r L
ZL
input acceptance
load transmission
load reflection
ZS Z0
rS
ZS Z0
tS 1 rS
Z 0, , l
ZS
ZL
input acceptance
source transmission
load transmission
source reflection
load reflection
Z 0, , l
ZS
ZL
u2
a H tL
??
2
u0
1 H r L rS
Z 0, , l
ZL Z0
ZS
u2
aH
u0
ZL
ZS Z L Z0
u2 1
H
u0 2
Matched interconnect:
Voltage
lossless transmisson line

lossy transmisson line
Time
TD
Mismatched Interconnect:
Voltage
low source impedance
high source impedance
Time
2 TD
1 Z S 10 , Z 0 50 , Z L 1k
zero losses
2 Z S 50 , Z 0 50 , Z L 100
zero losses
3 Z S 50 , Z 0 50 , Z L 50
zero losses
4 Z S 100 , Z 0 50 , Z L 100
3
zero losses
5 Z S 10 , Z 0 50 , Z L 1k
non-zero losses
6 Z S 50 , Z 0 50 , Z L 50
non-zero losses
(all lines have a delay of 0.1 ns)
Matching Terminations
(2 TD TR )
Check your interconnect length
Check your interconnect impedance!
Match receiver input impedance!
Match transmitter output impedance!
!
Real World Interconnect (Link)
Data
Equalizer
+ Slicer
.
.
Data
Equalizer
Serializer
Tx
CDR
Deserializer
Clock & Data Recovery
Clock
Rx
The technology is typically CMOS with the links being voltage

mode, unidirectional, serial, point-to-point, and sourcesynchronous. For improved bandwidth equalization is typically used
in the Tx, Rx, or both.
Interconnect
(Link)
Connector
Effect of Lumped Discontinuities
Signal
Out
Signal
In
Source
Voltage
u1
50
Tx-Output
2.5
nH
Bond Wire
50
Rx-Input
u2
Received
Voltage

Signal
In
Signal
Out
Source
Voltage
u1
50
Tx-Output
50
1 pF
Via
Rx-Input
u2
Received
Voltage
Attenuation of high frequency signal components
Slowing down" of the edges of a digital signal

Step Response
u2(t) / u1(t)
Magnitude of u2 / u1
Frequency Response
t 1/w0 = 25 ps
f0 6.37 GHz
Frequency [GHz]
Time [ps]
Effect of Distributed Discontinuities

Z0
Z, ,l
Z0
1 inch, 45 Ohm mismatched transmission line at c0 /2
c
f
2.952GHz
4l
Frequency Response
(Scattering Parameters)
Overall Effect of Discontinuities
Port1
Port2
2nH
2nH
2nH
P=1cm
P=15cm
P=5cm
P=1cm
300fF
Z=48
300fF
Z=52
300fF
Z=48
300fF
Z=49
Managing Discontinuities
Avoid them!
Check their impact!
Minimize them ( 10 Ohm around 50 Ohm)!
Compensate them (difficult)!
Concentrate on the bottleneck!
!
Interconnect
(Link)
Connector
Effect of Coupling
Consider two transmission lines in close proximity:
(1) Input
(3) Near End
Aggressor Line (Active Line)
Victim Line (Quiet Line)
(2) Output
(4) Far End
Effect of Coupling
Consider two transmission lines in close proximity:
(1) Input
(2) Output
IC
UL
(3) Near End
(4) Far End
NEXT =
Near End Crosstalk
FEXT =
Far End Crosstalk
(sum of ind. and cap. crosstalk)
(difference of ind. and cap. crosstalk)
Effect of Coupling
For weak coupling (kL,C 0.25) it is found approximatively:
(1) Input
(2) Output
Effect of crosstalk
is usually small.
INPUT
U max
TR
TD
(3) Near End
(4) Far End

Polarity is equal
to input polarity.
TR
2 TD TR
Polarity also depends

on coupling coefficients.
TD TD TR
Effect of Coupling
For weak coupling (kL,C 0.25) it is found approximatively:
NEXT
U max
FEXT
max
kC k L TD
INPUT
U
max
2
T
R
INPUT
kC k L U max
(TD 0.5 TR )
(TD 0.5 TR )
kC kL TD
INPUT
U max
2
TR
It should be noted that these formulas do not take into account losses
on the lines or reflections from load mismatches.
Example for Coupling Coefficients

For two thin wires above infinite ground one can find:
diameter = d
C12
ln(1 (2h / a) 2 )
kC
C12
C11
2 ln( 4h / d )
Reducing Coupling
Increase line separation!
Decrease distance to ground!
Balance capacitive and inductive coupling!
Increase rise time!
Reduce coupling length!
Use differential signaling!
Differential Signaling
In a SINGLE-ENDED link
there is a common
(global) reference against
which the signal is
measured ("ground").
In a DIFFERENTIAL link
the reference is the
negative of the signal
itself (which has to be
transmitted as well).
(3)
Power Integrity
Effect of Common Power Delivery

IC #1
ZPDN
IC #2
U0
PDN = Power Delivery Network
Effect of Common Power Delivery

R
U0
uIC
iGate1, iGate2,
Du
uIC = U0 - Du
d
Du (t ) R iGate1 (t ) iGate1 (t ) ... L iGate1 (t ) iGate1 (t ) ...
dt
"DC-drop or IR-drop"
"DI-drop or DI-noise"
Maintaining Power Integrity

1. Decrease PDN impedance
2. Add decoupling
3. Add even more decoupling
4. Use several power supplies
5. Use on-chip VRMs
PDN Elements
High Power
DC Supply
Discrete
Decoupling
Capacitors
(various sizes)
IC incl.
Power/Ground Grid
& Integrated Decaps
Voltage
Regulator
Module
Printed Circuit Board incl.

Power/Ground Planes
Package incl.
Power/Ground
Planes
PDN Impedance
In frequency domain the standard PDN model looks like this:
ZPDN ( f )
u0
Du( f ) Dumax
Du( f )
ZIC ( f )
f " operating frequency range"
Z PDN ( f ) Z Target
PDN Impedance
A typical maximum ripple for ditigal systems is:
Dumax
maximum ripple 5% to 10%
u0
With a 10% value the following numbers can be obtained for
applications of the early 1990'ies: of 2000 and on:
u0 1.2 V
u0 5.0 V
iavg 120 A
iavg 1 A
u0 / iavg 0.01
u0 / iavg 5.0
Pavg 144 W
Pavg 5 W
Z Target 0.001 = 1 m !
Z Target 0.5
PDN Impedance
Is 1 m hard to achieve? How about 10 m? Let's see
Example:
The PDN consists of a simple copper wire of 2 mm radius in
theform of a flat rectangle with side lengths of 5 cm and 1 cm,
respectively.
with
Z PDN R 2 (wL) 2
R 0.7 m
L 40 nH
It turns out that 10 m cannot be maintained beyond 40 kHz!
Decreasing PDN Impedance
Use adequate copper cross sections!
Avoid big current loops!
Use power/ground planes!
Provide enough power/ground pins!
Decouple!
!
Decoupling
Based on the simple example from before:
R
U0
ZIC ( f )
Z PDN R jwL
jwL
(R = 0.7
m,
L = 40 nH)
(for large w )
Decoupling
we ask what a so called "decoupling" or "bypass" capacitor does:
R
U0
Z PDN
R jwL
1 jwRC w 2 LC
1
(for large w )
jwC
ZIC ( f )
R = 0.7 m
L = 40 nH
C = 1 mF
Decoupling
Heuristic explanation:
R
U0
ZIC ( f )
Frequency domain: Beyond the resonance frequency the capacitor

decouples the part of the PDN that lies "left" of him, i.e. the IC sees
only the impedance of the capacitor.
Time domain: The capacitor stores charges close to the IC that can
become currents needed for fast switching. It is like a "small battery".
Decoupling
While being beneficial at higher
frequencies decoupling increases
the PDN impedance in the vicinity
of the resonance frequency:
1 L
w0
R2
L C
Z PDN (w0 )
R = 0.7 m
L = 40 nH
C = 1 mF
Z PDN (w0 ) 57m
( L / C R 2 )*
1 L
R
R C
Hence, increasing the "damping"

(by increasing R and/or reducing
L/C) can be helpful:
(with Q 1 / R L / C the condition becomes Q 1)*
R = 10 m
L = 40 nH
C = 1 mF
Real Word Decoupling Capacitors

Unfortunately, there is no ideal capacitor available in the real world!
Ideal world:
and real world:
R is also is called the EQUIVALENT SERIES RESISTANCE

(ESR) and L the EQUIVALENT SERIES INDUCTANCE (ESL).
As a consequence any real world capacitor behaves approximately

like an inductor beyond its resonance frequency:
w0 1 / LC
More Decoupling
~
board-level
package-level
Amount of
charge, size
of decoupling
capacitance
chip-level
Speed of charge
delivery,
effective
frequency
Power/Ground Planes
Power/ground planes serve multiple purposes at the same time:
easy access to power and ground domains for mounted

components
a "natural" decoupling capacitor for PDN improvement
return current paths, i.e. they serve as reference conductors
shielding between different signal layers, i.e. they reduce

crosstalk
containment for internal EM fields, i.e. reduce EM emission
HOWEVER
Power/Ground Planes
they do show a resonant behavior:
Dielectric Filling
(r = 4)
Cpp 0 r
10 mil
Port
Power
Ground
A
11 nF
d
11 inch
11 inch
(1 inch = 2.54 cm,

1 mil = 0.001 inch)
Power/Ground Planes
The resonance frequencies are given by:
f mn
c0
r r
m n

2a 2b
(m, n 0,1, 2, ...)
Examples of standing wave patterns on a rectangular power/ground plane pair.
Adding Decoupling
Determine your target impedance!
Determine your operating frequency range!
Provide decoupling at all levels/frequencies!
Use parallel decoupling to reduce ESR/ESL!
Be wary of resonances!
!
(4)
Vias and Return Currents
The Problem With Vias

Signal Current
SignalVia
Load
Return Current
Ground Via
Load
A Physcis-Based Model for Vias

Current
Plane
viu
Cp
vi
vil
Cp
Plane
Via
Via Cross Section
i'iu
Zp
viu 1 Z pp vil
i
i
0
1
il
iu
Zpp
iil
vil 1
i 1 / Z
pl
il
Zp
v'il
0 viu
1 iiu
iiu
Zpp:
(Parallel Plate
Impedance)
v'iu 1
i ' 1 / Z
pu
iu
i'il
0 v'il
1 i'il
Where Do We Zpp Get From?

Port i (xi,yi)
Port j (xj,yj)
(a,b,d)
Current
Open
Plane
Edges
(a,b,0)
Voltage
z
Filling with and
(0,0,0)
jwd
Z ij (w )

ab m0 n 0
(a,0,0)
y
x
2 2 cos(k xm xi ) cos(k yn yi ) cos(k xm x j ) cos(k yn y j )

CmCn
2
2
2
k
xm
yn
m
n
k yn
a
b
Cm , Cn 1 for m, n 0 and
k xm
k w
2 otherwise
Including Striplines
Trace between planes:
2 Modes: Stripline + Parallel Plate
Stripline Mode
Parallel Plate Mode (pp)
Modal decomposition: find suitable transformation

matrices to diagonalize MTL equations
Including Striplines
h2
h1
h1
h1 h2
I ps1
V ps1
V
I ps2 k 2 Y stripline Y pp
(k k )Y stripline Y pp ps2
I
2
2
Vgs1
gs1
(
k
)
Y
Y
(
k
2
k
1
)
Y
Y
stripline
pp
stripline
pp

I
V
gs2
gs2
R. Rimolo-Donadio, H. D. Brns, C. Schuster, Including Stripline Connections into Network Parameter Based Via Models for
Fast Simulation of Interconnects, International Zurich Symposium on Electromagnetic Compatibility, Switzerland, Jan. 12-15, 2009
Stacking the Deck

Decap
Linterc.
Decoupling capacitor model

Port 1
Zpp
Port n
Cavity
representation
Ztl
S-Parameter
Matrix
Zpp
Ztl
Cavity
representation
Cavities joined by
segmentation
techniques
R. Rimolo-Donadio et al., Physics-based via and trace models for efficient link simulation on multilayer structures
up to 40 GHz", IEEE Trans. Microw. Theory and Techn., vol. 57, no. 8, p.p. 2072-2083, August 2009.
Comparison with Full-Wave Results

Full-wave model
6 Vias, 4 traces case
Magnitude
[dB]
of SS12
Magnitude of
14 [dB]
Centered striplines at two

levels, and thru vias in a 6
cavity stackup
Full-wave model
Frequency
Frequency [GHz]
[GHz]
Model
Model
FEM simulation
simulation
FEM
FIT simulation
simulation
FIT
Comparison with Measurements
119 vias (76 signal,

43 ground)
Assumption
of infinite
plates
14 differential
striplines (2D)
6 cavities
Terminations
Comp. time: < 3 min
Comparison with Measurements

|S13| [dB] - FEXT
|S12| [dB] - IL
Link 10 S3 Stripline
Measurement Link 10
Models capture the salient features of the

hardware response despite the drastic
model simplification
Measurement Link 17
Model Link 10
Model Link 17
Investigation of Via Return Currents

Effect of number
of ground vias:
GND via
1 GND via
2 GND vias
4 GND vias
6 GND vias
Investigation of Via Return Currents
Magnitude of S12 [dB]
Effect of number
of ground vias:
1 GND vias
2 GND vias
4 GND vias
6 GND vias
Frequency [GHz]
(5)
Measurement Techniques
Multiport Vector Network Analysis

Agilent Vector Network
Analyzer 8364C with
12-port extension at
Institute of Electromagnetic
Theory (TUHH)
12 ports
Bandwidth 10 MHz 50 GHz
Electronic calibration module

Advanced calibration software
Common Surface Launches
Surface Connectors
Access Vias
MICRO-PROBE
5 mm
5 mm
STRUCTURE UNDER TEST
STRUCTURE UNDER TEST
... but vias are usually a high

frequency bottleneck !
The Recessed Probe Launch (RPL)

MICROPROBE
MICROPROBE
STRUCTURE
UNDER TEST
Ground Vias
Signal
trace
No access vias
less distortion
probes closer to the structure under test
Ground pads with

U strap
RPL Error Box Extraction
Error boxes of RPLs from TRL calibration
(thru = 90 mil long, line = 220 mil long)

Problems with Via Arrays
13
mm
45
Via array
Via array
many vias at tight pitch!
92
The Interposer Concept

SMA or SMP Connectors
~ 1 cm
~ 1 cm
~ 1 mm
Signal pitch conversion from ~1 cm to ~1 mm
& easy multiport access
93
Typical Measurement Set-up

Multiport VNA
Interposer 1
Interposer 2
High speed serial links

94
Interposer Prototype
SMP
adapters
SMP
connectors
Interposer
LGA
Test
board
Hardware courtesy of
IBM YKT (Y. Kwark)
Clamping and pressure plates

95
Application to Link Measurement

Stripline connecting vias
from both via arrays
Hardware courtesy of
IBM YKT (Y. Kwark)
1st interposer connected to

the via array
2nd interposer connected to the

via array
96
(6)
Wrapping Up

The basic goals of EMC, SI, and PI for an electrical system are
complementary to each other.
SIGNAL INTEGRITY: insure

acceptable quality of signals within
SNR
System
Target
Frequency
POWER INTEGRITY: insure

acceptable quality of power
delivery within
EMC: insure acceptable level of

interference with the outside
PDN
Impedance
Target
System
Frequency
EMI
Target
System
Frequency
Contact Information
Prof. Dr. sc. techn. Christian Schuster
Institut fr Theoretische Elektrotechnik
Technische Universitt Hamburg-Harburg
Harburger Schloss Str. 20
21079 Hamburg, Germany
Tel: +49 40 42878 3116
WWW: http://www.tet.tuhh.de/
E-Mail: schuster@tuhh.de

Fundamentals of Signal and Power Integrity

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Fundamentals of

Signal and Power Integrity

Young Kwark, Xiaoxiong Gu, Mark Ritter,

A Birds Eye View on SI, PI & EMC

A Birds Eye View on SI, PI & EMC

Signal Transmission Issues:

A Birds Eye View on SI, PI & EMC

Signal Transmission Issues:

A Birds Eye View on SI, PI & EMC

Power Delivery Issues:

A Birds Eye View on SI, PI & EMC

Power Delivery Issues:

A Birds Eye View on SI, PI & EMC

Electromagnetic Compatibility Issues:

A Birds Eye View on SI, PI & EMC

Electromagnetic Compatibility Issues:

SI + PI + EMC = Electrical Integrity

Hamburg and TUHH

Vias and Return Currents

Hamburg and TUHH

Hamburg University of Technology

Approx. 6000 Students

Hamburg University of Technology

Electrical Integrity of Digital Systems

Packaging of Digital Systems

Packaging of Digital Systems

Any real interconnect will additionally change timing and amplitude:

Timing jitter or simply:

Amplitude noise or simply: NOISE

2TB bit period

Maintaining Signal Integrity

Transmission Lines in Digital Systems

Transmission Lines in Digital Systems

lossless transmisson line

low source impedance

high source impedance

Check your interconnect length

Check your interconnect impedance!

Match receiver input impedance!

Match transmitter output impedance!

Real World Interconnect (Link)

Clock & Data Recovery

The technology is typically CMOS with the links being voltage

Packaging of Digital Systems

Effect of Lumped Discontinuities

Effect of Lumped Discontinuities

Effect of Lumped Discontinuities

Attenuation of high frequency signal components

Slowing down" of the edges of a digital signal

Effect of Distributed Discontinuities

1 inch, 45 Ohm mismatched transmission line at c0 /2

Overall Effect of Discontinuities

Check their impact!

Minimize them ( 10 Ohm around 50 Ohm)!

Compensate them (difficult)!

Concentrate on the bottleneck!

Packaging of Digital Systems

(3) Near End

Aggressor Line (Active Line)

Victim Line (Quiet Line)

(4) Far End

(3) Near End

(4) Far End