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I. INTRODUCTION
A DDSM is a discrete-time system whose function is to re
quantize a discrete-amplitude input signal coarsely to produce
a lower resolution output signal. This requantization process
takes place within a negative feedback loop such that the
power of the resulting quantization noise is suppressed within
some signal band of interest [1]. Ideally the quantization noise
introduced by the DDSM is white and uncorrelated with the
DDSM's input sequence. In practice, however, the quantization
error often forms short and repeating patterns, giving rise to
spurious tones in the output spectrum.
Two classes of techniques have been developed to whiten
the quantization noise: stochastic and deterministic. Stochastic
techniques include the use of LSB dithering [2]-[4] and time
varying noise transfer functions [5]. Their goal is to make the
quantization noise asymptotically white and indpendent of the
modulator's input, thereby eliminating spurious tones in the
output spectrum. Deterministic techniques include the setting
of predefined initial conditions [6]-[8], using prime modulus
quantizers [9] and architectural modification [10], [11]. The
goal of these methods is to maximize the cycle length of
the quantization error signal, thereby causing the quantization
power per tone to be minimized.
In this work, we focus on a deterministic technique, namely
setting predefined initial conditions. It has been proven that an
irrational initial condition imposed on the first accumulator of
a third or higher order MASH DDSM driven by a rational
DC input guarantees a spur-free output spectrum [6]. In the
case of a fixed-point digital implementation, the authors of [6]
suggested the use of an odd number as an approximation to
an irrational initial condition. The authors of [7] performed
extensive simulations on various orders of MASH DDSMs
and error feedback modulators (EFMs) to extract an empir
ical design methodology based on setting predefined initial
479
y[n]
{ 1,
0,
v[n] <M,
v[n] 2:M.
(1)
x[n]
N
Fig. I.
where X(z) and Ez(z) are the Z-transforms of the input and
the quantizer error introduced by the [th stage. We can write
the negative of the quantization error from the [th stage in
ICECS 2010
where
a
b
4 n+10
(8)
6n2 +30n+35
(9)
C =
4 n3 +30n2 +70n+50
3n+6
e = 3n2 +12n+11.
x[nJ
Fig. 2. Block diagram of an zth order MASH DDSM incorporating a cascade
of EFMls
-ez[n]
Iz+
kl_1=O
IZ_ 1 +
k2
+. . . +
kl-2=O
L h +(k1 + I)X )
k1=O
modM,
(3)
22m+(3n+6)2m+3n2 +12n+11,
(4)
III.
FOURTH-ORDER
f(k+1,1)
( t f: f:
h +(k1 + I)X
) modM
31(22h+(3k+6)2h+3k2 +12k+11).
f(h, k+1)
(16)
22h+(3(k+1)+6)2h+3(k+1)2
+12(k+l)+11
22h+(3k+9))2h+3(k2 +2k+1)
+12(k+l)+11
(5)
22h+(3k+6)2h+3k2 +12k+11
+322h+3(2k+l)+12,
(n+1)(n+2)(n+3)(n+4 )
X
24
(n+l)(n+2)(n+3)
+
I1 modM.
6
=
(15)
-e4[n]
22 k +9 . 2k +26+322k +92k ,
MASH DDSM
-e4 [n]
(14)
modM
(13)
(12)
f(m, n)
IZ_
2
(10)
(11)
(6)
x
( Nl+aNl+bN4+c
24
Nl+dN4 +e
+
I1 ) - 0 modM,
6
N4
(7)
480
(17)
Q)
g.
a;
"0
-;; -100
:0
>-
l!'
'l':
rr
0.1 .---------,
-200
-300
U."'_'I"f
1111
-400 '-----.......
-3
10
0.08
0.06
c
o
<3
"
'"
0.04
-e5[n]
Lag Index
+3)(n+4)(n+5)
( (n+l)(n+2)(n120
X
(n+l)(n+2)(n+3)(n+4) )
+
I1 modM.
24
=
(19)
0.1
N5
0.08
gh
0.06
c
<3
"
0
0
S
0.04
(20)
where
0.02
0
==
b
c
-0.02
-0.04
d
e
-0.06
-1048576
-524288
524288
1048576
Lag Index
IV.
FIFTH-ORDER
MASH DDSM
481
5n+15
(21)
10n2 +60n+85
10n3 +90n2 +255n+225
4
5n +60n3 +255n2 +450n+274
4n+20
(22)
(23)
(24)
(25)
6n2 +30n+35
(26)
(27)
0.1
0.08
0.06
c
0
<)
Qi'
Ci
E
:s
-50
1j
-1 00
.......... .:::
"
.
. ..... .
-0.02
-0.04
-0.06
>-
Q)
0.02
0
:;
<{
50
0.04
-1048576
-1 50
-524288
-200
-250
({
-300
524288
1048576
Lag Index
"
11
------------
-350 --------------3
10
TABLE I
CYCLE LENGTHS WITH PREFERRED INITIAL CONDITIONS FOR EFMs
WITH WORD LENGTH N (7)
MASH
Minimum
Maximum
Initial
Order m
Cycle Length
2N+1
Cycle Length
2N+2
Condition
4
5
2N+2
2N+2
odd
odd
0.1
0.08
REFERENCES
c
0
<)
0
:;
<{
0.06
0.04
0.02
-0.02 L-___________----'
1048576
-1048576 -524288
o
524288
Lag Index
V. CONCLUSION
In this work, we have verified mathematically the empirical
results presented in [7] for fourth- and fifth-order MASH
DDSMs. For an odd initial condition on the first accumulator
of the fourth- and fifth-order modulators, the minimum and
maximum cycle lengths are given in Table I, where N is the
wordlength of the modulator. In the case of the fourth-order
MASH DDSM, the maximum cycle length is achieved for
odd inputs. In the case of the fifth-order MASH DDSM the
maximum cycle length is achieved for all inputs.
ACKNOWLEDG MENT
482