Unit-3

Dr B Lakshmi
SENSE

Basic Flip Flop

Sequential Logic

Timing Aspect
A Sequential logic is said to be functionally
correct if it meets both functional and timing
goals
Functional verification
Logical correctness of the circuit

Timing verification
Intrinsic or propagation delay

t2-t1 is called intrinsic delay of the gate or propagation delay

 Clock to Q delay
Time difference from the time at which active
clock edge happens to the time at which a stable
output is available at the Q pin of the flip flop is
the intrinsic delay or clock to Q delay

Meta stable state is where the output is

unpredictable
Window around the clock edge where the
input signal has to be stable
Window is defined by set up and hold time

 Set up time
Minimum time for which the data input must be
stable before the clock transition

Hold time
Minimum time for which the data input must be
stable after the clock transition

Binary Counter

 If the clock period is less than the time

needed to generate the combinatorial output,
flop will not capture the correct value
Hence clock period should be higher than the
largest of the three equations generation time

Static Timing Analysis (STA)

It is the process of verifying the timing
requirement of a sequential circuit
Called static analysis because the external
inputs for the circuit are not dynamically
changed unlike functional testing using test
vectors

 Sequential circuits can be a set of flops, each

of which has a combinational cluster at their
inputs
For every flop (FF1) there is a set of logical
paths and each path has a source flop at the
starting point
All these paths converge into the D input of
the flop FF1 making combinatorial cluster
(logical cones)
Longest path in this cone will determine the
frequency of operation of the circuit

 For a given frequency of operation for the

logic, combinatorial delays b/w the source and
destination flops must be less than the clock
period for the proper functioning of the logic
Following relation has to be satisfied for the
destination flop to capture the logic value
correctly
T Clock period
Tpd- Propagation delay
Tsu Set up time
Tcq- Clock to Q delay

 Tsu_margin is included in the above eqn

I/p at the destination flop has to be held at
the same value for at least equal to the hold
time requirement of the flop
Hold check is done at one clock edge before
the edge at which set up check is done
If the circuit meets the hold check at this edge
then for every clock edge, the hold time will
met

Clock Skew
Clock is not ideal one
Rising edge does not appears exactly at the
same time all over the digital circuit
Metals are used to connect the various flops
to make clock connections
Clock connection in an IC is called clock tree
It is made up of clock buffers to balance the
load on each branch of tree, reducing the
skew
Difference in the arrival of time of clock in
various branches

Process Variations
Electrical characteristics of the wafer will vary
w.r.t process, voltage and temperture
This alters the electrical properties of the
wafer- process variation
Temperature also affects the operation of the
device
PVT variations are due to the physical nature
of silicon
These affect the timing parameters, making to
fluctuate within a range of values

Effect of Skew and PVT Variations

Clock at source and destination flops are
skewed
This variation is represented by a min value
and max value
Min value corresponds to the earliest time of
arrival of clock at the destination flop
Max value corresponds to the latest time at
which the clock is seen at the destination flop
This is called Clock Uncertainty

 Data Uncertainty
Data while traversing thro the combinational logic
will experience a delay and it has min and max
values depending on the PVT values

 Set up margin
Earliest capturing clock edge and the latest time
when data can change will indicate the worst
timing for the set up

Hold margin
Latest edge of the clock and the earliest time at
which the data changes will give the worst timing
of hold

 For set up calculations,

Tdata(max) is the worst case data path delay
Tclkskew(min) is the best case clock path delay
Apply maximum timings

For hold calculations,

Tdata(min) is the best case data path delay
Tclkskew(max) is the worst case clock path delay
Apply minimum timings

Example Analysis

Critical Path
Longest path delay is called critical path
It limits the system performance
It not only tells the system cycle time but also
what part of combinational logic must be
changed to improve the system performance
Only way to reduce the delay is to speed up a
gate on its critical path
Done by increasing the transistor sizes or
reducing wiring capacitance
Redesigning the logic along the critical path to
use a faster gate configuration

Critical Path-Examples

Slack
It is defined as the difference between actual
or achieved time and the desired time for a
timing path
For timing path, slack determines if the design
is working at specified speed or frequency

Timing exceptions
Most designs have paths that exhibit timing
exceptions
Logic may contain multi cycle paths or false
paths
To analyze the design, Prime Time (PT) is used

Prime Time (PT)

It is a stand-alone tool by Synopsys used to
perform STA on full chip level design
It checks the design for the required
constraints governed by design specifications
It performs the comprehensive analysis of the
design
It provides Tcl interface for analysis and and
debugging of designs

Multi-cycle Path
They require more than one clock cycle to
propagate
It cannot be inferred by the timing tool
It is specified by the designer so that the
analyzer can mark the path and correctly
compute the timings
A start point, end point and/or through point
is specified along with the number of allowed
clock cycles

 PT is used for multi-cycle path design

Data may take more than one clock cycle to
reach its destination
Amount of time taken by the data to reach its
destination is governed by the multiplier value

Defining Relationship for a single

Clock

 A multiplier value of 2 is used to inform PT

that the data latching occurs at regB after an
additional clock pulse
In case of generated clocks, PT does not
automatically determine the relationship
between the primary clock and derived clock
even if create_generated_clock command is
used

 For separate clock with different frequencies,

set_multicycle_path command is used to
define the relationship between these clocks
To specify a multicycle path between regA and
regB the command used is

Defining Relationship between

Separate Clocks

False Path
It is identified as a timing path that does not
propagate a signal
Above command does not disable the timing
arc of any cell, it removes the constraints of
the identified path
If timing analysis is performed on the false
path, an unconstrained timing report is
generated

Probelms