07 FF Registers Counters PDF

Chapter 7
Flip-Flops, Registers,
and Counters,
Arry Akhmad Arman
School of Electrical Engineering and Informatics
Institut Teknologi Bandung
Last Update : September 2010
School of Electrical Engineering and Informatics ITB, 2010, Arry Akhmad Arman
7.0
Basic Understanding
Types of Digital Circuit

Combinational
Se
Digital Circuit
Digital Circuit
Synchronous
Se
Sequential
Se
Digital Circuit
Asynchronous
Se
3
Combinational vs Sequential Circuit (1)

Fix output for
certain input
combination,
represented by
Truth Table
NO Fix output
for SAME input
combination.
Combinational
Circuit
Sequential
Circuit
4
Combinational vs Sequential Circuit (2)

No Memory!
No Feedback
line!
There is
Memory!
There is
Feedback line!
Dinamic
characteristic,
Represented by
STATE DIAGRAM!
Combinational
Circuit
Static
characteristic,
Represented by
TRUTH TABLE!
Sequential
Circuit
5
States in Sequential Circuits

Rangkaian
Sekuensial
Sinkron
A(H)
B(H)
C(H)
Timing Diagram
waktu
A B C
0 1 0
Variabel-variabel STATE
0 1 1
1 0 0
PREVIOUS STATE
1 0 1
1 1 0
PRESENT STATE pada suatu saat
1 1 1
0 0 0
0 0 1
NEXT STATE
6
Memory Element
in Sequential Circuit
Memory is an important element in
Sequential Logic Circuit
Set
Sensor
Reset
Memory
Element
On Off
Alarm
Type of Memories
[different input lines]
Q
Memory
J
K
K
Memory
Clock
Q
Memory
K
Preset
Clear
Memory
Clock
8
Memory Implementation
Simple,
Uncontrolled
Controlled
Memory
7.1
Basic Latch
10
10
Simple Controllable
NOR Memory
Q=0
if Reset=1
Q=1
if Set=1
11
NOR Memory
R
Qa
Qb
S
(a) Circuit
t1
t2
S R
Qa Qb
0
0
1
1
0/11/0
0 1
1 0
0 0
0
1
0
1
(no change)
(b) Truth table

t3
t4
t5
t6
t7
t8
t9
t10
1
R
0
1
S
Qa
0
1
?
0
Qb
1
?
0
Time
(c) Timing diagram
12
7.2
Gated SR Latch,
Flip-Flop
7.7
13
13
Gated SR Latch
Q
Clk
Clock!
S or R active if
clock active
Q
S
S
(a) Circuit
Clk
1
Clk S
Q( t + 1 )
Q(t) (no change)
Q(t) (no change)
0
1
Q
0
Q
Previous
NOR Memory
(b) Truth table
0
Time
(c) Timing diagram
14
Gated SR Latch with NAND Gates

Gated Latch is a basic latch that includes input
gating and a control input signal.
15
Gated D Latch (D Flip-Flop)

While clock active,
Q always follows D (D transparent to Q)
Clk
Q(t+1)
Q(t)
16
Gated T Latch (T Flip-Flop)

Clk
Q(t+1)
Q(t )
Q(t )
Q(t )
When clock active and T

active for long duration,
there is an oscillation in Q
output!
Notes:
Dalam CPLD MAX7000
terdapat configurable FF
yang dapat diset menjadi
D-FF atau T-FF
17
Gated JK Latch (JK Flip-Flop)

D = JQ + K Q
Clk
J-K
XX
Q(t+1)
Q(t )
00
Q(t )
01
10
11
Q(t )
18
Effects of Propagation Delays

tsu = setup time
th = hold time
During tsu+th,
D should be
stable
Typical CMOS values

tsu = setup time = 3ns
th = hold time = 2 ns
t su
th
Clk
D
Q
19
Master Slave D Flip-Flop
Pada FF biasa, perubahan output Q

selalu dipengaruhi input selama
CLOCK aktif.
Pada Master Slave D-FF, digunakan
2 buah FF dengan clock yang saling
komplemen.
Pada saat Clock aktif, D
mempengaruhi Qmaster, tetapi tidak
mempengaruhi Qslave.
Pada saat clock tidak aktif, clock
untuk Ffslave menjadi aktif, sehingga
Qmaster diteruskan ke Qslave.
20
Edge-Triggered D Flip-Flop
Pada edge triggered FF,
perubahan di sisi output
hanya terjadi pada saat
sisi naik/turun clock.
Pada negative edge triggered,
perubahan terjadi pada saat
clock berubah dari HV ke LV.
Pada positive edge triggered,
perubahan terjadi pada saat
clock berubah dari LV ke HV.
21
Pulse triggered
Comparison
Rising
edge triggered
Falling
edge triggered
Perhatikan standar
simbol untuk jenis
clock yang berbeda!
Pulse trigger, ada

daerah transparan
Rising edge trigger
Falling edge trigger
22
All Possibilities
Positive
Pulse
Trigger
Negative Pulse
Trigger
Rising Edge
Trigger
Falling Edge
Trigger
D-FF
Positive Pulse
Trigger D-FF
Negative Pulse
Trigger D-FF
Rising Edge
Trigger D-FF
Falling Edge
Trigger D-FF
T-FF
Positive Pulse
Trigger T-FF
Negative Pulse
Trigger T-FF
JK-FF
Positive Pulse
Trigger JK-FF
Negative Pulse
Trigger JK-FF
Rising Edge
Trigger T-FF
Falling Edge
Trigger T-FF
Rising Edge
Trigger JK-FF
Falling Edge
Trigger JK-FF
23
23
FF with Clear and Preset

(Master Slave D-FF)
Preset
D
Clock
Clear
(a) Circuit
Preset untuk memaksa

Q menjadi aktif (logika 1)
Preset
D
Q
Q
Clear
Clear untuk memaksa

Q menjadi tidak aktif
(logika 0)
(b) Graphical symbol
24
FF with Clear and Preset

(Positive Edge Triggered D-FF)
Preset untuk memaksa

Q menjadi aktif (logika 1)
Clear untuk memaksa
Q menjadi tidak aktif
(logika 0)
25
7.8
Registers
26
26
Shift (only) Register
Data bit dari saluran input

ditransfer bit per bit, secara
bertahap dari kiri ke kanan
sampai ke saluran output.
Data ditransfer (digeser)
setiap kali clock aktif.
27
Parallel-Access Shift Register
Choose
mode!
28
7.9
Counters
29
29
Asynchronous Counter
(case: a three-bit up-counter)
1
Clock
Q
Q0
Q
Q
Q1
Q2
Clock
Q0
Q1
Q2
Count
000
001
010
011
100
101
110
111
000
30
Asynchronous Counter
(case: a three-bit down-counter)
1
Clock
Q
Q0
Q
Q
Q1
Q2
Clock
Q0
Q1
Q2
Count
000
111
110
101
100
011
010
001
000
31
Synchronous Counter
(case: a three-bit synchronous up-counter)
Clock
cycle
T0 =1
T 1 = Q0
T 2 = Q0Q1
T 3 = Q0Q1Q2
...
Tn = Q0Q1 L Qn 1
0
1
2
3
4
5
6
7
8
Q2 Q1 Q0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Q1 changes
Q2 changes
32
Synchronous Counter
(case: a four-bit synchronous up-counter)
1
Q0
Clock
Q1
Q
Q2
Q
Q
Q3
Q
(a) Circuit
All clock lines
connected
together
Clock
(b) Timing diagram
Q0
Q1
Q2
Q3
Count 0
10 11
12 13
14 15
33
Inclusion of
Enable and Clear Capability
1
Clock
Q
Q0
Q
Q1
Q
Q2
Q
Without
Enable and Clear
Q
Q3
Q
With
Enable and Clear
Enable
Clock
Q
Q
Q
Q
Q
Q
Q
Q
Clear
34
Synchronous Counter
with D Flip-Flop
D0 = Q0 = 1 Q0
D1 = Q1 Q0
D2 = Q2 Q1Q0
D3 = Q3 Q2Q1Q0
35
Counter with
Parallel-Load Capability
36
7.10
Reset Synchronization
37
37
Enable
D0
Q0
D1
Q1
D2
Q2
Load
Clock
Clock
A modulo-6
counter
with
synchronous
reset
(a) Circuit
Clock
Q0
Q1
Q2
Count 0
(b) Timing diagram
38
When Q0=1
and Q2=1 ,
Data=000
loaded
Enable
D0
Q0
D1
Q1
D2
Q2
Load
Clock
Clock
A modulo-6
counter
with
synchronous
reset
(a) Circuit
Clock
Q0
Q1
Q2
Count 0
(b) Timing diagram
39
Clock
Q0
Q1
Q2
Reset
(Clear)
line!
(a) Circuit
A modulo-6
counter
with
asynchronous
reset
Clock
Q0
Q1
Q2
Count 0
(b) Timing diagram
40
7.11
Other Types of
Counters
41
41
BCD Counter
Reset after 9,
enable next digit
to count.
Reset
after 9
42
BCD Counter
BCD
to
7-Segment
Converter
BCD
to
7-Segment
Converter
43
Type of 7-Segments
44
Common Anode & Cathode
45
Ring Counter
(n-bit Ring Counter)
feedback line
When started, all FF

will be reset, except
the most left. Initial
=1000
1000
0100
0010
0001
46
Ring Counter: Another Choice!

(4-bit Ring Counter)
1000
0100
0010
0001
00
01
10
11
47
Johnson Counter
One bit change

between sequence!
Feedback line
is taken from
complement line
0000
1000
1100
1110
1111
0111
0011
0001
0000
12
14
15
48
7.12
Using Storage Elements
with CAD Tools
49
49
Three Type of Storage elements

in a schematic
50
Gated D Latch
generated by CAD Tools
51
Implementation of
Fig 7.31
in CPLD
52
Timing Simulation
53
Instantiating of D-FF
from a package
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY altera ;
USE altera.maxplus2.all ;
ENTITY flipflop IS
PORT ( D, Clock
Resetn, Presetn
Q
END flipflop ;
: IN
: IN
STD_LOGIC ;
STD_LOGIC ;
: OUT
STD_LOGIC ) ;
ARCHITECTURE Structure OF flipflop IS

BEGIN
dff_instance: dff PORT MAP ( D, Clock, Resetn, Presetn, Q ) ;
END Structure ;
54
End of slides
55

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Chapter 7

Types of Digital Circuit

Combinational vs Sequential Circuit (1)

Combinational vs Sequential Circuit (2)

States in Sequential Circuits

PRESENT STATE pada suatu saat

(b) Truth table

Q(t) (no change)

Q(t) (no change)

(b) Truth table

Gated SR Latch with NAND Gates

Gated D Latch (D Flip-Flop)

Gated T Latch (T Flip-Flop)

When clock active and T

Gated JK Latch (JK Flip-Flop)

Effects of Propagation Delays

Typical CMOS values

Master Slave D Flip-Flop

Pada FF biasa, perubahan output Q

Pulse trigger, ada

Rising edge trigger

Falling edge trigger

FF with Clear and Preset

Preset untuk memaksa

Clear untuk memaksa

(b) Graphical symbol

FF with Clear and Preset

Preset untuk memaksa

Shift (only) Register

Data bit dari saluran input

Parallel-Access Shift Register

(b) Timing diagram

(b) Timing diagram

(b) Timing diagram

(b) Timing diagram

Common Anode & Cathode

When started, all FF

Ring Counter: Another Choice!

One bit change

Three Type of Storage elements

ARCHITECTURE Structure OF flipflop IS

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