IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO.

3, MARCH 2013

429

A Dual-Junction Single-Photon Avalanche

Diode in 130-nm CMOS Technology
Robert K. Henderson, Eric A. G. Webster, and Lindsay A. Grant

AbstractA dual-junction single-photon avalanche diode structure is reported in a 130-nm low-voltage CMOS technology. The
device comprises two stacked avalanche multiplication regions
with virtual guard ring constructions. An 8.6-m-diameter p-well
is placed within a 12.3-m-diameter deep n-well. At 3-V excess
bias, the junctions operate with median dark count rates of 10 and
5 kHz and photon detection efficiencies of 32% at 450 nm and 29%
at 670 nm, respectively. We demonstrate that the junction at which
a photon is detected can be uniquely distinguished by the dead
time of the Geiger mode pulse allowing spectral discrimination by
simple digital circuitry.
Index TermsCMOS, photodiode, photon detection efficiency
(PDE), single-photon avalanche diode (SPAD).
Fig. 1. (a) Device cross section. (b) Micrograph.

I. I NTRODUCTION

TACKED junction photodiodes are well known in CMOS

image sensors where they allow spectral discrimination
without Bayer pattern color filters, enhancing effective image
resolution and detection efficiency [1], [2]. Interest is growing
in CMOS single-photon avalanche diodes (SPADs) due to their
high sensitivity and time resolution [3]. A dual-junction CMOS
SPAD structure has been reported recently for biological imaging of spectrally separated fluorescent probes [4], [5]. In this
structure, the two junctions were not fully stacked; the deeper
junction exhibited peripheral breakdown leading to low fill
factor and high dark count due to surface breakdown.
In this letter, we report a dual-junction SPAD implemented in
130-nm CMOS imaging technology [6]. This is the first singlephoton detector in which both avalanche multiplication regions
are vertically stacked beneath the surface of the silicon. This
has been accomplished by employing a recently proposed deepn-well guard ring construction forming a deep avalanche diode
with the p-substrate [7]. The deep n-well can also enclose a
conventional shallow junction avalanche diode structure [8].
Suitable biasing results in avalanche detection at the two vertically disposed high-field-breakdown regions.
The device inherits the low dark count rate (DCR), high
photon detection efficiency (PDE), and distinct spectral reManuscript received December 10, 2012; revised December 21, 2012;
accepted December 23, 2012. Date of publication January 21, 2013; date
of current version February 20, 2013. This work was supported in part by
The University of Edinburgh and in part by STMicroelectronics (R&D) Ltd.,
Edinburgh, U.K. The review of this letter was arranged by Editor W. T. Ng.
R. K. Henderson and E. A. G. Webster are with the Institute for Integrated
Micro and Nano Systems, School of Engineering, The University of Edinburgh,
Edinburgh EH9 3JL, U.K. (e-mail: robert.henderson@ed.ac.uk).
L. A. Grant is with STMicroelectronics (R&D) Ltd., Edinburgh EH12 7BF,
U.K.
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2012.2236816

sponses of the constituent diodes [7], [8]. The DCR has been
reduced from a few megahertz in [3] to a few kilohertz while
increasing PDE to around 40% at 3-V excess bias. Compared
to buried double-junction (or triple-junction) photodiode structures [2], these avalanche detectors offer high sensitivity (few
millilux noise equivalent illumination) and high temporal resolution (hundreds of picoseconds of jitter). The structures are
compatible with low-voltage CMOS technologies and include
integrated quench, level shift, and buffer circuitry. In addition,
we demonstrate a novel approach to spectral discrimination of
single-photon events through thresholding of pulse dead time.
II. D EVICE S TRUCTURE
Fig. 1(a) shows the device cross section taken through the
center of the circular device [Fig. 1(b)]. The outer diameter
of the n-well measures 16 m. A metal shield covers all but
the inner 12.3-m-diameter region in which is enclosed an
8.6-m-diameter p-well. The p-well is surrounded by a virtual
guard ring formed by blocking peripheral n-well formation.
The retrograde doping profile of the deep n-well favors breakdown at the buried interface between the p-well and the deep
n-well [8]. A second deeper breakdown region is formed at
the buried interface of the deep n-well and the p-substrate.
A second virtual guard ring is created by blocking peripheral
p-well formation and allowing the p-epitaxial doping profile
to favor breakdown at depth [7]. A 400-k polysilicon quench
resistor, 14-fF metaloxidemetal capacitor, and output buffer
are integrated beside the SPAD.
Fig. 2 shows the equivalent circuit of the SPAD test structure.
The p-substrate to deep-n-well diode constitutes the deep redsensitive junction and has its anode at ground. The shallow
blue-sensitive junction between the p-well and deep n-well
can be freely biased by adjusting the p-well voltage Vpw . Both
detectors share a common cathode biased via a quench resistor

0741-3106/$31.00 2013 IEEE

430

IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 3, MARCH 2013

Fig. 2. Equivalent circuit schematic.

Fig. 4.

Histogram of pulse duration at 650 nm.

Fig. 5.

Mean pulse duration versus wavelength.

Fig. 3. PDE. i. DNWPsub. ii. DNWPW. iii. Both DNWPsub and

DNWPW. iv. Difference of (iiii.) scaled to the active area of the DNWPW
junction.

Rq to a high voltage Vhv . Avalanches will be detected by

a falling edge of pulses occurring at this node. A capacitive
coupling element Cc is employed to level shift the high-voltage
pulse to the low-voltage levels tolerated by standard CMOS
logic. A PMOS reset transistor Mp maintains the dc voltage
at the input of the digital buffer.
The breakdown voltages of the p-substrate and p-well junctions are 20 and 13.7 V, respectively. To activate only the
p-substrate SPAD, Vhv is raised above 20 V and Vpw is set
to a voltage greater than (Vhv 13.7 V). Conversely, if only
the p-well SPAD is to be activated, Vpw is set to 0 V, and
Vhv is adjusted in the range 13.720 V. Both junctions can
be activated simultaneously by setting Vhv > 20 V and Vpw <
(Vhv 13.7 V). The output buffer supply is 3.3 V, and so, the
onset of triggering occurs at logic threshold of 1.65 V above
breakdown.
III. R ESULTS
The deep-n-wellp-substrate (DNWPsub) and deep-n-well
p-well (DNWPW) SPAD junctions have been individually
characterized in previous publications for IV , dark count,
device jitter, and afterpulsing [6], [7]. We focus on those
characteristics which pertain to the novelty of stacking the two
junctions. The median DCRs of ten devices tested were 5 and
10 kHz for the DNWPsub and DNWPW, respectively.
Fig. 3 shows the PDE of the SPAD in different bias configurations. The PDE of the DNWPsub diode is evaluated
by biasing the deep n-well at Vhv = 23 V while maintaining
the DNWPW diode below breakdown by setting Vpw = 10 V

(13-V bias). The peak PDE is 29% at 670 nm, calculated assuming a 12.3-m active diameter. The PDE of the DNWPW
diode is determined by setting the DNW bias to Vhv = 16 V
and the p-well bias to Vpw = 0 V. This is below the breakdown
of the DNWPsub diode but above that of the DNWPW
diode. The peak PDE is 32% at 450 nm based on an 8.6-m
active diameter.
Both diodes are activated by setting Vhv > 23 V and Vpw =
7 V; therefore, the DNWPW SPAD has a total bias voltage of
16 V (excess bias of 2.3 V). Pulses at the device output now
represent breakdown of either SPAD junction. The peak PDE
of the combined junctions is 39% at 650 nm. The PDE in this
configuration is exactly the sum of the individual PDEs of the
DNWPsub and DNWPW at 23 and 16 V, respectively.
Determination of the junction that has undergone breakdown
is possible by monitoring the sign of pulses on a resistor biasing
Vpw [3]. We demonstrate a new approach based on the duration
of the SPAD dead time. Fig. 4 shows a histogram of pulse durations at increased bias voltages across the DNWPsub diode
of 25 V and DNWPW diode of 18 V. The pulse duration of
the DNWPW junction peaks at around 48 ns, while that of the
DNWPsub junction occurs at 33 ns. When both junctions are
biased above breakdown, the pulse duration histogram shows
two distinct peaks at these values.
Fig. 5 shows that when the junctions are active individually
there is little variation of the mean pulse duration with wavelength but a significant shift when both junctions are active

HENDERSON et al.: DUAL-JUNCTION SINGLE-PHOTON AVALANCHE DIODE

431

DNWPW junction. The threshold duration of 40 ns is chosen

approximately midway between the two peaks in Fig. 6. The
PDE is calculated by dividing each of these two count values
by the measured optical power incident on the relevant diode
active area and compares very closely to that in Fig. 4. A D-type
flip-flop can act as a pulse duration comparator by connecting
the SPAD output to the D-input and a delayed version to the
clock input. A desired duration can be set by the length of a
buffer-chain delay line.
IV. C ONCLUSION

Fig. 6. Histogram of pulse durations at various wavelengths for Vhv = 25 V

and Vpw = 7 V (25 V across DNWPsub and 18 V across DNWPW).

A dual-junction SPAD implementing fully stacked multiplication regions in a low-voltage CMOS process offers a new
device for biophotonics research, machine vision, and color
sensing. Simple on-chip digital electronics can be used to
discriminate between photons detected by either junction. The
requirement for quench resistor, coupling capacitor, and timeduration comparator will limit the fill factor in array implementations of the detector.
ACKNOWLEDGMENT
The authors would like to thank STMicroelectronics, Crolles,
France, for fabricating the devices and S. Pellegrini and
B. Hearn for measurement assistance.
R EFERENCES

Fig. 7. Reconstructed spectral PDE plot thresholding pulse durations at 40 ns.

The junctions are biased at Vhv = 25 V and Vpw = 7 V.

simultaneously. The mean pulse duration of the dual junction

drops because the proportions of short pulse durations (due to
detections at DNWPW) and long pulse durations (due to detections at DNWPsub) are varying as a function of absorption
depth and wavelength.
Fig. 6 shows in more detail the variation of the pulse duration
histograms at a few wavelengths under conditions Vhv = 25 V
and Vpw = 7 V. At 450 nm, the heights of the peaks at 33 and
48 ns are almost equal, while above 650 nm, the 33-ns peak
far exceeds that at 48 ns. The SPAD pulse durations are related
to the recharge time constants due to the quench resistance and
junction capacitances as well as the time to cross an inverter
threshold set by the excess bias voltage. The two populations
may therefore be explained by the different capacitances and
excess bias voltages of the two junctions.
Fig. 7 shows that the spectra at either junction can be
reconstructed by counting pulses in two bins: those below
40 ns for the DNWPsub junction and those above 40 ns for the

[1] R. B. Merrill, Color separation in an active pixel cell imaging array using
a triple-well structure, U.S. Patent 5 965 875, Oct. 12, 1999.
[2] S. Feruglio, G.-N. Lu, P. Garda, and G. Vasilescu, A review of the CMOS
buried double junction (BDJ) photodetector and its applications, Sensors,
vol. 8, no. 10, pp. 65666594, Oct. 2008.
[3] M. Ghioni, A. Guilinatti, I. Rech, F. Zappa, and S. Cova, Progress in
silicon single-photon avalanche diodes, IEEE J. Sel. Topics Quantum
Electron., vol. 13, no. 4, pp. 852862, Jul./Aug. 2007.
[4] H. Finkelstein, M. J. Hsu, and S. C. Esener, Dual-junction singlephoton avalanche diode, Electron. Lett., vol. 43, no. 22, pp. 12281229,
Oct. 2007.
[5] P. Schwille, F. J. Meyer-Almes, and R. Rigler, Dual-color fluorescence
cross-correlation spectroscopy for multicomponent diffusional analysis in
solution, Biophys J., vol. 72, no. 4, pp. 18781886, Apr. 1997.
[6] M. Cohen, F. Roy, D. Herault, Y. Cazaux, A. Gandolfi, J. P. Reynard,
C. Cowache, E. Bruno, T. Girault, J. Vaillant, F. Barbier, Y. Sanchez,
N. Hotellier, O. LeBorgne, C. Augier, A. Inard, T. Jagueneuau, C. Zinck,
J. Michailos, and E. Mazaleyrat, Fully optimized Cu based process with
dedicated cavity etch for 1.75 and 1.45 pixel pitch CMOS image sensors,
in IEDM Tech. Dig., San Francisco, CA, 2006, pp. 14.
[7] E. A. G. Webster, J. A. Richardson, L. A. Grant, D. Renshaw, and
R. K. Henderson, A high-performance single-photon avalanche diode in
130-nm CMOS imaging technology, IEEE Electron Device Lett., vol. 33,
no. 11, pp. 15891591, Nov. 2012.
[8] J. Richardson, L. A. Grant, and R. K. Henderson, Low dark count singlephoton avalanche diode structure compatible with standard nanometer scale
CMOS technology, IEEE Photon. Technol. Lett., vol. 21, no. 14, pp. 1020
1022, Jul. 2009.