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Review
a,*
, Frank Schwierz
School of EE and CS, University of Central Florida, Orlando, FL 32816 2450, USA
b
Fachgebiet Festkorperelektronik, Technische Universitat Ilmenau, Germany
Received 15 April 2003; accepted 6 May 2003
Abstract
Recent advances in complementary metal oxide semiconductor (CMOS) processing, continuous scaling of gate
length, and progress in silicon on insulator have stirred serious discussions on the suitability of metal-oxide semiconductor eld-eect transistors (MOSFETs) for RF/microwave applications. This paper covers the recent advances
and current status of mainstream CMOS as the dominating technology in very large scale integration, future trends of
RF MOSFETs, and applications of MOSFETs in RF electronics. Aspects of RF MOSFET modeling are also addressed. Despite some lingering debates, the prospects for RF MOS with operating frequencies in the lower GHz range
are very promising.
2003 Elsevier Ltd. All rights reserved.
Contents
1.
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
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0038-1101/$ - see front matter 2003 Elsevier Ltd. All rights reserved.
doi:10.1016/S0038-1101(03)00225-9
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5.
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
10 9
10 8
DRAM
1M
1
0.1
22nm
Processors 9nm
0.01
1k
1970
1980
1990
2000
Year
2010
2020
Pentium III
Pentium II
Pentium
10 7
Itanium
ISSCC 2003
Pentium 4
486
10 6
386
286
10 5
8086
10 4
8080
4004
10 3
1970
8008
1980
1990
2000
2010
Year of introduction
0.001
10
1G
Itanium
ISSCC 2002
103
100
1T
1. Introduction
102
0.01
0.1
1883
Table 1
Comparison of the low-eld mobility in a Si inversion channel,
bulk Si, and bulk GaAs
Material
Low-eld
mobility, cm2 /V s
Si inversion
channel
Bulk Si
Bulk GaAs
6550
700
4700
1884
Source
Gate
Drain
Oxide
Poly Si
n+
n+
Inversion channel (2DEG)
p-type substrate
during the last 10 years was the introduction of the silicon on insulator (SOI) technology, where the transistor
body is separated from the semiconducting wafer by an
insulating layer. The gate length, which is directly related to the eective channel length, is a main feature
controlling the MOSFET performance. Reducing the
gate length, however, requires the scaling of other features such as the oxide thickness, drain/source junction depth, and substrate doping density [2426]. For
example, when the gate length is reduced, the oxide
thickness needs to be reduced so that the gate can have a
better control of the channel inversion and can give rise
to a larger oxide capacitance. Typically, the gate is made
of a heavily doped polysilicon, and silicides are frequently deposited underneath the drain/source contacts
to reduce the contact resistance.
Unfortunately, undesirable eects called shortchannel eects occur in modern deep submicrometer
MOSFETs. To alleviate such eects, several additional
features have been added to the basic MOSFET structure. For example, to minimize hot-carrier eects due to
the high electric eld near the drain junction, lightly
doped drain/source (LDD) regions are implemented in
MOSFETs [27]. Another important phenomenon associated with the short-channel eects is the threshold
voltage roll-o (i.e., threshold voltage starts to decrease
when the channel length is reduced below a critical
value). This can be eectively eliminated by the use of
halo or pocket-implant MOSFET [28].
Many foundries, including IBM, Intel, TSMC,
Philips, Motorola, and LSI Logic, are gearing up to
start volume production of 100- to 90-nm technology
node processes as early as 2003. In these processes, gate
lengths can be selectively etched down to about half this
technology node. In fact, Intels prototype 90-nm process has already produced functional circuits with
MOSFET gate length of 50 nm.
The primary aim of the entire research and development eorts in VLSI electronics has been to decrease
the cost per logic function and per stored bit, and simultaneously to increase the switching speed of logic
2.2.2. RF MOSFET
An important measure of RF transistor is the cuto
frequency fT . This is the frequency at which the smallsignal current gain h21 of the transistor rolls o to unity
(i.e., 0 dB). Fig. 6 shows the cuto frequency versus the
gate length of n-channel MOSFETs, with the upper limit
as of May 2002 indicated [23]. For todays 50- to 100-nm
gate-length MOSFETs, the cuto frequency can reach
an astonishing 200 GHz [29,30]. Applying a frequently
used rule of thumb that the cuto frequency should be
around 10 times the transistors operating frequency,
one could use these devices to design integrated circuits
operating up to 20 GHz, an operating frequency higher
than that for the great majority of modern RF electronics. This, however, is only half of the picture because
a high cuto frequency is not the only requirement for a
good RF transistor. Other gures of merit have to be
considered as well. For example, a high maximum frequency of oscillation fmax which is the frequency at
which the transistors unilateral power gain U rolls o to
unity (i.e., 0 dB), is often desirable. Small noise gure
NFmin and high output power Pout are also critical for RF
noise and power applications, respectively.
Properly designed IIIV RF eld-eect transistors
(MESFET and HEMT) show comparable fmax and fT ,
but typically with fmax > fT . The situation is dierent for
Si MOSFETs. For these devices, one could either realize
short-channel transistors for high fT but substantially
lower fmax or long-channel transistors for rather low fT
but higher fmax . Table 2 illustrates such a trade-o using
two Si MOSFETs reported in 1998 and 2000. The tradeo resulted from the fact that a very high fmax can only
be achieved with transistors having a high fT and a low
500
Empirical Upper Limit
Experimental Data
100
10
0.05
0.1
Gate Length, m
Fig. 6. Reported cuto frequency versus gate length of MOSFETs [23].
Table 2
State of the art of RF MOSFETs in terms of fT and fmax reported in late 2000s
LG , nm
fmax , GHz
fT , GHz
Reference
80
500
60
66
140
25
[31]
[32]
gates. So far this aim has in fact been achieved and resulted in new generations of microchips containing more
transistors and having a higher clock frequency than
their predecessor.
1885
300
100
10
0.04
0.1
Gate Length, m
Fig. 7. Reported maximum frequency of oscillation versus gate
length of MOSFETs [33].
1886
Gate
Reported Jan. 2001 - March 2003
Reported by Dec. 2000
Source
Drain
-
n LDD
200
n+
fmax , GHz
n+
150
p body
p + sinker
100
p - epi
50
0
50
100
150
200
p + substrate
250
f T , GHz
Fig. 8. Reported maximum frequency of oscillation of MOSFETs versus the cuto frequency [33].
2.0
Exp. Data MOSFET
Empirical Lower Limit
1.5
1.0
(c)
0.5
(b)
0.0
0.6
Source
(a)
(a)
10
20
Frequency, GHz
Fig. 9. Measured data of minimum noise gure versus frequency, with four lowest gures indicated with (a), (b), and (c)
reported in [3638].
minimum noise gures NFmin of experimental Si MOSFETs are given in Fig. 9 [23]. Only noise gures up to
about 15 GHz had been reported, and MOSFETs become too noisy at even higher frequency for practical
microwave applications.
Due to the low breakdown voltage, the standard
MOSFET structure, shown in Fig. 5, can only be used in
relatively low power applications. High-power microwave ampliers used in the base stations for mobile
communication systems, however, are designed for maximum operating (and thus breakdown) voltage to deliver
maximum output power. For such applications, a different MOSFET structure called the LDMOSFET (laterally-diused MOSFET) is frequently used [23]. The
cross-section of a typical high-power LDMOSFET is
shown in Fig. 10. It consists of a p -Si substrate on top
of a lightly doped p -layer grown epitaxially. While the
1887
relatively high series resistance. Metal gates can minimum these two problems. But before choosing a suitable metal, factors such as thermal stability and work
function need to be considered. Recently, ruthenium
tantalum alloy has been suggested as a possible gate
metal, which has the advantage of adjustable work
function to meet the required threshold voltage of
MOSFETs [41].
In the past few years, more and more researches have
been devoted to investigating innovative MOSFETs
having more than one gate to enhance the control
of ultra-small MOSFETs. Several vertical and planar
structures have been suggested and tested, and the
frontrunner is an approach called the double-gate
MOSFET under development by many semiconductor
companies [4244]. In Fig. 11, two double-gate MOSFET versions are shown. On the left is a planar doublegate transistor investigated by IBM researches, and the
other is a vertical double gate FET commonly called
FinFET favorited by AMD, TSMC, and others. The
FinFET is built by etching the silicon layer of an SOI
wafer to form narrow vertical ns on the wafer surface.
The narrow n forms the channel, the source and drain
are formed at end of the n, and the gate drapes over
both sides of the n (i.e., two gates). Since the n is made
extremely thin, no region of the n escapes the inuence
of the gate, and no leakage path for the carriers to ow
between the source and drain when the device is o.
Currently, Intel is pushing for a modied FinFET version called the Trigate FET. Here, an almost quadratic
cross-section of the ns is striven for and the gate surrounds the n from the vertical surfaces and from the
top. Thus, there are three gates controlling the current
path in the n. Such a device is schematically shown in
Fig. 12.
2.3.2. RF MOSFET
The advanced MOSFET concepts described above
are focused on developing transistors for high-level integrated circuits, such as microprocessors, ASICs, etc.
How they will be used for RF MOSFETs is still unclear.
1888
NFmin , dB
Reference
2
4
10
26
0.14
0.18
0.2
1.5
[46]
[46]
[47]
[47]
250
a Conexant 2001
b Hitachi 2002
fT
fmax
fmax , GHz
IBM 2002
200
IHP 2002
100
100
200
f T , GHz
IHP 2002
b
a
150
100
IBM 2001
a
IHP 2001
IHP 2002
IBM 1999
Lucent 1999
50
0
0.0
0.2
0.4
IHP 1999
IBM 1999
0.6
0.8
1.0
Emitter width, m
Fig. 14. Reported fT and fmax of SiGe HBTs versus the emitter
width [33].
300
Frequency, GHz
200
300
400
Operating frequency
Pagers
Cellular phones 1st generation (1G)
Cellular phones generation 2 and 2.5
(2G, 2.5G)
Cellular phones generation 3 (3G)
Global positioning system (GPS)
Wireless area networks (WLAN)
Bluetooth
HiperLAN2
802.11a Local Area Network (WiFi)
1889
the relatively low output power density. GaAs transistors (especially GaAs HBT) dominate this application.
To date, the dominant power RF transistor used in
base stations of wireless communications systems with
operating frequencies up to 2.5 GHz is the Si LDMOSFET, which in the last several years has replaced all
other competing Si and GaAs transistors [53]. Si LDMOSFETs combine the advantages of moderate cost,
high reliability and extremely high output power.
Aside from cellular phones, several other civil RF
systems with operating frequencies below 20 GHz are
potential elds for the application of RF MOSFETs as
well. For example, Bluetooth, in which the requirements
on transistors RF performance are quite moderate, is
predestinated for RF MOSFETs. In fact, all-MOS
Bluetooth products are already commercially available
[54]. For other applications below 20 GHz but with
more stringent requirements concerning RF performance, the combination of SiGe HBTs and CMOS
(SiGe BiCMOS) is currently a heavily discussed possibility in industry [55,56].
Although RF MOSFETs seem to fulll most of the
performance requirements for civil RF systems with
operating frequencies up to 6 GHz, debates still existed
as to whether such devices will nd widespread applications in the market [57]. Nevertheless, there is a
growing belief that the importance of MOSFETs in RF
applications will increase in the near future and for
many years to come.
1890
possible, many bias combinations for the ac characteristics will need to be considered, and the measurements
and parameter extractions become impractical and too
time consuming.
In spite of these problems, intensive eorts have been
devoted to RF MOS modeling and parameter extraction. In the following, we will rst briey introduce the
strategies for RF modeling and parameter extraction of
two-port networks. Then the modeling of four-terminal
MOSFETs based on the macro-modeling approach will
be discussed. Only the approaches and concepts will be
given in this section, as the detailed information of
device physics and RF modeling can be found in the
literature.
4.1. Modeling of three-terminal RF MOSFET
We will rst discuss RF IIIV FET models, as these
models have been developed in the past to address highfrequency issues and can be readily extended for RF
MOSFETs.
Only when both a proper model and a good set of
model parameters are used together can one obtain accurate and meaningful circuit simulation results. Thus it
is imperative to develop a well-constructed model and its
parameter extraction method in order to eectively describe and predict the device characteristics. A model is
normally represented by an equivalent circuit consisting
of elements such as resistances, capacitances, inductances, and current sources. These elements are described by mathematical equations. All of the constants
and coecients associated with the equations, called the
model parameters, ideally should have physical origins.
However, some of them may result from empirical experiences to enhance the model accuracy. The model
parameters need to be determined from extraction
techniques based on experimental data from MOSFETs
measured at dierent biased condition and frequencies.
At low frequencies, these measurements are usually done
utilizing Z, Y , or H matrices. This is because it is easier
to measure the voltage or current with open or short
circuits. However, there are many problems with this at
high frequencies. By terminating the port with a cable of
characteristic impedance, the S-parameter technique
measures power waves propagating into and being reected from the device and thus is the easiest and the
most reliable way to characterize high-frequency networks.
A conventional small-signal equivalent circuit of III
V FETs is shown in Fig. 15 [59]. This equivalent circuit,
which consists of capacitances C, inductances L, resistances R, and a current source involving transconductance gm and delay time s, can be divided into two parts:
(1) Intrinsic elements: gm , gds , Cgs , Cgd , Cds , Ri , and s,
which are functions of biases.
Intrinsic device
Lg
C pg
C gd
Rg
Cgs
Rd
g me-jwt
gds
Cds
Ld
Cpd
Ri
Rs
Ls
1891
G
Lg
Rg
Igs
S
Q gs
Qgd
Igd
D
Ls
Rs
D
Ids
Rs
Ls
Qds
Fig. 16. Equivalent circuit of large-signal model for threeterminal FETs.
Table 5
Availability of BSIM, MOS, and EKV models in commercially available software tools
HSpice
Spectre
SmartSpice
Pspice
BSIM3
BSIM4
MOS9
MOS11
EKV
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Table 6
Comparison of the various BSIM versions
Model
Geometry (lm)
Ids
Subthreshold
Rout
Scalability
Berkeley Level-1
Berkeley Level-2
Berkeley Level-3
BSIM-1
BSIM-2
BSIM-3
BSIM-4
5.0
2.0
1.0
0.8
0.25
0.15
0.1
Poor
Poor
Fair
Good
Good
Good
Good
NA
Poor
Poor
Fair
Good
Good
Good
Fair
Fair
Poor
Poor
Fair
Good
Good
Poor
Fair
Poor
Fair
Fair
Good
Good
1892
Table 7
Summary of the approached used in the BSIM, MOS, and EKV models
Method
Channel inversion
DC current
Reference
Symmetry
Gate noise
Tunneling
BSIM3
BSIM4
MOS9
MOS11
EKV
Analytic
Vt-based
Drift
Source
No
Ignore
Ignore
Analytic
Vt-based
Drift
Dynamic
Yes
Yes
Yes
Analytic
Vt-based
Drift
Source
No
Yes
Ignore
Analytic
Surface-potential based
Drift-diusion
Source
Yes
Yes
Yes
Analytic
Hybrid
Drift
Bulk
Yes
Ignore
Ignore
1000
BSIM3V2
C DB
BSIM 3V3
Dint
BSIM2
HSP28
BSIM 3V3
BSIM3V2
BSIM 4
BSIM2
PCIM
SP2000
HSP28
LEVEL2
BSIM3V1
EKV V3.0
MM9
BSIM
EKV V2.6
LEVEL3
100
Gext
BSIM
10
Without Scaling
1
1960
1970
1980
1990
2000
RG
RDSB2
G int
R DSB1
LEVEL1
R DB
2010
Years
Model
Core
RDSB3
B ext
B int
Sint
C SB
RSB
Sext
Fig. 18. Four-terminal RF MOSFET model based on the
macro-modeling approach.
9
8
7
6
0.0
Y12 [ mS ]
-1.0
Imaginary
2
1
0
Real
-1.5
Imaginary
-2.0
-2.5
10
15
-3.5
20
7
6
Real
Measurement
Model
10
5
0
Imaginary
10
10
15
Real
Measurement
Model
0
20
Frequency [ GHz ]
20
0
0
15
Imaginary
-5
-10
Frequency [ GHz ]
25
15
(b)
30
20
Measurement
Model
-3.0
Frequency [ GHz ]
(a)
Y21 [ mS ]
Real
-0.5
5
4
3
(c)
1893
0.5
Measurement
Model
Y22 [ mS ]
Y11 [ mS ]
(d)
10
15
20
Frequency [ GHz ]
Fig. 19. Characteristics of Y -parameters modeled and measured from a 0.18-lm n-MOSFET (after [67]).
5. Conclusions
The evolution, state of the art, as well as future
trends of RF MOSFETs have been presented and discussed. Aspects of RF MOSFET modeling and three
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