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1, 2,3,4,5
ABSTRACT
In this paper the Traff's current comparator is designed
using a current differencing stage is seen which
compares an input current with a reference current
maintaining high speed and low power. Earlier works
of current comparator neglected the current
differencing stage although the current differencing
stage forms an important part of the current
comparison process. The circuit has been simulated in
Cadence EDA tool in 90nm CMOS process technology
using Spectre simulator. Transient response confirms
the very high speed operation of the Current
Comparator when the current differencing stage is
added.
Keywords current difference, delay, positive
feedback, reference current, Traffs current
comparator
I.
II.
INTRODUCTION
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III.
IV.
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TABLE I
Corner Analysis Performance Results of the Current
Comparator
Corner
TT
FS
SF
SS
Delay
(ns)
0.72
0.79
0.69
0.82
Power
(W)
116.4
124.9
88.12
59.93
Slew Rate
(V/ns)
4.399
3.211
6.646
7.675
V.
CONCLUSION
REFERENCES
[1] D. A. Freitas and K. W. Current, "A CMOS
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no. 17, p. 695-697. Aug. 1983.
Fig. 6 Variation of Power with Current Difference
The plot of PDP (Power Delay Product) against current
difference is shown in Fig. 6. It is seen that the PDP
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[3]K.W. Current, Current-mode CMOS multiplevalued logic circuits, IEEE J. Solid State Circuits, vol.
29, no. 2, pp. 95-107, Feb.1994.
[4] A.T.K. Tang and C. Toumazou, High performance
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[5] Byung-moo Min and Soo-won Kim, High
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[6] Lu Chen, Bingxue Shi, and Chun Lu, A High
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[10] Chun Wei Lin,and Sheng Feng Lin, Low Input
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