UNIVERSITI TEKNOLOGI MALAYSIA

Faculty of Electrical Engineering

HW/SW Co-design of a Nios II-based Embedded System

32-bits Signed Multiplication

Report from a project conducted on11st Sept 2009

as part of SEW 4722 at the ECAD Laboratory

SEW 4722, Section 1, Group No. 3

Eunice Ng Hui Xian
Lee Chen Cheak
Mohd Firdaus
Teoh Shu Wen
 HW/SW Co-design of a Nios-II-based
Embedded System
32-bits Signed Multiplication
Eunice Ng Hui Xian, Lee Chen Cheak, Mohd Firdaus, Teoh Shu Wen
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
81310 UTM Skudai, Johor, Malaysia

Abstract—Before the implementation of the laboratory work, a
process of create, compile, and download of a Nios II-based
embedded system is implemented on Altera DE2 board for
system verification was completed. In this paper, an embedded
system application is written using C++ programming language
and is run on Nios II-based embedded system. Meanwhile, a
hardware accelerator is designed to do the previous operation. A
system bus interface and firmware device driver of the hardware
accelerator is also designed and is integrated into the Nios II-
based embedded system.
I. INTRODUCTION
In today's world, embedded systems are everywhere --
homes, offices, cars, factories, hospitals, plans and consumer
electronics. Their huge numbers and new complexity call for a
new design approach, one that emphasizes high-level tools and
hardware / software tradeoffs, rather than low-level assembly-
language programming and logic design.
An embedded system is a system designed to perform one
or few dedicated functions which often involve real-time
computing. As embedded system is designed only to perform
dedicated function(s), engineers can optimize it, reducing the
size and cost of the product. Examples of embedded system
are PDAs, MP3 players, mobile phones, digital cameras, DVD
players, GPS receivers and printers.
circuit (IC) chip. The result is a single chip with no external
connections to other chips, thus reducing the size and
packaging of the product.
This lab also introduces the Altera SOPC Builder (System-
on-Programmable Chip) to develop a Nios II-based Embedded
System using SOPC Builder, Quartus II, and Nios II IDE
software. It aims to design the software and hardware partition
(hardware IP core) of an embedded system. It also aims to
perform the design-space exploration between the hardware
and software partition when performing specific computation.
The performance metric is measured in logic cost and
computation cycle count.
II. METHODOLOGY
This project is divided into two design parts that are,
software and hardware. The software part is to write a RNG
and 32-bits signed multiplication in the embedded system
application using C++ programming language and for the
hardware part is to design a mul_coprocessor. After designing
the both parts, they will be downloaded into the Altera DE2
board.

This PBL lab project designs an embedded 32-bit signed

multiplier with Field Programmable Gate Array (FPGA) based
hardware acceleration for multiplication of random number.
This is done by designing the 32-bit signed multiplication
hardware core. All the hardware cores are integrated into an
embedded system implemented as a System-on-Chip (SoC).

With the state-of-the-art very large scale integration (VLSI)

technology available today, many of the embedded systems or
substantial parts of the systems can be integrated on a single,
programmable platform. In other words, these embedded
systems are implemented as System-on-Chip, which from here
on will be referred to as a SoC design or SoC embedded
system.

SoC is the system that integrates all the hardware

components of the embedded system into a single integrated Fig. 1 Work flow of lab project
 For the software design part, there are two tasks need to be Referring to Appendix 1 shows a software code for the 32-
completed that are, Random Number Generator (RNG) and bits signed multiplication function. To generate the random
32-bits signed multiplication. The RNG that is written using number, “rand()” and “rand()%2” are used to verify the
C++ programming language has to generate 25 sets of 32-bits number generated was a odd or even number. If it is “true”
signed random number as input operand. The random seed means that the remainder exited and sure that the number was
was based on user input. When user inserts a value, the an add number. All odd numbers will be a negative signed
software will generates 25 sets of random numbers including number.
signed numbers. Then the software performs 32-bits signed
multiplication and display the random number generator and For the second part of the project, VHDL code is written
multiplication output. based on the provided algorithm. The algorithm for signed
multiplication is as follows.
Referring to Fig.2 shows a flowchart of the function. Once
start the program, it requests a user input to enter a seed Input : x, y (signed number)
number. The user input will store as seed number and will Output : P, where P = x * y
generate 25 sets of random numbers based on the seed A = x, B = y, P = 0
number. After one set of random number is generated, it will for i = 0 to 31 do
then perform the multiplication operation. 32-bits signed If Bi = 1 then
number as a user input will produce 64-bits of output P=P+A
multiplication. End if
A << 1;
Return P

From the algorithm above, the ASM flowchart was first

designed as shown in Fig.3 below. Then, the functional block
diagram of the control and data path units were obtained as
shown in Fig.4 below. The RTL control sequence table as in
Appendix 2 was next derived, to determine the appropriate
control vector signals. Then, the VHDL code was written and
is attached in Appendix 3

Fig.2 Flow chart of 32-bits signed multiplication

 To connect the multiplier designed earlier to the system
interconnect fabric, an Avalon Memory-Mapped Bus Interface
is needed. As shown in Appendix 5, the MU_interface
connects the multiplier to the system interconnect fabric. This
combination of MU_avalon and mul_MU formed
MU_avalon, which is the hardware accelerator. Note that only
some of the I/O of the mul_MU were connected to the
MU_interface.

VHDL codes shown in Appendix 6 and 7 shows the

functional mechanism of MU_interface and MU_avalon
respectively.

Referring to both Appendix 5 and 6, we will first discuss

the architecture of the MU_interface. When reset equals one,
the output of readdata will be zero. The output of start will be
zero also, which is, the multiplier will be in off state. When
chipselect equals to one, a 2-bit data will be loaded into the
address. If the input of address is “00”, the output of start will
be equal to ‘1’, which initiates the multiplier(mul_MU).
When the input of address equals to “01”, the output of data1
will be equal to the input of writedata. When the input of
address equals to “10”, the output of data2 will be equal to the
input of writedata. The output of readdata equals to the input
of result when address input equals to “11”.

Next, the architecture of the MU_avalon will be discussed.

Fig.4 Functional block diagram The connection is shown in Appendix 5. As the mul_MU
inputs two 32-bit data to perform multiplication, the result of
the multiplication will be 64-bit. Due to the restriction of the
The signed multiplication operation requires several width of the Avalon bus, which is 32-bit, this attempt is made:
considerations to be taken regarding the MSB of the inputs. a range is set for user input, which is from -32768 to 32767.
This is shown in Fig.5 below. This is the range of signed 16-bit numbers. These inputs are
loaded into the mul_MU as a 32-bit data. After multiplication,
a 64-bit result will be obtained. However, the upper 32 bit will
A B Operation always be ‘00000000000000000000000000000000’ or
‘11111111111111111111111111111111’because the input is
Positive Positive No change
set to 16-bit range. Hence, the upper 32-bit data can be
Positive Negative Swap A and B omitted. The result input of the MU_interface will only load
Negative Positive No change the lower 32-bit data from the result output of mul_MU.
Negative Negative 2’s complement A Therefore, the readdata output which take the value of result
and B input will be in 32-bit, which fulfills the Avalon bus width
Fig.5 Multiplication operation restriction.

The disadvantage of the previous attempt is that only

This is needed so that the algorithm will work on sign
numbers. The modifications were made by adding a
combinational block to the data path unit, named convert
block, which detects the sign of the inputs and changes it
accordingly. Besides that, during the loading of input A, it is
sign extended with the appropriate bit. This is coded in the
data path unit.
Waveform simulation was then performed to verify the
functionality. The results are shown in Appendix 4. It can be
observed that the results are valid for all combination of
signed numbers.
numbers within 16-bit range can be accepted. To expand the
input range to 32-bit signed number range, an alternative was
suggested. An extra register have to be added into the
MU_interface to hold the 64-bit value from the result output
of mul_MU. It will then output the 64-bit data through the 32-
bit readdata output separately. It will first output the upper 32-
bit, then the lower 32-bit sequentially. If this method is used,
an extra session must be added into the firmware design, so
that it will read the output of readdata as a loop.
 III. RESULT AND ANALYSIS
For the first part in the project which is required to write a
software program in C++ to produce a Random Number
Generator (RNG) with 32-bits signed multiplication function.
In this part, there did not have any big problem to come out a
program by using C++ language, since the language is already
familiar from the past. The only problem that had been faced
at the beginning was, a wrong type of variable type was
assigned to the variable, so cannot obtain the random 32bit
number. Fig.xx below shows the output of the 32-bits signed
multiplication .
Fig. 6 Output of 32-bits signed multiplication
APPENDICES
Then we continue to integrate the mul_coprocessor into a
NIOS-II SoC as user peripheral. This part can easily be done
because we have do the same thing we we do it our pre-lab.
In the part to write the firmware device driver of the
mul_coprocessor, execute by the Nios II CPU to compute the
signed Multiplication number. Due to the time limitation and
the problem we faced at the previous part, we can’t write the
firmware in term to understand the coding of the system.h. we
were just able to finished up to this part.
Since we can’t finish the firmware, then we can’t proceed
to Question 3 in combination. But we try to find the solution
as theoretical compare between the hardware and the software.
In prediction, the multiplication operation compute by the
hardware mul_coprocessor will be faster than the software
mul_coprocessor. As the hardware multiplication is using an
SoC as a platform thus it has all advantages of an SoC system.
In part of the design trade off, we can find that the hardware
have the higher cost compare the software. It can be
determined through the LE cost after the simulation and before
the simulation.
CONCLUSION
As conclusion, by doing this lab, we brush up our C
programming language. Besides, get to know more about the
VHDL language and also learned a more proper way to use
HDL language to come out a design. In addition, learned
about the SOPC system although we are unable to finish the
entire lab, but we have learned a lot through this lab session.
The most important thing we get from this lab is we found out
how importance cooperation is, and things cannot be done just
by one without others. Instead of gaining knowledge, we were
gained more on soft skill side. We learn about how to
communicate with each others and the importance of
communication.
REFERENCES
[1] Dr. Mohamed Khalil Hani, “Starter’s Guide to Digital Systems VHDL
& Verilog Design 2nd Edition ,” Pearson Prentice Hall
[2] B. Stephen, V. Zwonko, “Fundamentals of digital logic with vhdl design
2nd ed,” Mc Graw Hill Higher Education, 2005.
APPENDIX 1- C++ code RNG.

#include <iostream>
#include <stdio.h>
#include <stdlib.h>
using namespace std;

int main()
{
short i;
int seed;
int set1[25];
int set2[25];
long long mul[25];

cout << “Enter a seed number:”;

cin >> seed;
srand(seed);
for (i=0; i<=24; i++)
{
set1[i] = rand();
set2[i] = rand();

if (rand()%2==1)
{
set1[i]=set1[i]*(-1);
}
if (rand()%2==1)
{
set1[i]=set1[i]*(-1);
}
mul[i]=static_cast<long long>(set1[i])*static_cast<long long>(set2[i]);
cout <<”\n\tx is \t” << set1[i] << “\t and y is \t” << set2[i] << endl;
cout << “\tx multiply y is \t” << mul[i] << endl;
}
return(0);
}

APPENDIX 2
RTL Control Sequence Table

RTL Operation Activated Control Signals DU Control Vector

Psel ldP ctrlA ldA ctrlB ldB Psel ldP ctrlA ldA ctrlB ldB
S1: P
0; Psel’ ldP 0 1 0 0 0 0

(Start’)/A⇓MSB &dataA ctrlA ldA 0 1 1 1 1 1

(Start’)/B⇓dataB ctrlB ldB
(Start’)/A⇓go to S1
S2: A
A<<1 ctrlA’ ldA 0 0 0 1 0 1
B
B>>1 ctrlB’ ldB

(Z’b0)/P
P+A Psel ldP 1 1 0 1 0 1

Z’/go to S2 ctrlA’ ldA 0 0 0 1 0 1
S3: done
1 0 0 0 0 0 0
(Start’)/ go to S1
(Start)/ go to S3

APPENDIX 3
VHDL Codes

64-bit Register
library ieee;
use ieee.std_logic_1164.all;

entity mul_Reg64 is
port (clk, en, rst : in std_logic;
d : in std_logic_vector (63 downto 0);
Q : buffer std_logic_vector (63 downto 0));
end mul_Reg64;

architecture arch_reg of mul_Reg64 is begin

process (clk, rst) begin
if rst = '1' then Q <= (others => '0');
elsif (clk'event and clk = '1') then
if en = '1' then Q <= d;
else Q <= Q;
end if;
end if;
end process;
end arch_reg;

64 bit Shift Left Register

library ieee;
use ieee.std_logic_1164.all;

entity mul_shiftLreg64 is
port (d : in std_logic_vector(63 downto 0);
ldsh, en, w, clk, rst : in std_logic;
q : buffer std_logic_vector (63 downto 0));
end mul_shiftLreg64;

architecture Shift_arch of mul_shiftLreg64 is begin

process (clk, rst) begin
if rst = '1' then q <= (others => '0');
elsif (clk'event and clk = '1') then
if en = '1' then
if ldsh = '1' then q <= d;
else
q(0) <= w;
for i in 1 to 63 loop
q(i) <= q(i-1);
end loop;
end if;
end if;
end if;
end process;
end Shift_arch;

32-bit Shift Right Register

library ieee;
use ieee.std_logic_1164.all;

entity mul_shiftRreg32 is
port (d : in std_logic_vector (31 downto 0);
ldsh, en, w, clk, rst : in std_logic;
q : buffer std_logic_vector (31 downto 0));
end mul_shiftRreg32;

architecture Shift_arch of mul_shiftRreg32 is begin

process (clk, rst) begin
if rst = '1' then q <= (others => '0');
elsif (clk'event and clk = '1') then
if en = '1' then
if ldsh = '1' then q <= d;
else
q(31) <= w;
for i in 0 to 30 loop
q(i) <= q(i+1);
end loop;
end if;
end if;
end if;
end process;
end Shift_arch;

Convert Block
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity mul_convert is
port (dataA, dataB : in std_logic_vector (31 downto 0);
outA, outB : buffer std_logic_vector (31 downto 0));
end mul_convert;

architecture arch_convert of mul_convert is

signal z: std_logic_vector(1 downto 0);
signal tempA: std_logic_vector(31 downto 0);
signal tempB: std_logic_vector(31 downto 0);
begin
process (z, dataA, dataB, outA, outB,tempA,tempB) begin
z(1) <= dataA(31);
z(0) <= dataB(31);
if z <= "00" then
outA <= dataA;
outB <= dataB;
elsif z <= "01" then
outA <= dataB;
outB <= dataA;
elsif z <= "10" then
outA <= dataA;
outB <= dataB;
else
for i in 0 to 31 loop
tempA(i) <= not dataA(i);
tempB(i) <= not dataB(i);
end loop;
outA <= (tempA) + '1';
outB <= (tempB) + '1';
end if;
end process;
end arch_convert;

Data Path Unit

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mul_DU is
port( clk, rst : in std_logic;
in_dataA, in_dataB: in std_logic_vector(31 downto 0);
P : buffer std_logic_vector(63 downto 0);
Psel, ldP, ctrlA, ldA, ctrlB, ldB : in std_logic;
A_tp : out std_logic_vector(63 downto 0);
B_tp :out std_logic_vector(31 downto 0);
dataP_tp : out std_logic_vector(63 downto 0);
z, b0 : out std_logic);
end mul_DU;
architecture DU_arch of mul_DU is
signal Ain, A, sum, dataP : std_logic_vector(63 downto 0);
signal B : std_logic_vector(31 downto 0);
signal zero1 : std_logic;
signal dataA, dataB : std_logic_vector(31 downto 0);

component mul_Reg64 port (

d : in std_logic_vector(63 downto 0);
en, clk, rst : in std_logic;
q : buffer std_logic_vector(63 downto 0));
end component;

component mul_ShiftLreg64 port (

d : in std_logic_vector(63 downto 0);
ldsh, en, w, clk, rst : in std_logic;
q : buffer std_logic_vector(63 downto 0));
end component;

component mul_ShiftRreg32 port (

d : in std_logic_vector(31 downto 0);
ldsh,en, w, clk, rst : in std_logic;
q : buffer std_logic_vector(31 downto 0));
end component;

component mul_convert port (

dataA, dataB : in std_logic_vector (31 downto 0);
outA, outB : buffer std_logic_vector (31 downto 0));
end component;
begin
zero1 <= '0';
process (dataA, Ain) begin
if dataA(31) = '0'
then Ain <= "00000000000000000000000000000000" & dataA;
else Ain <= "11111111111111111111111111111111" & dataA;
end if;
end process;

U_convert:mul_convert port map (in_dataA, in_dataB,dataA, dataB);

U_shiftRreg32:mul_ShiftRreg32 port map (dataB, ctrlB, ldB, zero1, clk, rst, B);
U_shiftLreg64:mul_ShiftLreg64 port map (Ain, ctrlA, ldA, zero1, clk, rst, A);
sum <= A + P;

process (Psel, sum ) begin

if Psel = '1' then dataP <= sum;
else dataP <= (others => '0');
end if;
end process;

U_reg64:mul_reg64 port map (dataP, ldP, clk, rst, P);

z<='1' when B="00000000000000000000000000000000" else '0';
b0 <= B(0); A_tp <= A; B_tp <= B; dataP_tp <= dataP;
end DU_arch;

Control Unit
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mul_CU is port(

clk, rst, start, b0,z : in std_logic;
done : out std_logic;
state : out std_logic_vector(1 downto 0);
CtrlVector : out std_logic_vector(5 downto 0));
end mul_CU;
architecture fsm of mul_CU is
signal y: std_logic_vector (1 downto 0);
constant S1: std_logic_vector (1 downto 0):= "00";
constant S2: std_logic_vector (1 downto 0):= "01";
constant S3: std_logic_vector (1 downto 0):= "10";

begin
fsm_transitions:process (clk, rst) begin
if (rst='1')then
y<=S1;
elsif (clk'event and clk = '0') then
case y is
when S1 => if start = '0' then y <= S1; else y <= S2; end if;
when S2 => if z = '0' then y <= S2; else y <= S3; end if;
when S3 => if start = '0' then y <= S1; else y <= S3; end if;
when others => y <= S1;
end case;
end if;
end process fsm_transitions;
fsm_outputs:process (y,z,b0,start) begin
CtrlVector <= (others=>'0');
done <= '0';
case y is
when S1 => CtrlVector <= "010000"; if start = '0' then CtrlVector <= "011111"; end if;
when S2 =>
CtrlVector <= "000101";
if (z = '0' ) then
if (b0 = '1')
then CtrlVector <= "110101";
else CtrlVector <= "000101“;
end if;
end if;
when S3 => CtrlVector <= "000000"; done <= '1';
when others => CtrlVector <= "------";
end case;
end process;
state <= y;

end fsm;

Sequential Multiplier (Top Level)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

entity mul_MU is port(

clock, start : in std_logic;
dataA, dataB : in std_logic_vector(31 downto 0);
result : buffer std_logic_vector(63 downto 0);
reset : in std_logic;
CtrlVector : out std_logic_vector (5 downto 0);
done : out std_logic;
state : out std_logic_vector(1 downto 0);
tpA : out std_logic_vector(63 downto 0);
tpB : out std_logic_vector (31 downto 0);
tpdataP : out std_logic_vector(63 downto 0));
end mul_MU;
architecture MU_arch of mul_MU is
signal intb0, intz : std_logic;
signal intCtrlVec : std_logic_vector(5 downto 0);

component mul_CU port(

clk, rst, start : in std_logic;
b0, z : in std_logic;
done : out std_logic;
state : out std_logic_vector(1 downto 0);
CtrlVector :out std_logic_vector(5 downto 0));
end component;

component mul_DU port(

clk, rst : in std_logic;
in_dataA, in_dataB: in std_logic_vector(31 downto 0);
P : buffer std_logic_vector(63 downto 0);
Psel, ldP, ctrlA, ldA, ctrlB, ldB : in std_logic;
A_tp : out std_logic_vector(63 downto 0);
B_tp :out std_logic_vector(31 downto 0);
dataP_tp : out std_logic_vector(63 downto 0);
z, b0 : out std_logic);
end component;

begin
U_CU:mul_CU port map(clock, reset, start, intb0, intz, done, state, intCtrlVec);
CtrlVector<=intCtrlVec ;
U_DU:mul_DU port map(clock, reset, dataA, dataB, result,
intCtrlVec (5),
intCtrlVec (4),
intCtrlVec (3),
intCtrlVec (2),
intCtrlVec (1),
intCtrlVec (0),
tpA, tpB, tpdataP, intz, intb0);

end MU_arch;

APPENDIX 4
Signed Multiplier Waveform Simulation (Timing)

Example 1: -1024 x 272 = -278528

Example 2: -512 x -112 = 57344

Example 3: 15360 x -16368 = -251412480

Example 4: 0 x 272 = 0

APPENDIX 5
APPENDIX 6
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

ENTITY MU_interface IS
PORT ( reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
chipselect : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
write : IN STD_LOGIC;
writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
readdata : OUT STD_LOGIC_VECTOR 63 DOWNTO 0);
start : OUT STD_LOGIC;
data1 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
data2 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
result : IN STD_LOGIC_VECTOR (63 DOWNTO 0));
END MU_interface;

ARCHITECTURE arch OF MU_interface IS

BEGIN

process (reset, clk)

begin

if reset = '1' then

readdata <= (others => '0');
start <= '0';
elsif clk'event and clk = '1' then
if chipselect = '1' then
case address is
when "00" =>
start <= '1';
when "01" =>
data1 <= writedata;
start <= '0';
when "10" =>
data2 <= writedata;
start <= '0';
when others =>
readdata <= result;
end case;

end if;
end if;
end process;
END arch;

APPENDIX 7
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

ENTITY MU_avalon IS
PORT ( reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
chipselect : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
write : IN STD_LOGIC;
writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END MU_avalon;

ARCHITECTURE avalon_arch OF MU_avalon IS

signal lineA : std_logic_vector (63 downto 0);
signal lineB : std_logic_vector (63 downto 0);
signal start_signal : std_logic;
signal result_MU : std_logic_Vector (63 downto 0);

COMPONENT MU_interface IS
PORT ( reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
chipselect : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
write : IN STD_LOGIC;
writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
start : OUT STD_LOGIC;
data1 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
data2 : OUT STD_LOGIC_VECTOR (63 downto 0);
result : IN STD_LOGIC_VECTOR (63 DOWNTO 0));
END COMPONENT;

COMPONENT mul_MU IS
PORT ( clock, start : in std_logic;
dataA, dataB : in std_logic_vector(31 downto 0);
result : buffer std_logic_vector(63 downto 0);
reset : in std_logic;
CtrlVector : out std_logic_vector (5 downto 0);
done : out std_logic;
state : out std_logic_vector(1 downto 0);
tpA : out std_logic_vector(63 downto 0);
tpB : out std_logic_vector (31 downto 0);
tpdataP : out std_logic_vector(63 downto 0));
END component;

BEGIN
U_MuUnit: mul_MU
port map ( clock => clk,
dataA => lineA,
dataB => lineB,
start => start_signal,
 result => result_MU,
reset => reset
);

U_Interface_MU: MU_interface
port map ( clk => clk,
reset => reset,
chipselect => chipselect,
address => address,
write => write,
writedata => writedata,
readdata => readdata,
result => result_MU,
data1 => lineA(31 downto 0),
data2 => lineB(31 downto 0),
start => start_signal
);
END avalon_arch;