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ABSTRACT
For high speed applications, the important factors are
speed, power and resolution. The CMOS dynamic
comparator using dual input single output differential
amplifier stage at both input and output stage is
presented as a proposed dynamic comparator. The
desired output of CMOS dynamic comparator circuit is
obtained with 3.3V power supply voltage and 20 MHz
clock frequency using 0.13 m technology. The
comparison results of various comparators indicates that
the proposed comparator achieve improved switching
speed and power consumption than the two state
dynamic comparator. The circuit is suitable for high
speed analog to digital converter, window detector, level
shifter and relaxation oscillator.
II.
METHODOLOGY
I.
INTRODUCTION
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3, Issue 9, December 2014
III.
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3, Issue 9, December 2014
IV.
CONCLUSION
Mohammad Anisur Rahman, A High-Speed and LowOffset Dynamic Latch Comparator, Hindawi Publishing
Corporation, The Scientific World Journal, Volume
2014, Article ID 258068, 8 pages.
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REFERENCES
[1] Neil H.E.Weste, David Harris, CMOS VLSI Design,
Third edition, 2005
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