Beruflich Dokumente
Kultur Dokumente
CTRL_LE CTRL_CLK
CTRL_
DATA
CP_OUT
OPA_N
OPA_P
OPA_OUT
STAUS_
LOCK
REF_IN
GND
GND
GND
GND
GND
GND
GND
I_REF
GND
AVCC
AVCC
AVCC
AVCC
AVCC
STATUS_
REF
VCXO_IN
GND
GND
GND
GND
GND
VCC
STATUS_
VCXO
VCXO_IN_
B
GND
VCC
VCC
VCC
VCC
VCC
VCC
Y0
GND
GND
GND
GND
GND
VCC
Y4B
Y0B
VCC
VCC
VCC
VCC
VCC
VCC
Y4
NPD
Y1
Y1B
Y2
Y2B
Y3
Y3B
NRESET
Description
The CDC7005 is a high-performance, low phase noise and low-skew clock synchronizer that
synchronizes the VCXO (Voltage Controlled Crystal Oscillator) frequency to the reference clock.
The programmable pre-dividers M and N give a high flexibility to the frequency ratio of the
reference clock to VCXO: VCXO_IN/REF_IN = (N*P)/M. VCXO_IN clock operates up to 650
MHz. Through the selection of external VCXO and loop filter components, the PLL loop
bandwidth and damping factor can be adjust to meet different system requirements. Each of the
five differential LVPECL outputs is programmable by SPI (serial programmable interface). SPI
allows individually control of frequency and enable/disable state of each output. The device
operates in 3.3V environment. The build in Latches ensures that all outputs are synchronized.
The CDC7005 is characterized for operation from 40C to +85C.
10/1/02
1
CDC7005
3.3-V High Performance Clock Synchronizer
Functional Block Diagram
OPA_IN
OPA_OUT
OPA
OPA_IP
STATUS_REF
STATUS_VCXO
STATUS_LOCK
HOLD
REF_IN
LVCMOS
INPUT
Progr. Divider
M
Progr. Delay
M
Progr. Divider
N
Progr. Delay
N
PFD
CP_OUT
Charge
Pump
CTRL_LE
VI
Reference
SPI LOGIC
I_REF
CTRL_DATA
CTRL_CLK
PECL
2 LVTTL
NPD
NRESET
MUX_SEL
VCXO_IN
VCXO_INB
PECL
INPUT
/1
Y0
PECL
OUTPUT
PECL
MUX0
PECL
Latch
PECL
MUX1
PECL
Latch
PECL
OUTPUT
PECL
MUX2
PECL
Latch
PECL
OUTPUT
PECL
MUX3
PECL
Latch
PECL
OUTPUT
PECL
MUX4
PECL
Latch
PECL
OUTPUT
Y0B
/2
/4
Y1
Y1B
/8
/16
Y2
Y2B
P Divider
Y3
Y3B
Y4
Y4B
10/1/02
2
CDC7005
3.3-V High Performance Clock Synchronizer
Terminal Functions
TERMINAL
NAME
Y[0:4]
Y[0:4]_B
TYPE
DESCRIPTION
O LVPECL
O LVPECL
LVPECL Output
LVPECL Output
Power
3.3V Supply
Ground
Ground
Power
Ground
VCC_OPA
GND_OPA
NO.
F1, H1, H4, H7, G8
G1, H2, H5, H7, F8
C2, C3, C4, E2, E3,
E4, E5, E6, E7, E8,
F7, G2, G3, G4, G5,
G6, G7
B2, B3, B4, B8, D2,
D3, D4, D5, D6, D7,
F2, F3, F4, F5, F6,
F7
B5, B6, B7, C7
C5, C6
CTRL_LE
A1
I LVTTL
CTRL_CLK
CTRL_DATA
A2
A3
I LVTTL
I LVTTL
NPD
H3
I LVTTL
NRESET
H6
I LVTTL
VCXO_IN
VCXO_IN_B
REF_IN
D1
E1
B1
I LVPECL
I LVPECL
I LVCMOS
I_REF
C1
OPA_IN
OPA_OUT
OPA_IP
CP_OUT
A5
A6
A7
A4
I
O
I
O
STATUS_REF
C8
O LVTTL
STATUS_VCXO
D8
O LVTTL
STATUS_LOCK
A8
O LVTTL
VCC
GND
10/1/02
3
CDC7005
3.3-V High Performance Clock Synchronizer
SPI Control Interface
The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the
registers of the device. It consists of three control lines CTRL_CLK, CTRL_DATA and
CTRL_LE. There are four 30 bits wide registers, which can be addressed by the two LSB of a
transferred word. Every transmitted word must have 32 bits, starting with MSB first.
The transfer is initiated with the falling edge of CTRL_LE; as long as CTRL_LE is high, no data
can be transferred. During CTRL_LE low data can be written. The data has to be applied at
CTRL_DATA and has to be stable TBDns before the rising edge of CTRL_CLK. The transmission
is finished by a rising edge of CTRL_LE.
t4
CTRL_CLK
t1
CTRL_DATA
DB23(MSB)
t2
DB22
DB2
DB1
DB0
t6
CTRL_LE
t5
10/1/02
4
CDC7005
3.3-V High Performance Clock Synchronizer
Word 0:
MUXS0
MUXS1
MUXS2
RES0
Current
PFD
Pulse
Width
Ref.
Delay
Reference Counter M
Description / Function
CP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
Name
C0
C1
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
MD0
MD1
MD2
PFD0
PFD1
PFD2
CP0
CP1
CP2
Y03St
Y13St
Y23St
Y33St
Y43St
CP3St
OP3St
Output 3State
Bit
Register Selection
Register Selection
Reference Counter M Bit 0
Reference Counter M Bit 1
Reference Counter M Bit 2
Reference Counter M Bit 3
Reference Counter M Bit 4
Reference Counter M Bit 5
Reference Counter M Bit 6
Reference Counter M Bit 7
Reference Counter M Bit 8
Reference Counter M Bit 9
Reference Delay MD Bit0
Reference Delay MD Bit1
Reference Delay MD Bit2
PFD Pulse Width PFD Bit 0
PFD Pulse Width PFD Bit 1
PFD Pulse Width PFD Bit 2
CP Current Setting Bit 0
CP Current Setting Bit 0
CP Current Setting Bit 0
Y0 N3State
Y1 N3State
Y2 N3State
Y3 N3State
Y4 N3State
CP N3State
OPA N3State & Disable
MUXSEL Select Bit 0
MUXSEL Select Bit 1
MUXSEL Select Bit 2
RESERVED0
Type
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Power Up
Condition
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
Pin
Affected
A4
A4
A4
A4
A4
A4
F1, G1
H1, H2
H4, H5
H7, H8
G8, F8
A4
A6
C1
10/1/02
5
CDC7005
3.3-V High Performance Clock Synchronizer
Word 1:
MUX
2
MUX
1
MUX
0
VCXO
Delay
VCXO Counter N
Description / Function
MUX
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
Name
C0
C1
N0
N1
N2
N3
N4
N5
N6
N7
N8
N9
ND0
ND1
ND2
MUX00
MUX01
MUX02
MUX10
MUX11
MUX12
MUX20
MUX21
MUX22
MUX30
MUX31
MUX32
MUX40
MUX41
MUX42
RES1
RES2
MUX
4
Bit
Register Selection
Register Selection
VCXO Counter N Bit 0
VCXO Counter N Bit 1
VCXO Counter N Bit 2
VCXO Counter N Bit 3
VCXO Counter N Bit 4
VCXO Counter N Bit 5
VCXO Counter N Bit 6
VCXO Counter N Bit 7
VCXO Counter N Bit 8
VCXO Counter N Bit 9
VCXO Delay ND Bit0
VCXO Delay ND Bit1
VCXO Delay ND Bit2
MUX0 Select Bit 0
MUX0 Select Bit 1
MUX0 Select Bit 2
MUX1 Select Bit 0
MUX1 Select Bit 1
MUX1 Select Bit 2
MUX2 Select Bit 0
MUX2 Select Bit 1
MUX2 Select Bit 2
MUX3 Select Bit 0
MUX3 Select Bit 1
MUX3 Select Bit 2
MUX4 Select Bit 0
MUX4 Select Bit 1
MUX4 Select Bit 2
RESERVED1
RESERVED2
Type
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Power Up
Condition
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
1
1
0
0
0
Pin
Affected
F1, G1
F1, G1
F1, G1
H1, H2
H1, H2
H1, H2
H4, H5
H4, H5
H4, H5
H7, H8
H7, H8
H7, H8
G8, F8
G8, F8
G8, F8
10/1/02
6
CDC7005
3.3-V High Performance Clock Synchronizer
Word 2:
Bit
0
1
2
3
4
Bit
Name
C0
C1
HOLD
ENBG
REXT
NPD
NRESET
CLK_SEL
CP_ON
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Description / Function
Register Selection
Register Selection
Enables Hold Functionality, High Active
Enable Bandgap
Enable External Reference Resistor
PD, current Sources, dividers and
3States all outputs
RESET all Dividers, Low Active
Determines in which direction CP should
regulate, if REF_CLK is faster than
VCXO_CLK and vice versa.
Switches both the current source and the
current sink in the Charge Pump on, to
test the current matching (Test purposes
only)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
W
W
W
W
W
Power Up
Condition
1
0
1
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin
Affected
A4
C1
10/1/02
7
CDC7005
3.3-V High Performance Clock Synchronizer
Functional Description of the Logic
Reference Divider M and VCXO Divider N
M9
0
0
0
0
M8
0
0
0
0
M7
0
0
0
0
M6
0
0
0
0
M5
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M4
0
0
0
0
1
1
1
M3
0
0
0
0
M2
0
0
0
0
M1
0
0
1
1
M0
0
1
0
1
Div by
1
2
3
4
Default
128
yes
1
1
1
1
1
1
0
1
1
1
0
1
1022
1023
1024
MD1 /
ND1
0
0
1
1
0
0
1
1
MD0 /
ND0
0
1
0
1
0
1
0
1
Delay by
Default
0ps
+ 100ps
+ 200ps
+ 300ps
+ 400ps
+ 500ps
+ 1ns
+ 2ns
yes
PFD1
PFD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Additional Pulse
Width by
0ps
+ 100ps
+ 200ps
+ 300ps
+ 400ps
+ 500ps
+ 600ps
+ 800ps
max. PFD
Frequency
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Default
yes
10/1/02
8
CDC7005
3.3-V High Performance Clock Synchronizer
Charge Pump Current
nominal Charge Pump
Current
0
0
0
0.5 mA
0
0
1
1 mA
0
1
0
2.5 mA
0
1
1
4 mA
1
0
0
5 mA
1
0
1
6 mA
1
1
0
7.5 mA
1
1
1
10 mA
CP1
CP0
Default
yes
MUXSEL Selection
MUXS2
MUXS1
MUXS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Default
yes
MUXx1
MUXx0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Default
for Y0
for Y1
for Y2
for Y3
for Y4
10/1/02
9
CDC7005
3.3-V High Performance Clock Synchronizer
State Machine Description Hold Functionality
Power Up / Reset
STATE 1: PRE LOCK
Normal Operation VCXO_ CLK
syncs with REF_CLK
10 Cycles
of VCXO in Hold
STATE 3: HOLD
OPERATION
CP is in 3-State
REF_CLK missing
10/1/02
10
CDC7005
3.3-V High Performance Clock Synchronizer
Absolute Maximum Ratings over Operating Free Air Temperature (unless
otherwise noted)
Supply voltage range, VDD........ -0.5 V to 4.6 V
Input voltage range, VI (see Notes 1 and 2) ....... -0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) ........-0.5 V to VDD +0.5 V
Input clamp current, IIK (VI < 0) ..... -50 mA
Output clamp current, IOK (VO < 0) ...... -50 mA
Continuous total output current, IO (VO = 0 to VDD) ..... 50 mA
Package thermal impedance, JA (see Note 3): GGV package ....... 75K/W
Storage temperature range Tstg ...... -65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at
these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolutemaximumrated conditions for extended
periods may affect device reliability.
NOTES:
1. The input and output negative voltage ratings may be exceeded if the input
and output clampcurrent ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51
and JEDEC2S2P (high-k board).
Supply voltage
Operating free-air temperature
Low level input voltage LVTTL
High level input voltage LVTTL
Input voltage range LVTTL
VIL
VIH
MIN
3.0
-40
2
0
VDD1.81
VDD1.165
NOM
3.3
MAX
3.6
85
0.8
3.6
VDD1.475
VDD0.88
Unit
V
C
V
V
V
V
V
10/1/02
11
CDC7005
3.3-V High Performance Clock Synchronizer
Timing Requirements over Recommended Ranges of Supply Voltage, Load
and Operating Free Air Temperature
fREF
tr / tf
dutyREF
fVCXO
tr / tf
dutyVCXO
fCTRL_CLK
t1
t2
t3
t4
t5
t6
tr / tf
MIN
REF_IN Requirements
LVTTL REF Clock Frequency
3.50
Rise & Fall Time REF_IN Signal from 20% to 80%
of VDD
Duty Cycle Ref Clock @ VDD / 2
40
VCXO_IN, VCXO_IN_B Requirements
LVPECL VCXO Clock Frequency
10
Rise & Fall Time VCXO_IN VCXO_IN_B 20% to
NOM
MAX
Unit
100
MHz
4.0
ns
60
650
MHz
3.0
ns
60
20
MHz
ns
ns
ns
ns
ns
ns
ns
10/1/02
12
CDC7005
3.3-V High Performance Clock Synchronizer
Device Characteristics over Recommended Operating Free-Air
Temperature Range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IDD
Supply Current
IDDPD
Overall Parameter
fVCXO=245 MHz, fREF_IN =
30 MHz, VDD = 3.6V; fPFD =
240 kHz, ICP = 5mA
fIN = 0MHz,Vdd=3.6V
VPUC
tpho
VIK
II
VOH
VOL
CI
CI
VPP
VCMR
VIK
II
IOZ
CI
VOH
VOUTpp
tsk(p)
tsk(o)
tr / tf
fCPmax
VOL
MIN
TYP
MAX
Unit
TBD
mA
20
2.3
LVTTL Parameter
VDD = 3 V; II = 18 mA
VI = 0 V or VDD
IOH = TBD
IOL = TBD
VI = 0 V or VDD
VI = 0 V or VDD
LVPECL Parameter
see Figure TBD
see Figure TBD
V
250
ps
-1.2
TBD
TBD
4.0
pF
2.5
pF
0.5
1.3
VDD0.3
-1.2
150
5
VI = 0 V or VDD
V
V
V
A
A
2.0
IOH = -30mA
IOL = -5mA
VDD1.085
VDD1.83
500
pF
VDD0.88
VDD1.62
V
V
mV
ns
ps
ns
TBD
200
TBD
TBD
TBD
MHz
10/1/02
13
CDC7005
3.3-V High Performance Clock Synchronizer
ICP
ICP3St
IS
Voff
IB
IOS
RI
VCM
KOL
GBW
SR
VO
RO
ISC
CMRR
PSRR
en
in
10
mA
TBD
20
TBD
TBD
%
10
mA
mV
nA
nA
M
5
200
70
10
VDD
5
4
1
VDD
VDD
60
V
V/mV
MHz
V/s
V
V
mA
70
dB
80
dB
nV/
Hz
pA/
Hz
40
1
10/1/02
14
CDC7005
3.3-V High Performance Clock Synchronizer
Application Section Phase Noise Reference Circuit
VCC
VCC
V_CTRL
PECL_OUT_B
PECL_OUT
NC
GND
VCC
R7
1k
R8
10k
OPA_OUT
REF_IN
C
3
1
0
0
n
F
R7
50
C
6
0.
1
u
R11
27k
OPA_IP
OPA_IN
CP_OUT
CTRL_LE
STATUS_REF
CTRL_DATA
CTRL_CLK STATUS_VCXO
STATUS_LOCK
R9
10k
SPI
VCXO_IN
C
4
4
7
n
R10
510
R1
200
R???
1k
C
5
1
n
Yx
VCXO_IN_B
Yx_B
R2
200
R5
270
C
1
1
n
F
R4
66
R6
270
R3
66
C
2
1
n
F
phn10
Phase Noise @ 10 Hz
#
phn100 Phase Noise @ 100 Hz
#
phn1k
Phase Noise @ 1 kHz
#
phn10k Phase Noise @ 10 kHz
#
phn100k Phase Noise @ 100 kHz
#
phn240k Phase Noise @ 240 kHz
PLL Stabilization Time
tstabi
# Yx running @ 30.72 MHz
MIN
TYP
-70
-95
-120
-140
-148
-155
TBD
MAX
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
us
10/1/02
15
CDC7005
3.3-V High Performance Clock Synchronizer
Mechanical Data
10/1/02
16
CDC7005
3.3-V High Performance Clock Synchronizer
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to
discontinue any product or service without notice, and advise customers to obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and complete.
All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the
extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be or
are used. TIs publication of information regarding any third partys products or services does not
constitute TIs approval, warranty or endorsement thereof.
This is a preliminary datasheet and the parametric data should be considered as design
targets. This data may be subject to change based on device characterization results.
10/1/02
17