Beruflich Dokumente
Kultur Dokumente
XRD98L55/98L56
CCD Image Digitizers with
CDS, PGA and 10-Bit A/D
July 2001
FEATURES
l
XRD9855/56:
250/300m W @ V DD = 5.0V
XRD98L55/L56:
APPLICATIONS
l
PC Video Teleconferencing
Digital Copiers
CCTV/Security Camera
Industrial Cameras
GENERAL DESCRIPTION
The XRD9855/XRD9856 are complete CCD Image
Digitizers for digital cameras. The products include a
high bandwidth differential Correlated Double Sampler
(CDS), 8-bit digitally Programmable Gain Amplifier
(PGA), 10-bit Analog-to-Digital Converter (ADC) and
digital controlled black level auto-calibration circuitry.
The C orrelated D ouble Sam pler (C D S ) subtracts the
C C D output signal black level from the video level.
C om m on m ode signalnoise and pow ersupply noise are
rejected by the differentialC D S inputstage.C D S inputs
are designed to be used either differentialor singleended.
The auto calibration circuitcom pensates forany internaloffsetofthe X R D 9855/X R D 9856 as w ellas black
leveloffsetfrom the C C D .
ORDERING INFORMATION
Part No.
XRD9855AIV
Package
48 Lead TQFP (7 x 7 x 1.4 mm)
Operating
Temperature Range Power Supply
-40C to 85C
5.0V
Maximum
Sampling Rate
18 MSPS
XRD98L55AIV
-40C to 85C
3.0V
18 MSPS
XRD9856AIV
-40C to 85C
5.0V
27 MSPS
XRD98L56AIV
-40C to 85C
3.0V
27 MSPS
Rev. 1.01
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRD9855/9856
XRD98L55/98L56
VDD
VRBO
VRB TESTVIN
VRT
VRTO
VDD
GND
DVDD
In_Pos
CDS
ADC
PGA
Reg
DB[9:0]
In_Neg
DGND
SHD
SHP
RSTCCD
Timing
Generator
SYNC
CLAMP
CLK_POL
OVER
Offset
Calibration
UNDER
SCLK
SDI
Serial Port
Registers
LOAD
GND
STBY1
STBY2
RESET
EnableCal
OE
Rev. 1.01
2
XRD9855/9856
XRD98L55/98L56
NC
V RB
V RBO
GND
In_Pos
In_Neg
V DD
V RTO
V RT
SDI
LOAD
NC
PIN CONFIGURATION
36
CLAMP
SHD
SHP
RSTCCD
GND
CLK_POL
VDD
SYNC
UNDER
DB0
DB1
NC
25
24
37
48
13
12
NC
NC
DB2
DB3
DB4
DGND
DV DD
DB5
DB6
DB7
NC
NC
SCLK
RESET
STBY2
STBY1
Test
GND
EnableCal
VDD
OE
OVER
DB9
DB8
Symbol
Description
NC
No Connect.
NC
No Connect.
DB2
DB3
ADC Output.
DB4
ADC Output.
DGND
DVDD
DB5
ADC Output.
DB6
ADC Output.
10
DB7
ADC Output.
11
NC
No Connect.
12
NC
No Connect.
13
DB8
ADC Output.
14
DB9
15
OVER
Over Range Output Bit. OVER goes high to indicate the ADC input voltage is
greater than VRT.
Rev. 1.01
3
XRD9855/9856
XRD98L55/98L56
PIN DESCRIPTION 48 pin TQFP (CONTD)
Pin #
Symbol
Description
16
OE
17
VDD
18
EnableCal
19
GND
20
TESTVIN
21
STBY1
22
STBY2
23
RESET
24
SCLK
25
NC
26
LOAD
27
SDI
28
VRT
29
VRTO
Internal Bias for VRT. Short VRT to VRTO to use internal reference voltage.
30
VDD
31
In_Neg
32
In_Pos
33
GND
Analog Ground.
34
V RBO
Internal Bias for VRB. Short VRB to VRB0 to use internal reference voltage.
35
V RB
Bottom ADC Reference. Voltage at VRB sets zero scale of the ADC.
36
NC
No Connect.
37
CLAMP
38
SHD
39
SHP
40
RSTCCD
41
GND
42
CLK_POL
43
VDD
44
SYNC
45
UNDER
46
DBO
47
DB1
ADC Output.
48
NC
No Connect.
Shift Clock. Shift register latches SDI data on rising edges of SCLK.
No Connect.
Data Load. Rising edge loads data from shift register to internal register. Load
must be low to enable shift register.
CDS DC Restore Clamp. Clamps In_Pos & In_Neg to internal bias voltage.
CCD Reset Pulse Disconnect. Used to decouple CDS during the reset pulse.
Analog Ground.
Clock Polarity. Controls the polarity of SHP, SHD & CLAMP.
Analog Power Supply.
Digital output for Exar test purposes only. No connect.
Under Range Output Bit. UNDER goes high to indicate the ADC input voltage
is less than VRB.
Rev. 1.01
4
XRD9855/9856
XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS XRD9855 and XRD9856
U n less otherw ise specified: D V DD = VDD = 5.0V, Pixel Rate = 18MSPS, VRT = 3.8V, VRB = 0.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Input Range
200
800
mV PP
BW
60
MHz
SR
Slew Rate
40
V/s
FT
-60
dB
Conditions
CDS Performance
CDSVIN
PGA Parameters
AVMIN
Minimum Gain
3.5
6.5
dB
AVMAX
Maximum Gain
35.5
37
38.5
dB
PGA n
Resolution
bits
GE
Gain Error
% FS
Resolution
10
bits
27
MSPS
Differential Non-Linearity
-1
+0.75
1.2
LSB
DNL27
Differential Non-Linearity
-1
+1.3
2.0
LSB
EZS
50
mV
EFS
% FS
VIN
DC Input Range
VDD
VRT
1.5
3.8
VDD
VRT >VRB
V RB
0.3
0.5
VDD-1
VRT >VRB
1.0
3.3
VDD
RL
Ladder Resistance
280
400
520
Ohms
V RB
0.4
0.5
0.6
3.5
3.8
4.1
VREF
VRT
-50
GND
(
(
)
)
VRB = VDD
10
VRT = VDD
1.30
Rev. 1.01
5
XRD9855/9856
XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS XRD9855 and XRD9856 (CONT'D)
Unless otherwise specified: DVDD = VDD = 5.0V, Pixel Rate = 18MSPS, VRT = 3.8V, VRB = 0.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
System Specifications
DNL S
System DNL
1.0
LSB
XRD9855 up to 18 MSPS
DNL S27
1.0
LSB
XRD9856 up to 27 MSPS
INLSMIN
LSB
INL SMAX
LSB
VOS
VOS
MINAV
mV
MAXAV
mV
en
MAXAV
0.2
mVrms
en
MINAV
1.1
mVrms
Digital Inputs
VIH
V IL
IL
C IN
2.0
V
0.7
DC Leakage Current
Input Capacitance
pF
Digital Outputs
VOH
V OL
IOZ
High-Z Leakage
DVDD-0.5
-10
Rev. 1.01
6
0.5
10
XRD9855/9856
XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS XRD9855 and XRD9856 (CONT'D)
Unless otherwise specified: DVDD = VDD = 5.0V, Pixel Rate = 18MSPS, VRT = 3.8V, VRB = 0.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
20
25
ns
Conditions
TPW1
10
ns
TPW2
10
ns
TPIX
Pixel Period
37
T BK
56
ns
ns
TVD
ns
TRST
ns
TSC
50
TSET
10
Latency
100
ns
ns
Pipeline Delay
cycles
Power Supplies
VDD
4.5
5.0
5.5
2.7
5.0
5.5
Supply Current
50
75
mA
IDD27
55
85
mA
FS = 27MHz (XRD9856)
IDDPD
50
100
DVDD
IDD
Rev. 1.01
7
XRD9855/9856
XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS XRD98L55 and XRD98L56
Unless otherwise specified: DVDD = VDD = 2.7V, Pixel Rate = 18MSPS, VRT = 2.07V, VRB = 0.27V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Input Range
200
800
mV PP
BW
60
MHz
SR
Slew Rate
40
V/s
FT
-60
dB
Conditions
CDS Performance
CDSVIN
PGA Parameters
AVMIN
Minimum Gain
3.5
6.5
dB
AVMAX
Maximum Gain
36.5
37
38.5
dB
PGA n
Resolution
bits
GE
Gain Error
% FS
Resolution
10
bits
27
MSPS
Differential Non-Linearity
-1
+0.75
1.2
LSB
DNL27
Differential Non-Linearity
-1
+1.3
2.0
LSB
EZS
EFS
VIN
DC Input Range
VRT
1.2
2.07
V RB
0.2
RL
Ladder Resistance
V RB
VREF
VRT
-50
50
mV
% FS
VDD
VDD
VRT >VRB
0.27 VDD-1
VRT >VRB
1.0
1.8
VDD
280
400
520
Ohms
0.20
0.30
0.40
2.0
2.3
2.6
GND
(
(
)
)
VRB = VDD
10
VRT = VDD
1.30
Rev. 1.01
8
XRD9855/9856
XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS XRD98L55 and XRD98L56 (CONT'D)
Unless otherwise specified: DVDD = VDD = 2.7V, Pixel Rate = 18MSPS, VRT = 2.7V, VRB = 0.27V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
System Specifications
DNL S
System DNL
1.0
LSB
XRD98L55 up to 18 MSPS
DNL S27
1.5
LSB
XRD98L56 up to 27 MSPS
INLSMIN
LSB
INL SMAX
LSB
mV
VOS
MINAV
MAXAV
mV
en
MAXAV
0.2
mVrms
en
MINAV
0.7
mVrms
Digital Inputs
VIH
V IL
IL
C IN
1.5
V
0.7
DC Leakage Current
Input Capacitance
pF
Digital Outputs
VOH
V OL
IOZ
HighZ Leakage
DVDD-0.5
-10
Rev. 1.01
9
0.5
10
XRD9855/9856
XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS XRD98L55 and XRD98L56 (CONT'D)
Unless otherwise specified: DVDD = VDD = 2.7V, Pixel Rate = 18MSPS, VRT = 2.07V, VRB = 0.27V
Symbol
Parameter
Min.
Typ.
Max.
Unit
28
35
ns
Conditions
TPW1
10
ns
TPW2
10
ns
TPIX
Pixel Period
37
T BK
56
ns
ns
TVD
ns
TRST
ns
TSC
50
TSET
10
Latency
100
ns
ns
Pipeline Delay
cycles
Power Supplies
VDD
2.7
3.0
3.6
2.7
3.0
3.6
Supply Current
40
55
mA
IDD27
45
65
mA
FS = 27MHz (XRD9856)
IDDPD
50
100
DVDD
IDD
+7.0V
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
-65C to 150C
ESD
2000V
Notes:
1 Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode
clamps (HP50822835) from input pin to the supplies. All inputs have protection diodes which will protect the
device from short transients outside the supplies of less than 100mA for less than 100s.
3 V
DD refers to AVDD and DVDD. GND refers to AGND and DGND.
Rev. 1.01
10
XRD9855/9856
XRD98L55/98L56
SYSTEM DESCRIPTION
Correlated Double Sample/Hold (CDS) &
Programmable Gain Amplifier (PGA); Gain [7:0]
During the black reference phase of each pixel the
SDRK switches are turned on, shorting the PGA1
inputs to VDD. The sampling edge of SHP turns off the
SDRK switches, sampling the black reference voltage
on capacitors C1 & C2.
During the video phase of each pixel the SPIX switches
are turned on. The difference between the pixel reference level and video level is transmitted through capacitors C1 & C2 and converted to a fully differential
signal by the differential amplifier PGA1. The sampling
edge of SHD turns off the SPIX switches, sampling the
pixel value on capacitors C3 & C4.
CDS
PGA
VDD
External
Coupling
Capacitors
CCD
Supply
CCD
Signal
Gain
Register
SDRK
SPIX
RSTCCD
In_Pos
C1
In_Neg
+
PGA1
C2
PGA2
C3
C4
CLAMP
Offset
Calibration
VBIAS~0.8
ADC
Code
Enable Cal
Rev. 1.01
11
BUF
to
ADC
XRD9855/9856
XRD98L55/98L56
CCD
RSTCCD
SHP
SHD
(Internal Signals)
SDRK
SPIX
PGA1
Output
PGA2
Output
ADCLK
Hold
Track
40
FS = 18MHz
VDD = 3.0V
VRT = 2.3V
VRB = 0.3V
TA = 25C
35
30
25
20
15
10
5
code
Gain[dB] = 6 + 32
256
64
128
192
Gain Code
Rev. 1.01
12
256
XRD9855/9856
XRD98L55/98L56
Analog-to-Digital Converter
The analog-to-digital converter is based upon a twostep sub-ranging flash converter architecture with a
built in track and hold input stage. The ADC conversion
is controlled by an internally generated signal, ADCLK
(see Figure 3). The ADC tracks the output of the CDS/
PGA while ADCLK is high and holds when ADCLK is
low. This allows maximum time for the CDS/PGA
output to settle to its final value before being sampled.
The conversion is then performed and the parallel
output is updated, after a 2.5 cycle pipeline delay, on
the rising edge of RSTCCD. The pipeline delay of the
entire XRD9855/XRD9856 is 4 clock cycles.
Graph 1.
Rev. 1.01
13
XRD9855/9856
XRD98L55/98L56
CDS
PGA
10
Reg
IN_POS
ADC
DB[9:0]
IN_NEG
Up/Down
Counter
Reg
Offset Adjust
DAC
XOE
A-B
B
EnableCal
Enable
Offset Reg
State
Machine
ADCLOCK
CCD
Input
CDS
PGA
ADC
DB[9:0]
Automatic
Offset
Calibration
V[1:0]
Manual
Global Offset
V[1]
V[0]
Offset
0mV
25mV (default)
50mV
75mV
Rev. 1.01
14
XRD9855/9856
XRD98L55/98L56
ADDRESS
DATA
(MSB)
SDI
AD1
AD0
Bit 7
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Shifts on
Rising Edges
TSET=10ns min.
SCLK
TSC=50ns min.
TSET=10ns min.
TSET=10ns min.
LOAD
Data
Name
Gain
AD1
0
AD0
0
bit 7
Gain[7]
bit 6
Gain[6]
bit 5
Gain[5]
bit 4
Gain[4]
bit 3
Gain[3]
bit 2
Gain[2]
bit 1
Gain[1]
bit 0
Gain[0]
Offset
Offset[7]
Offset[6]
Offset[5]
Offset[4]
Offset[3]
Offset[2]
Offset[1]
Offset[0]
Mode
Delay
1
1
0
1
V[1]
Dp[2]
V[0]
Dp[1]
M3
Dp[0]
M2
Dd[2]
Test3
Dd[1]
Test2
Dd[0]
M1
Dr[1]
Reset
Dr[0]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 1
bit 0
Gain [7:0]
0 0 0 0 0 0 0 0 - minimum gain (6dB) *
1 1 1 1 1 1 1 1 - maximum gain (38 dB)
bit 7
bit 6
bit 5
bit 4
bit 3
Offset [7:0]
bit 2
0 0 0 0 0 0 0 0 - do not use
0 0 0 0 0 0 0 1 - do not use
0 0 0 0 0 0 1 0 - minimum offset code
0 0 0 0 1 0 0 0 - default offset code, typical offset code 00100000
0 0 1 1 1 1 1 1 - maximum offset code
Rev. 1.01
15
XRD9855/9856
XRD98L55/98L56
bit 7
bit 6
V[1:0]
bit 5
M3
bit 4
M2
bit 3
Test3
bit 2
Test2
bit 1
M1
bit 0
Reset
0 0 - 0mV offset
0 - Clamp only*
0 - RSTCCD*
0 - TestVin off*
0 - test off*
0 - auto detect*
0 - normal*
0 1 - 25mV offset*
1 - no RSTCCD
1 - TestVin on
1 - factory test
1 - manual
1 - reset
1 0 - 50mV offset
1 1 - 75mV offset
bit 7
bit 6
Dp[2:0]
0 0 0 - SHP min delay *
1 1 1 - SHP max delay
bit 5
bit 4
bit 3
bit 2
Dd[2:0]
0 0 0 - SHD min delay *
1 1 1 - SHD max delay
bit 1
bit 0
Dr[1:0]
0 0 - RSTCCD min delay *
1 1 - RSTCCD max delay
Rev. 1.01
16
XRD9855/9856
XRD98L55/98L56
The sampling edge of SHD should be positioned so that
it samples the pixel video level at a stable and repeatable point. The video level should be sampled after the
CCD output has settled from the black level and before
the output transitions to the reset pulse. Aperture
delay TVD needs to be taken into consideration when
positioning the sampling edge of SHD (see Figure
8). This aperture delay is the time from the sampling
edge of SHD to the time the pixel video level is actually
sampled by the CDS. The correct positioning of SHD
will be 5-6 ns prior to where the video level has
adequately settled.
Reset Pulse
RSTCCD
Switch
Turn Off
RSTCCD
Switch
Turn On
TBK
T VD
CCD
Signal
Sample Point
T RST
RSTCCD
SHP
SHD
Rev. 1.01
17
XRD9855/9856
XRD98L55/98L56
Pixel N
CCD
Signal
Sample Pixel
Video Level
Sample Pixel
Black Level
SHP
SHD
RSTCCD
TDL
DB[9:0]
Data N-4
(Output)
Data N-3
Data N-2
Data N-1
Rev. 1.01
18
Data N
XRD9855/9856
XRD98L55/98L56
CDS Clock Polarity
The CLK_POL pin is used to determine the polarity of
the CDS clocks (SHD, SHP, CLAMP). See Figures 10
& 11, and Tables 7 & 8.
Event
Action
Event
Action
RSTCCD
RSTCCD
RSTCCD
RSTCCD
SHP
SHD
SHP
SHD
SHP/SHD
No Action
SHP/SHD
No Action
Clamp Low
High
High
Line N
Active Video
pixels on
OB*pixels
OB LINES
Line N+1
Vertical Shift
Dummy &
OB*pixels
Active Video
pixels on
OB LINES
CCD Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
* Note: OB = Optically Black or Shielded pixels.
Rev. 1.01
19
XRD9855/9856
XRD98L55/98L56
Line N+1
Line N
Active Video Pixels
on Optical Black Lines
Vertical
Shift
OB*
Pixels
Dummy &
OB*
Pixels
Active Video
Pixels on OB line
CCD
Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
CLK_POL=Low
Pixel N
CCD Signal
RSTCCD
1
0
SHP
1
0
SHD
1
0
DB[9:0]
1
0
Data N-4
Data N-3
Data N-2
Data N-1
Rev. 1.01
20
Data N
XRD9855/9856
XRD98L55/98L56
Programmable Aperture Delays
Dp[2:0], Dd[2:0], Dr[1:0]
To help fine tune the pixel timing, the XRD9855/
XRD9856 allows the system to adjust the aperture
delays associated with SHP (TBK), SHD (TVD) and
RSTCCD (TRST) by programming the Aperture Delay
serial port register. On power up these three aperture
delays are set to their minimum values.
Dp[1]
Dp[0]
0
0
0
0
0
1
6ns (default)
8ns
0
0
1
1
0
1
10ns
12ns
1
1
0
0
0
1
14ns
16ns
1
1
1
1
0
1
18ns
20ns
Dd[1]
Dd[0]
0
1
5ns (default)
7ns
0
0
1
1
0
1
9ns
11ns
1
1
0
0
0
1
13ns
15ns
1
1
1
1
0
1
17ns
19ns
0
1
1
0
7ns
11ns
15ns
SHD Aperture
Delay TVD (typ)
0
0
SHP Aperture
Delay TBK (typ)
0
0
RSTCCD Aperture
Dd[2]
Dr[0]
Dp[2]
Dr[1]
Rev. 1.01
21
XRD9855/9856
XRD98L55/98L56
Optically Black Pixels
(OB)
Active Pixels
N+1
N
Figure 13.
OB Pixels
INNEG
RSTCCD
SHP
SHD
Enable_Cal
ADC Sample point
State
RESET
Enable
Cal on
settle
CDS
ADC
ADC
ADC Digcomp/ DAC
CDS
ADC
ADC
ADC Digcomp/ DAC
samples converts converts converts accum Update samples converts converts converts accum Update
input
input
Rev. 1.01
22
0
RESET
XRD9855/9856
XRD98L55/98L56
The timing needed for Frame Calibration Mode is
shown in Figure 16. In Frame Calibration Mode,
Enable_Cal needs to be active during the OB line
output from the CCD. Enable_Cal gates the XRD9855
and XRD9856s auto-calibration logic and must never
be high when CLAMP is active. Clamp still needs to be
active once a line, either during start of line or end of
line OB pixels.
Optically Black
(OB) Pixels
N+1
N
Frame Calibration
(OB) Pixels
Figure 15. OB Lines Used For Frame Calibration on a Typical CCD Array
Line N
Active Video
pixels on
OB*pixels
OB LINES
Line N+1
Vertical Shift
Dummy &
OB*pixels
Active Video
pixels on
OB LINES
CCD Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
* Note: OB = Optically Black or Shielded pixels.
Rev. 1.01
23
XRD9855/9856
XRD98L55/98L56
Clamp Only Timing (XRD4460 compatible)
M1=1, M3=0, NOT RECOMMENDED
In this mode EnableCal is held high, and Clamp is
activated during the Optical Black pixels. While this
mode is available, it is not recommended for best
performance. This timing does not perform frame
calibration.
Line N
Line N+1
Optical Black
Line
Vertical Shift
Dummy &
OB* Pixels
Signal
Pixels
CCD Signal
EnableCal 1
0
Clamp 1
0
Minimum 10 OB Pixels
2 OB Pixels
Internal DC 1
Restore Switch 0
Internal Calibrate 1
0
1
RSTCCD 0
SHP 1
0
SHD 1
0
* Note: OB = Optically Black or Shielded pixels.
CDS
PGA
DC Restore
Switch
Bias
Clk_Pol
Clamp
ADC
Offset
Calibration
Control
Logic
EnableCal
Rev. 1.01
24
DB[9:0]
XRD9855/9856
XRD98L55/98L56
Clamp & EnableCal Timing (XRD9853 Compatible)
M1=1, M3=1
In this mode EnableCal must be active during the large
number of Optical Black pixels (usually at the end of
each CCD line or at the start of a frame), Clamp should
be active during the Dummy pixels (usually at the
beginning of each CCD line).
The EnableCal pin (always active high) directly controls the calibration logic.
Line N
Signal
Pixels
Line N+1
OB* Pixels
Vertical Shift
Dummy &
OB Pixels
Signal
Pixels
CCD Signal
EnableCal
Min. 8 OB Pixels
Clamp
Min. 2 Pixels
RSTCCD
SHP
SHD
* Note: OB = Optically Black or Shielded Pixels.
Figure 19. Clamp & EnableCal Timing, CLK_POL=1, M1=1, M3=1, M2=0
Rev. 1.01
25
XRD9855/9856
XRD98L55/98L56
CDS
PGA
DC Restore
switch
DB[9:0]
ADC
Offset
Calibration
bias
Clk_Pol
Clamp
EnableCal
STBY2
STBY1
CDS/
PGA
ADC
Clock
Inputs
Digital
Outputs
Off
Off
Off
High-z
On
Off
On
High-z
Off
On
On
On
On
On
On
On
Rev. 1.01
26
XRD9855/9856
XRD98L55/98L56
Chip Reset
The chip has an Internal Power-On-Reset function to
ensure all internal control registers start up in a known
state. Pulling the Reset pin high or writing a logic 1 to
the Mode Registers reset bit will also reset the chip to
the Power-up default conditions.
Register
Gain[7:0]
Default
00000000
Notes
minimum gain
OS[7:0]
V[1:0]
00001000
01
code 08 hex
25 mV offset
M3
M2
0
0
Clamp only
RSTCCD required
M1
Test3
0
0
Test2
Reset
0
0
Dp[2:0]
Dd[2:0]
000
000
minimum delay
minimum delay
Dr[1:0]
00
minimum delay
Rev. 1.01
27
XRD9855/9856
XRD98L55/98L56
TestVin
S1
CDS
PGA
ADC
Figure 21. Using TestVin to Access PGA Output & ADC Input
Mode Reg.
TestVin
Normal
AD1
1
1
AD0
0
0
V[1]
0
0
V[0]
0
0
M3
0
0
M2
1
1
Test3
1
0
Test2
0
0
M1
0
0
Reset
0
0
CCD
CCD
Signal
Signal
RSTCCD
RSTCCD
SHP
SHP
SHD
SHD
ADC Clock
(internal)
Track
ADC Clock
(Internal)
Hold
Track
Hold
ADC Data
ADC Data
Rev. 1.01
28
XRD9855/9856
XRD98L55/98L56
Digital Output Power Supplies
VDD
DVDD
Source-Body
Junction Diode
Between DVDD
& VDD
Output
Register
Digital Output
Source-Body
Junction Diode
Between
DGND & GND
GND
DGND
Rev. 1.01
29
XRD9855/9856
XRD98L55/98L56
General Power Supply and Board Design Issues
In general, all traces leading to the XRD9855/XRD9856
should be as short as possible to minimize signal
crosstalk and high frequency digital signals from feeding into sensitive analog inputs. The two CCD inputs,
In_Pos and In_Neg, should be routed as fully differential signals and should be shielded and matched.
Efforts should be made to minimize the board leakage
currents on In_Pos and In_Neg since these nodes are
AC coupled from the CCD to the XRD9855/XRD9856.
The digital output traces should be as short as possible
to minimize the capacitive loading on the output drivers
(see Figure 25)
All of the GND pins, including DGND, should be connected directly to the analog ground plane under the
XRD9855/XRD9856. The VDDs should be supplied
from a low noise, well filtered regulator which derives
the power supply voltage from the CCD power supply.
All of the VDD pins are analog power supplies and
should be locally decoupled to the nearest GND pin with
a 0.1F, high frequency capacitor. DVDD is the power
supply for the digital outputs and should be locally
decoupled. DVDD should be connected to the same
power supply network as the digital ASIC which receives data from the XRD9855/XRD9856.
12V
5V/3V
Regulator
5V/3V
Regulator
VDD
DVDD
DVDD
DB[9:0]
Digital
ASIC
DGND
DGN
D
In_Neg
CCD
In_Pos
GND
XRD9855/XRD9856
AGND
AGND
Application Note
Rev. 1.01
30
to CCD
VDD Signal
NC
25
0.01F
26
29
VRTO
LOAD
30
VDD
27
31
In_Neg
VRT 28
32
34
VRBO
In_Pos
35
VRB
GND 33
36
38
SHD
RESET 23
39
SHP
STBY2 22
40
RSTCCD
STBY1 21
41
GND
42
CLK_POL
VDD
Test 20
GND 19
XRD9855/XRD9856
43
VDD
44
SYNC
45
UNDER
46
DB0
OVER 15
47
DB1
DB9 14
48
NC
EnableCal 18
VDD 17
DVDD
DB5
DB6
DB7
NC
NC
10
11
12
DB4
5
DB8 13
DVDD
0.1F
DB3
4
DGND
DB2
3
NC
OE 16
VDD
CLAMP
NC
0.1 F
SCLK 24
37
From Clock
Signal
Generator
NC
0.1 F
SDI
0.01F
Serial
Interface
0.01F
to CCD
Ground
XRD9855/9856
XRD98L55/98L56
Rev. 1.01
31
0.1 F
VDD
XRD9855/9856
XRD98L55/98L56
2.4
AVDD = DVDD = 5.0V
2.2
VRT = AVDD/1.3
2.0
VRB = AVDD/10
30MHz
MODE = NON-RSTCCD
1.8
en, mV RMS
1.6
27MHz
1.4
1.2
25MHz
1.0
18MHz
0.8
12MHz
0.6
0.4
0.2
0.0
0
32
64
96
128
160
192
GAIN CODES
Rev. 1.01
32
224
255
XRD9855/9856
XRD98L55/98L56
XRD98L55 INPUT REFERRED NOISE
2.0
AVDD = DVDD = 3.0V
1.8
VRT = A VDD/1.3
1.6
VRB = AVDD/10
MODE = NON-RSTCCD
1.4
30MHz
en, mVRMS
1.2
25MHz
1.0
27MHz
0.8
18MHz
0.6
12MHz
0.4
0.2
0.0
0
32
64
96
128
160
GAIN CODES
Rev. 1.01
33
192
224
255
XRD9855/9856
XRD98L55/98L56
48 LEAD THIN QUAD FLAT PACK
(7 x 7 x 1.4 mm TQFP)
rev. 2.00
D
D1
36
25
24
37
D1
13
48
1
2
1
B
A2
C
A
Seating
Plane
A1
L
SYMBOL
A
A1
A2
B
C
D
D1
e
L
a
INCHES
MIN
MAX
0.055
0.063
0.002
0.006
0.053
0.057
0.007
0.011
0.004
0.008
0.346
0.362
0.272
0.280
0.020 BSC
0.018
0.030
0
7
Rev. 1.01
34
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.17
0.27
0.09
0.20
8.80
9.20
6.90
7.10
0.50 BSC
0.45
0.75
0
7
XRD9855/9856
XRD98L55/98L56
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of
patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending
upon a users specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright 2001 EXAR Corporation
Datasheet July 2001
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.01
35