Design analysis of NAND Gate Using Cascode-Voltage Switch Logic

Tanuja Dogra

Rajesh Mehra

ME Student,

Associate Professor,

NITTTR Chandigarh,

ECE Department,

dogra.tanuja@gmail.com

NITTTR, Chandigarh.

Abstract-Cascode-voltage Static Logic(CVSL),a CMOS circuit

I. INTRODUCTION

by f(bar).One of the pull down networks will be ON for

given pattern of inputs and the other will be OFF. the output
is pulled to LOW by the ON pull down network. The pMOS
transistor is turned ON by the low output and the opposite
output goes HIGH. The other pMOS transistor turns off on
rising of opposite output.On the other hand in conventional
CMOS NAND gate ,two series nMOS transistors are there
between output and ground. Also two parallel pMos
transistors are present between output and supply. If either of
the input is0,then one of the nMOS transistors will be OFF
but at the same time one of the pMOS transistor will be ON
resulting in HIGH output.If both the inputs are 1,both the
nMOS transistors will be ON and both the pMOS transistors
will be OFF resulting in LOW output[1]

Cascode voltage switch logic(CVSL) uses both true and

complementary outputs using a pair of nMOS pull-down
networks as shown in fig.1

II.SCHEMATIC DESIGN AND SIMULATION

design technique having various advantages over conventional

CMOS logic in terms of circuit delay,power and flexibility.In
this paper a comparison of CVSL and conventional logic is
carried out by simulation using MICROWIND,of the
performance of NAND gate designed using different circuit
techniques.The parameters compared are power dissipation and
delay constraints(rise and fall delays). CVSL can be more faster
than conventional Cmos,but at the expense of increased device
count and power dissipation.

Keywords: CMOS, CVSL, NAND Gate,

Microwind ,Power Dissipation

The basic principle of a CVSL logic gate lies in between

dynamic logic and static logic.The inputs of the logic gate are
connected to nMOS transistors only and pMOS transistors
are connected in back to back manner with nMOS
transistors.Every gate consists of two outputs which are
opposite to each other.Thus the information bearing signal is
stored on both output nodes.In fig.(2), the nodes labeled as
NAND and its inverse AND are referred to as output
nodes.The conventional NAND circuit configurations is same
as the n-channel circuit configuration on the NAND as well
as the AND side;although AND function is obtained by
inverting the inputs of NAND.The conventional NAND
schematic is shown in fig.(4).

Fig.1 General Schematic of a CVSL logic gate.

The function f is implemented by pull down network while

the inverted outputs feeding transistors are used

Fig.4 Schematic of Conventional CMOS gate

Fig.2 Schematic of CVSL NAND gate

Fig.3 Timing Diagram for CVSL NAND

The stability of the logical operation can be increased by

connecting the two sides sides of the logic gate.The node
NAND or AND is first pulled to logic0 by n-channel
devices when inputs are given to the gate,consequently
providing the logic1to the opposing node.The p-channel
devices help us to decide pull-up time while the n-channel
devices determine the pull down time.The corresponding
analysis is carried out on 90nm CMOS technology.The 90nm
technology is used to obtain all the simulation results.[24]Comparing to static logic,the input node capacitances can
be given be reduced upto a factor of 2 to 5 because the
inputs are given to the n-channel devices.The operating speed
of the circuit depends upon the charging and discharging of
the capacitors which can be increased by reducing the
capacitances.By pulling down one side to logic 1 and the
other side to logic 0,both the outputs can be stabilized.Thus
two stage logic circuit can be made effectively from this logic
gate by using feedback connection.The overall delay for two
input logic gates can be effectively increased by two
parameters-higher stage length and decreased input gate
capacitance.As CVSL supports two gates in one,the
minimum sized CVSL NAND gate delay is 2.1 times of the
traditional CMOS Nand gate.In case of logic gate with higher
inputs,there is reduction in delay in comparison to static
logic.It is so because with higher number of inputs,only one
CVSL logic is required to implement a complex function.On
the other hand two input NAND gates are used in multiple
stages while using conventional CMOS design.[5]The
complex gates that are designed using using CVSL logic gate
are faster than traditional logic gates if more than two logic
levels are used in conventional logic.Also implementation of
complex functions using CVSL gates can operate faster than
conventional logic upto four times.Due to the presence of
cross-coupled pMOS transistors the delay in switching from
high to low will always be less than the delay in switching
from low to high.By using properly sized p-channel
devices,the improvement can be made in these transitions.
III.LAYOUT ANALYSIS
In CVSL logic gate two additional transistors per logic gate
are required in comparison to traditional logic gate which
results in increased layout area per gate.The layout examples
for CVSL NAND gate and conventional CMOS NAND gate
in 90nm technology can be observed in fig.6 and fig.7
respectively.[8-9]

Fig.5 Timing diagram of CMOS NAND

Fig.(8)Analog simulation of CVSL

Fig.6 Microwind layout for CVSL NAND Gate.

Fig.9 Analog simulation of CMOS

Fig.7 Microwind Layout for conventional CMOS NAND
gate
It is observed for this layout that there is increase in area per
gate in comparison to conventional CMOS logic but this is
the case for only two input logic gate.In case of complex
functions,there is only one CVSL gate required due to which
there is decrease in area as per number of inputs used in
CVSL logic gate.The number of inputs will be proportional
to the number of n-channel devices between the output node
and ground.the use of large number of n-channel devices per
gate leads to poor performance of total dose.Thus for CVSL
logic circuits,a compromise exists between total vulnerability
and area.As CVSL requires four n-channel transistorsand two
p-channel transistors for dual logic systems,the charging and
discharging of capacitors associated with these transistors
require more power in comparison to conventional CMOS
NAND gate.[5]
Parameter
Power
Rise Delay
Fall delay
Step Size
Time Scale

CVSL NAND
0.104mW
0.009ns
0.006ns
300(ps)
10ns

CMOS NAND
2.873uW
0.002ns
0.002ns
300(ps)
10ns

IV. CONCLUSION
In conventional logic gates the logic information is stored
only on single node but in cascade voltage switch logic gate
can store logic information on two nodes.The main
conclusion includes that CVSL provides opportunities for
realizing faster circuits which conventional CMOS circuit
cannot.But this advantage is obtained at the expense of cicuit
area and power consumption.
ACKNOWLEDGMENT
I am greatly thankful to honourable DIRECTOR, NITTTR
Chandigarh, Prof.& Head ECE Department Dr. S.B.L
Sachan for their worthy guidance and help in writing this
paper.
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