Reg. No.

MANIPAL INSTITUTE OF TECHNOLOGY

Manipal University
THIRD SEMESTER B.TECH. (E & C) DEGREE END SEMESTER EXAMINATION
NOV/DEC 2014
SUBJECT: ANALOG ELECTRONIC CIRCUITS (ECE - 201)
TIME: 3 HOURS

MAX. MARKS: 50

Instructions to candidates
Answer ANY FIVE full questions.
Missing data may be suitably assumed.
1A. Design the values of R1, R2 and RE for the circuit shown in Figure 1A such that Q-point is 5V,
1.5mA and S=3. Use =70, Vcc=10V, and Rc=2k.
1B. Design an emitter follower circuit with input impedance of 500k and output impedance of 50.
For the BJT, use hie=1k, hfe=50, hre = hoe=0.
1C. Derive an expression for the short circuit current gain for the circuit shown in Figure 1C and plot
the frequency response.
(5+3+2)
2A. Calculate Current gain, Voltage gain, input and output resistance for the circuit shown in Figure 2A.
For the BJT, use hie=1k, hfe=50, hre = hoe=0.
2B. Calculate rbe, rbc and rce for a common emitter amplifier using hybrid pi model at low frequencies.
Assume hie=1k, hfe=50, hre=210-4, 1/hoe=40k, gm=5010-3A/V, IC=1.510-3A.
2C. Calculate all possible hybrid parameters using the graph shown in Figure 2C.
(5+3+2)
3A. Determine the values of fH, fL and mid-band gain for the amplifier circuit shown in Figure 3A.
Assume hie=1.1k, hfe=50, hre= hoe=0, gm=1.410-3A/V, rbe=1k, Cbc=4pF, Cbe=36pF.
3B. For Class A amplifier, considering 2nd order harmonic distortion, derive an expression for output
current and signal power. Sketch the necessary graphs.
3C. It is desired to have a Class B push pull amplifier to supply 5W power to a load of 15 with
Vcc=30V. Assuming transformer efficiency of 75%, calculate turns ratio, collector power dissipation
and conversion efficiency.
(5+3+2)
4A. Calculate voltage gain, input and output impedance for the FET amplifier shown in Figure 4A.
Assume gm=210-3A/V and rd=40k.
4B. Design a Common source amplifier with un-bypassed resistor (Rs) for a gain of -10 and output
impedance of 50k. Assume gm =2*10-3 A/V and rd = 40k.
4C. Determine the values of VGS, ID for the circuit shown in Figure 4C. Assume IDSS=8mA and Vp= 4V
(5+3+2)
5A. For the feedback circuit shown in Figure 5A, i) Determine the transfer function Vf/Vo ii) If the
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network is used in phase shift oscillator determine the frequency of oscillation and minimum
amplifier voltage gain required. The loading effect between this network and amplifier can be
neglected.
5B. For the equivalent circuit of crystal shown in Figure 5B, L=0.33H, C=0.065pF, C=1pF and
R=5.5k. Calculate the series resonant frequency, parallel resonant frequency.
5C. In the transistor sweep circuit shown in Figure 5C, VEE=5V, R=1k, VBE=0, =0.95, C=1F. If the
switch is opened at time t=0, calculate the volatge across capacitor at the end of 1ms.
(5+3+2)
6A. For the circuit shown in Figure 6A, i) Calculate the feedback factor () ii) Current gain without
feedback (I0/Ii) iii) De-sensitivity factor (D=1+A) iv) Current gain with feedback. Use hie=1.1k,
hfe=50, hre= hoe=0.
6B. Verify if the following statements are True or False for the block diagram shown in Figure 6B.
i)
The block diagram represents voltage shunt feedback system
ii)
The type of feedback used here is useful in case of voltage amplifier
iii)
With feedback both the input and output resistance increases.
6C. Fill in the blanks
i)
ii)

Negative feedback increases _____ and _____ Distortion.

Current shunt feedback decreases ____, ____ and increases _____, _____.
(5+3+2)

Figure 1A

Figure 2A

ECE - 201

Figure 1C

Figure 2C

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Figure 3A

Figure 5A

Figure 6A

ECE - 201

Figure 4A

Figure 4C

Figure 5B

Figure 5C

Figure 6B

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