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LCD example
Version 4.0 / september 2009
16*2
As can be seen in Figure 1, control and interface functions are both provided by a KS0066compatible controller, which interprets the incoming commands from the bus and executes
the requested action(s): show the corresponding characters on the display, run configuration
or read commands, etc.
Let us notice that the Information about the timing, instruction set or programming cycles for
this controller is complex and not suitable to be included in a reduced (and far from
complete) manner in this document. Up to this point, a careful and detailed reading of this
information in the original manufacturers datasheet is compulsory.
Here we only list the interface pins/signals of the circuit and, later in section 1.2, we provide
an example of utilization of this device.
The I/O pins and control signals for this circuit are:
pin
symbol
DE2
signal
VSS
Ground (0V)
VDD
description
Page - 2
VO
Contrast Adjustment
RD
LRS
R/W
LWRN
Data/Instruction Selection
LEN
DB0
Data Bus
DB1
Data Bus
DB2
Data Bus
10
DB3
Read/Write Selection
Enable
Data Bus
DB[7..0]
11
DB4
12
DB5
Data Bus
Data Bus
13
14
DB6
DB7
Data Bus
Data Bus / BUSY FLAG
15
A_LED
16
K_LED
17
ON
LCD_ON
IMPORTANT: After writing a character, we must periodically read the data bus bit 7 (DB7), to
check if the operation has already finished; because of that it is called BUSY FLAG.
KEY[1]
DB[7..0]
lcd_machine
Clock_div
nrst
LCD_ON
lcdctrl
clk
nrst
LEN
LRS
LWRN
Example.vhd
OSC_50
KEY[0]
A frequency divider, called clock_div. Since we are using the 50 MHz clock of the
DE2 board, this module is needed in order to fulfil the timing requirements of the
display: clk should have a frequency of 10 MHz or slower.
Page - 3
000
ZZZZZZZZ
101
delay
ZZZZZZZZ
key
001
set1
001111xx
function set
000
mode2
00000110
001
mode1
00000110
001
onoff1
00001111
000
clear2
00000001
000
onoff2
00001111
key
101
charw1
00100011
000
set2
001111xx
on / off control
waitkey
clear display
100
charw2
00100011
010
db(7)
ZZZZZZZZ
db(7)
001
clear1
00000001
db(7)
011
db(7)
readbf1
ZZZZZZZZ
readbf2
Figure 3. State diagram of lcd_machine. Outputs shown on each node/state are rs, rnw, en (upper
box), and data[7..0] (lower box).
Figure 4 shows the VHDL code of the module example.vhd. Remember that you must add
the frequency divider for proper work and visualisation.
: in std_logic;
: inout std_logic_vector(7 downto 0);
: out std_logic);
-- arc_example
LCD_ON <=
'1';
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when
when
when
when
when
when
set1|set2,
onoff1|onoff2,
clear1|clear2,
mode1|mode2,
charw1|charw2,
others;
Page - 5