Wireless Infrared Communications Link

ECE 310-01
Spring 2004
Eric Tollefson (CM 1316)
John Morahn (CM 1500)
April 23, 2004

Summary
In this project we were tasked with building an infrared communications system.
There were two sections to this system. The transmitter generates a pseudorandom unipolar
NRZ signal, modulates, and transmits this signal. The receiver captures, demodulates, filters,
and recovers the random data. Our system succeeded in doing all of these things without
errors for a range of up to six feet.

Design Overview
Our communications system had two major components: the transmitter and the
receiver. The transmitter unit generated a pseudorandom data stream, coded and modulated
the data, and then transmitted it via infrared. A block diagram of the system is shown below
in Figure 1. In this system, actual data was simulated by a pseudorandom sequence
generator to make testing easier and more practical. The resulting bit stream is in the form
of a unipolar NRZ signal, which is then modulated by a square-wave carrier. The resulting
signal drives an infrared LED.
Data
Clock

Modulator

Pseudorandom
Sequence
Generator

Infrared
LED

Carrier
Generator
Figure 1 - Block Diagram of Transmitter

The receiver unit then captures the infrared signal, demodulates it, and recovers the
data stream, as shown in Figure 2 below. The phototransistor converts the infrared signal
into a current, which is then converted again into a voltage with an op-amp circuit. This is
then bandpass filtered to reduce noise and eliminate the DC offset. An envelope detector
rectifies the signal and uses a lowpass filter for demodulation. A second lowpass filter also
averages the envelope over many bit periods to provide a threshold value. The resulting
envelope and average are fed into a comparator, which determines whether the signal
represents a 1 or a 0, and finally into a flip-flop which samples the signal to generate the
final output data. The sampling times are determined by a timing recovery circuit, which
consists of an edge detector driven by the comparator output and a phase-locked loop.

Current-toVoltage
Converter

IR Phototransistor

Bandpass
Filter

Comparator

Envelope
Detector

Data Out

Sampling
Flip-Flop

Timing
Recovery
Figure 2 - Block Diagram of Receiver

Transmitter Detail Design

The full transmitter unit was built up over the course of a few weeks laboratory.
The main component of this is the pseudorandom sequence generator (PSG). This consists
of a 4-bit shift register. The input of the register is connected via a XOR gate so that it
cycles through the full 15 possible states (excluding 0000) before repeating, which makes
the data stream as random as possible for this size register. The logic diagram for this circuit
is shown below in Figure 3.
U5
3

1
2

XOR2

U1
2
3

D
CLK

DFF

U2

2
3

U4

U3

2
3

CLK

DFF

CLK

DFF

2
3

Data Out

CLK

DFF

Clock In

Figure 3 - PSG Logic Diagram

For efficiency and simplicity, this logic was implemented using a programmable
GAL device, the Lattice GAL22V10D. In addition to the logic in Figure 3, the GAL also
includes an asynchronous reset and logic to prevent the 0000 state. This is necessary
because if the PSG enters the 0000 state it will become stuck and remain there indefinitely.
The program for our GAL device, which can be found in Appendix B was written in the
Verilog hardware description language. Finally, we inverted the clock on the PSG to make
the flip-flops falling-edge triggered. Because the sampling flip-flop in the receiver is risingedge triggered, this introduces a half-cycle difference which allows for delay and clock skew
in the system. This is needed during the early stages of testing when we are still transmitting

the clock on a wire between the transmitter and receiver. The GAL circuit is shown in
Figure 4 below.
Inv erted Clock
U10
100Hz Clk

2
3
4
5
6
7
8
9
10
11
13
1

+5V

24

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I
I
I
I
I
I
I
I
I
I
I

14
15
16
17
18
19
20
21
22
23

PSG

I/CLK
VCC

GND

12

GAL22V10

Figure 4 - GAL implementation of PSG

The clock to drive the PSG was created using a standard 555 timer circuit. We used
the astable mode of operation and chose components for a clock frequency of about 100
Hz. The circuit and equations used to calculate component values were found on the
datasheet. Our exact circuit is shown below in Figure 5.
+5V

+5V

6
2

TRG

100Hz Clk

LM555

RST
CV

+5V

5
C11

C10
0.1u

THR
GND

+
R17
56k

OUT

DSCHG

VCC

U9

+
R15
22k

0.01u

Figure 5 - 100 Hz Clock Circuit

To generate the square-wave carrier needed to modulate our signal, we used a second
555 timer. This was originally supposed to be one of the lab function generators, but we
decided to make our transmitter self-contained for greater portability. The same circuit
topology and design method was used as before, with the frequency changed to about 36
kHz. This circuit is shown in Figure 6 below.

+5V

+5V

+
+
R19
18k

6
2

VCC

U11

36kHz Carrier

THR
TRG

LM555

RST

+5V

CV

C13
0.01u

C12
0.01u

OUT

DSCHG

GND

R18
8.2k

Figure 6 - 36 kHz Carrier Generator

Finally, we used a pair of 2N3904 NPN transistors, shown below in Figure 7, to

generate the modulated data waveform needed to drive our infrared LED. This was
necessary to drive the LED near its maximum rating of 70 mA, because output of our ICs
cannot source that much current. The base resistors, R13 and R14, are used to limit the
current draw from the GAL and 555 outputs. The series resistor R16 sets the LED current.
This value was originally calculated during the first pre-lab, but was subsequently changed to
compensate for the additional voltage drop across each of the transistors in their on state.
+5V
R13
36kHz Carrier

Q1
2N3904/TO

1k
R14

PSG

Q2
2N3904/TO

1k

+
R16
41
D3
LED

Figure 7 - Modulation Circuit

Receiver Detail Design

The data stream generated by the transmitter is received by a phototransistor. As
light excites this biased phototransistor, it acts as a current source. The current produced is
then linearly converted to a voltage signal. The op-amp circuit that does this is shown in
Figure 8. The value of R6 controls the gain of the conversion.

+5V

VCC
U4A

U3
3 +

To Filter

2 TL072/TO

R6

+
30k

Figure 8 Current to Voltage Converter

The voltage waveform is then sent to the 2nd order active Butterworth filter in Figure
9. This is a band pass filter centered at about 36 kHz with a -3dB bandwidth of 5 kHz. The
filer removes both the DC offset that the current to voltage converter adds as well as any
60Hz and 120Hz noise that room lighting adds.
+12
8

U2A

TL072/TO
3

R1

R2

13k
13k

C3

-12V

R3

+
+

330p

13k

R4

-12V
4

13k

TL072/TO

R5
5
C4

130k

to Env elope Det.

330p

From I to V

U2B

+12V

Figure 9 Active Butterworth Filter

The filtered signal is then fed to an envelope detector, shown in Figure 10. This
circuit takes the AC waveform that comes from the filter, rectifies the positive half of the
signal, and then passes it through a lowpass filter. There are two separate lowpass filters.
The first has a cutoff of about 4.8 kHz and is outputs the envelope of the incoming signal.
This frequency was chosen to give a time constant slightly longer than a single 36 kHz
period. The second lowpass filter has a cutoff of 1.6 Hz and gives the average value over a
large number of bit periods, which is used as a threshold for the comparator.

R7

+
R8

10k
-12V

D2

R10

+
D1N4148

100k

C5

R12

+12V

Env elope

330p

1k

TL072/TO
1

D1
D1N4148

U4A

R9
From Filter

10k

100k

0
C6
0.1u

Threshold

Figure 10 Envelope Detector

The envelope and threshold signals are then fed to the comparator shown in Figure
11. This compares the envelope signal to the threshold to make the bit decisions and reproduce the digital data.
+5V
+5V
8
5
6

U7

2 +

Threshold

3 -

R11
7

4
1

Env elope

1k
Data to Timing

LM311/TO

00

Figure 11 Comparator Circuit

Now that a binary signal is present, the timing information must be recovered so that
this signal can be sampled to properly reconstruct the data stream. The circuit in Figure 12
performs this function. The GAL22V10 handles the timing recovery while the 7474 D flipflop does the sampling.

1
+5V

24

I
I
I
I
I
I
I
I
I
I
I

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

14
15
16
17
18
19
20
21
22
23

+5V
U6A
2
DFF trigger

+5V

I/CLK
VCC

3
1
4

D
CLK
CLR
PRE
7474

GND

Q
Q

12

GAL22V10

5
Data Out
6

GND

2
3
4
5
6
7
8
9
10
11
13

14

reset

VCC

U5

Data f rom Comparator

Figure 12 Timing Recovery & Data Reconstruction

The GAL recovers timing by detecting a rising or falling edge in the data stream.
This is done by a 2-stage flip-flop buffer on the incoming signal, which operates on a 1.6
kHz clock (16 times the data rate). When the outputs of the two stages are different, the
detector assumes that an edge is present and sends out a synchronization pulse. The GAL
contains a divide-by-16 counter, also operated at 1.6 kHz. This counter outputs the
recovered clock, which is low for the first half of the count cycle (0-7) and high for the
second half (8-15), generating a clock at 100 Hz. When the counter receives a
synchronization pulse from the edge detector, it resets to zero and begins counting again.
Thus, the clock pulse which triggers the DFF to sample the input signal always occurs half a
bit period after each edge, which is the condition for minimum intersymbol interference
(ISI). The clock will drift slightly over a repeated series of bits (i.e. 111), but this is only a
problem for extremely long sequences. The block diagram for this process is shown below
in Figure 13.

Data In
Reset

Edge
Detector

16 bit Counter

1.6 kHz Clock

Figure 13 - Timing Recovery Logic Diagram

DFF
Sync

Results
Our full communications unit works well, with a very low bit error rate up to a range
of about 6 feet. We are confident that the range could be extended further with an increase
in the transmitter power or an increase in the receiver gain, but we did not attempt to find
the extreme limits of the system. Figure 14, below, shows the functional system with input
data from the PSG and output data from the receiver flip-flop. Note the phase difference of
approximately one-half clock cycle between the two waveforms. This is because the flipflop samples the incoming signal in the center of the bit period to minimize ISI.

Figure 14 - Input and Output Data Streams

In addition to the full-system test, we also verified the individual components. On

the transmitter side, we looked at the bit clock, PSG output stream, and modulated data
signal, shown in Figure 15. Not shown below is the carrier wave, which was measured to
have a frequency of 35.71 kHz. The bit clock has a measured frequency of 94.3 Hz. This
screen capture shows one full cycle from the PSG, which is 15 bits long. Note that it is
falling-edge triggered. The modulated data signal shows the on-off keying pattern of the
carrier wave.

Figure 15 - Transmitter Unit Verification

On the receiver side, we began by looking at the signal path through the
amplification and demodulation stages, shown in Figure 16. The output from the currentto-voltage converter clearly shows the received carrier during the 1s and the unipolar
nature of the signal at this stage. Also, note the large noise signal superimposed on the data.
This signal is approximately 120 Hz and is caused by the florescent lighting in the lab. After
the bandpass filter, the keyed carrier wave is still easily distinguishable. Our bandpass filter
has a center frequency of 36.34 kHz and a Q of 10.9. Here we can see that the 120 Hz noise
has been greatly reduced and that the signal is now bipolar with no DC offset. Next, the
signal passes through an envelope detector for demodulation. As we can see, the envelope
detectors output it not a unipolar, nearly binary signal with a limited amount of ripple.
Finally, the envelope detector output drives a comparator. The threshold for this
comparator is provided by the averaging output of the envelope detector. Note how the
comparator output swings high when the carrier is keyed on and low when the carrier is off,
demonstrating correct operation.

Figure 16 - Receiver Demodulation Process

10

The second part of the receiver is the clock recovery circuit. The operation of this
unit is shown below in Figure 17. The comparator output drives the edge detector. As we
can see, the edge detector produces a synchronization pulse at each edge in the data stream.
This pulse is used to reset the divide-by-16 counter which provides the clock used to sample
the data. Note that each rising edge of the recovered clock appears almost exactly in the
center of the incoming data bits, providing maximum ISI immunity. We can also see slight
variations in the period of the recovered clock, especially after long periods of repeated bits,
which show that the system is compensating for drift between the two clocks. This
demonstrates that the clock recovery is operating correctly.

Figure 17 - Clock Recovery Process

Conclusions and Recommendations

The performance of our full communications system met the desired specifications
for full functionality. We were able to operate the system at a maximum range of
approximately six feet without bit errors. Since we did not have a formal method to
determine the bit error rate, we displayed several full PSG cycles on the oscilloscope. If
both input and output were visibly identical, we considered the system to be operating
correctly.
The main failure mode in our system is the transmitter power and inefficient
channel. Our infrared LED has a limited power output, and more importantly, has an
annular beam pattern with a null in the center of the beam. Due to this limitation, it was
difficult to direct the infrared beam to the receivers phototransistor. To solve this problem,
we could use an LED with higher power capability and a more tightly-focused beam. The
laboratory was also a very noisy optical environment. We had to deal with both sunlight
from the windows and the 120 Hz signal from the overhead lights. If even greater range is
required, additional optics such as lenses, IR filters, and ambient light shields could be used
to reduce these difficulties.
A simpler way to achieve some additional performance gain would be to increase the
gain in the receivers bandpass filter and half-wave rectifier stages. This increase would allow
the receiver to respond to lower signal levels from the transmitter, allowing greater distance.
11

However, this would also cause an increase in the noise level of the circuit and might cause a
saturation problem when operating at shorter ranges. It would also be possible to increase
the gain in the current-to-voltage converter, but this would dramatically increase both noise
and the DC offset, making improvements in the other stages more practical. Because of
these difficulties, increased gain can extend the performance of the system to a certain
degree, but there are limitations on how much improvement can be obtained.
Overall, my partner and I both enjoyed this series of labs. It was a nice change of
pace to spend our time building a real, functioning system with applicability outside of that
lab period. We also liked the approach of building a very simple system at first, then
gradually adding features to increase functionality and capabilities. One disadvantage of this
project was its heavy dependence on many other classes, several of which are not direct
prerequisites. However, we do not feel that is a bad thing because it is an accurate reflection
of engineering outside the academic environment. We were both glad to have extensive
work experience at Rose-Hulman Ventures, which prepared us to neatly build and debug
large circuits such as this one.

Appendices
Appendix A: Complete Schematics
Appendix B: Pseudorandom Generator Verilog Code
Appendix C: Clock Recovery Verilog Code
Appendix D: Pictures of System

12

Appendix A: Complete Schematics

+5V

+5V

+
8

U11

U8

LM7805C

10u

OUT

IN

C7

C8
100u

GND

C9
1n

R19
18k

6
2

TRG

+
LM555

0
+5V

36kHz Carrier
+5V

RST
CV

+5V

R13

36kHz Carrier

THR

C12
0.01u

Power in

OUT

DSCHG

1
2

VCC

+5V

GND

R18
8.2k

J1

C13
0.01u

Q1
2N3904/TO

1k
R14

PSG

Q2
2N3904/TO

1k

+5V

Inv erted Clock

R16

+
+
6
2

100Hz Clk

TRG

LM555

RST
CV

+5V

5
C11

100Hz Clk

THR

C10
0.1u

OUT

DSCHG

GND

7
R17
56k

41

U10

VCC

U9

R15
22k

0.01u

2
3
4
5
6
7
8
9
10
11
13
1

+5V

24

I
I
I
I
I
I
I
I
I
I
I

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

14
15
16
17
18
19
20
21
22
23

D3
LED

0
PSG

I/CLK
VCC

GND

GAL22V10

12

Figure 18 - Complete Transmitter Schematic

13

R7
+5V

+
R8

+
VCC

To Filter

From Filter

2
1k

TL072/TO

TL072/TO

D2

R10

100k

D1N4148

R6

C5

2 -

D1
D1N4148

U4A

Env elope

330p
R12

R9

3 +

10k
-12V
4

U4A

U3

10k

+12V

100k

Threshold

C6
0.1u

30k

0
+12
8

U2A

TL072/TO
3

R1

R2

13k
13k

C3

+
-12V
4

13k

2 +

Threshold

3 -

R11
1k

Data to Timing

to Env elope Det.

LM311/TO

5
C4

U2B

Env elope

TL072/TO
-

6
R5
130k

8
5
6

13k

4
1

330p

U7

00

330p

From I to V

+5V

R3

R4

+5V

-12V

+12V

+5V
U1
C1
1u

IN

LM7805C
GND

1
+5V

24

+5V
U6A
2
DFF trigger

+5V

I/CLK
VCC

3
1
4

GAL22V10

CLK
CLR
PRE
7474

GND

14

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I
I
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I
I
I
I
I

VCC

reset

14
15
16
17
18
19
20
21
22
23

12

5
Data Out
6

GND

U5
2
3
4
5
6
7
8
9
10
11
13

Data f rom Comparitor

Figure 19 - Complete Receiver Schematic

14

OUT

+12V

C2
1u

Appendix B: Pseudorandom Generator Verilog Code

module PSG(clk,clk_in,inv_clk,reset,out,sync);
input clk;
input clk_in;
input reset;
output inv_clk;
output sync;
output [3:0] out;

// Clock input
// Input to clock inverter
// Reset input
// Inverted clock output
// Synchronization pulse output
// Pseudorandom sequence output

reg sync;
reg [3:0] out;
wire xor1;

// Wire for XOR gate 1

assign inv_clk=~clk_in;
assign xor1=out[3]^out[0];

// Create clock inverter

// Create XOR gate

always @ (posedge clk or posedge reset)

if (reset)

// Asynchronous reset
out<=0;

else
if (out==0)
out<=4'b0110;
else begin
out[3]<=xor1;
out[2]<=out[3];
out[1]<=out[2];
out[0]<=out[1];
end

// Exit from 0 state

// Shift register

always @ (posedge clk or posedge reset)

state
if (reset)
sync<=0;
else
if (out==4'b1111)
sync<=1;
else
sync<=0;

// Generate sync pulse on 1111

endmodule

15

Appendix C: Clock Recovery Verilog Code

Top-level Module
module TimingRecovery(ClockIn,Data,reset,S,CDiv);
input ClockIn;
input Data;
input reset;
output S;
output CDiv;
wire CDiv;
wire S;
wire R;
ClockDiv
ClockSync

U1(.ClockIn(ClockIn),.ClockOut(CDiv),.R(R));
U2(.In(Data),.clk(ClockIn),.SyncOut(S),.R(reset));

assign R=reset|S;
endmodule

ClockDiv Sub-module
module ClockDiv(ClockIn,ClockOut,R);
// Define parameters
parameter bits=4;
parameter Max=15;
parameter dur=8;

// Counter size parameter

// Speed of divider
// Duty cycle (high time in 50 MHz cycles)

// Port Declarations
input ClockIn,R;
output ClockOut;
// Registers
reg [bits:0] count;
reg ClockOut;

// Counter register

always @ (posedge ClockIn or posedge R)

if (R)
count<=0;
else if (count==Max)
count<=0;
else
count<=count+1;

// Counter

always @ (count)
if (count<dur)
ClockOut<=1'b0;
else
ClockOut<=1'b1;

// Output logic

endmodule

16

ClockSync Sub-module
module ClockSync(In,clk,SyncOut,R);
// Port Declarations
input clk,R;
input In;
output SyncOut;

// Input Data bus

// Output SyncOut pulse

// Registers
reg Buf1,Buf2;

// Buffer registers

// Functionality
always @ (posedge clk or posedge R)
if (R)
Buf1<=0;
else
Buf1<=In;

// Buf1 register

always @ (posedge clk or posedge R)

if (R)
Buf2<=0;
else
Buf2<=Buf1;

// Buf2 register

assign SyncOut=~(Buf1==Buf2);

// Pulse output if not equal

endmodule

17

Appendix D: Pictures of System

Figure 20 - Completed Transmitter Unit

Figure 21 - Completed Receiver Unit

18