RSM2013 Proc.

2013, Langkawi, Malaysia

Memristor Based Delay Element

Using Current Starved Inverter
Siti Musliha Ajmal Binti Mokhtar, Wan Fazlida Hanim Wan Abdullah,Member, IEEE
Faculty of Electrical Engineering
University Teknologi Mara
Selangor, Malaysia
sitimusliha7@gmail.com

AbstractThis paper will first review on some applications of

newly found passive element, the memristor. Utilizing the
beneficial characteristic of memristor where it can remember its
last state, more and more improvements on today electronic
designs has been proposed. However, it is crucial to observe the
behavior of memristor model before applying into circuits,
especially when the memristor is coupled with other devices. In
this paper, LTspice memristor model is used to simulate
memristor behavior and applied to the basic delay element circuit.
The circuit used a tristate inverter as the delay element. It
controls the current flowing to the parasitic capacitor, thus
controlling the delay. The compatibility of memristor with the
delay element is also in consideration to ensure the functionality of
the circuits. At the end, a basic delay element using inverter and
memristor is presented. This paper is divided into 4 sections,
including the introduction where few examples of memristor
applications are explained. It follows by next section where the
inverter delay characteristic is narrated. Section 3 is about a
mathematical model of memristor that been used to provide a
specific memristor resistance in order to get certain delay value
during simulation. Using LT spice, a memristor based delay
circuit design is then proposed and the delay is observed by circuit
simulation. In conclusion, the calculated R and delay value is then
compared to the simulation result in order to verify circuit
functionality.
Keywordsmemristor applications, memristor resistance spice
model, tristate invert, delay element

I.

INTRODUCTION

Since the discovery of memristor, so-called fourth passive

element as claimed by Leon Chua in his paper [1] (other three
are resistor, capacitor and inductor), by Stan Williams and his
group at HP lab [2], [3] many researchers have raised their
attention towards memristor application. Among rising
application is the non-volatile memory [4] (specifically the nonvolatile random access memory, NVRAM) which using
memristor ability to remember its last state. The fouder of
memristor, Hewlett Packard has developed a crossbar latch
memory and reportedly currently about one-tenth the speed of
DRAM. There is also a presentation of low power and remote
sensors that using memristor. The memristor is coupled together
with memcapacitors and meminductors as presented in [5] to
produce nano-scale low power memory and distributed state st
orage. This is also as part of NVRAM development.

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Mass researches have widely been conducted to overcome the

limitation of transistor scaling by replacing transistor with the
memristor in circuits. The electronic manufacturers have taken
great interest on memristor as a replacement of transistor to
overcome the barrier of miniaturization and microprocessor
controller development. The crossbar latch is an extension of
memristor that responsible on transistor replacement in future
computer though it may consumes more funds along its
realization.
Memristor based logic circuit is also one of rising topic in
memristor application. Logic circuits such as AND, OR, NOR,
NAND and even more complex ADDER using memristor have
been presented in [6]. The memristor based logic circuit is
reported to have more density improvement compared to
CMOS logic family.
In this paper, a basic delay element using inverter and
memristor is presented as followed; Section 2 will discuss on
the inverter delay characteristic where the delay of the inverter
depends on size of output capacitor and (dis)charging current
that flow through the inverter. The proposed design has
implemented a tristate inverter as the current starved inverter
where the (dis)charging current is controlled by using a
memristor. In section 3, a mathematical model of memristor is
used to provide a specific memristor resistance in order to get
certain delay value. Next, in section 4, Rmin and Rmax is
calculated to get resistance range and thus to estimate maximum
and minimum delay of our delay element. A memristor based
delay circuit design is then proposed. In conclusion, the
calculated R and delay value is then compared to the simulation
result in order to verify circuit functionality.

II.

DELAY ELEMENT U SING M EMRISTOR AND INVERTER

A. Inverter Delay Characteristics

The inverter delay characteristic can be approximated as a
CMOS inverter that charging the CLoad or discharging the CLoad
as shown in Fig. 1. If Vin switches high, the gate voltage for
transistors becomes high (usually to the amount of VDD). Thus,
NMOS turns on and discharges CLoad while the PMOS turns off.
In reverse, if Vin switches low, the gate voltage is low (usually
to the amount of 0 or ground). Thus, PMOS turns on and

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RSM2013
Proc. 2013, Langkawi, Malaysia
charges CLoad while the NMOS turns OFF. The rising (falling)
time depends on time that is taken to fully discharge (charge)
the CLoad by NMOS (PMOS). In conclusion, the rising and
a the amount of
falling time depends on the size of CLoad and
current flow through PMOS and NMOS.
There are three common types of delay ellement; using shunt
capacitor to controlled Cload size, using resisttor and lastly using
current starved inverter to control the current which is
implemented by a tristate inverter in the proposed design.

the drain connected to voltage supply and ground. Therefore,

the gate voltage of stacked transsistors can control the amount of
current flow to middle inverter.. If the gate voltage is big, than
the current flows is also large. Otherwise,
O
if the gate voltage is
small, than only a little of currrent can flow. This is what it
means as current starved invertter, where we starve the current
flow to middle inverter.

(dis)charging cu
urrent
(aa)

Fig. 1 CMOS inverter with load cappacitance

Delay Time Derivation: NMOS Discharging Cload

Firstly, assume Vin switches abruptly from
m V LOW to VHIGH
(VLOW = 0 and VHIGH = VDD for CMOS) ass shown on Fig. 2.
We are interested in the delay time for Vout to fall from VHIGH
to the 50% point, i.e. to the value 0.5 x (V
VHIGH + V LOW). For
CMOS, it is time when Vout is half the VDDD. For Vout between
VHIGH and VHIGH VTN, the NMOS is in satturation. Therefore,
we can expressed the
by using
forrmula in saturation
region.

The delay can be calculated using equation below.

b

(bb)
Fig. 3(a) Current starved tri-statte inverter and (b) delayed clock

As stated in expression (1), thee inverter delay is determined by

the size of load capacitance and amount of (dis)charging
current. To apply a current starvved inverter as controllable delay
element, we control the gate vooltage of M3 and M6. In other
words, we control the (dis)chharging current of the output
parasitic capacitor C of middle inverter
i
which composed by M4
and M5, thus regulate the propaagation delay of this element. A
current mirror M1 and M2 conttrols the gate voltage of M3 and
M6 where M6 control the risingg edge of input signal and M3 is
otherwise. Sometimes, multiple cascaded inverters are put after
the current inverter as buffers for improving the rise and fall
edges of the delayed output. Fig. 4 shows basic circuit of
voltage controlled current starvee delay element, implementing a
current starved inverter. Here, a memristor is applied to control
the current as shown in Fig 5. The memristor is connected in
parallel with a NMOS transistoor and in series with a current
source. The description is as folllows:
Assuming circuit in saturation region
r
and
can get the
for each
from
m equation (2),

, we

From equation (4) and (5), wee can determine maximum and
minimum R value of the memrisstor.

Fig. 2. NMOS delay time derivatioon

I .

B. Current Starved inverter with memristor

Proposed design uses a tristate inverter as the current starved
as shown in Fig. 3. Unlike a common invverter, this tri-state
inverter has a stack of PMOS transistor and NMOS
N
transistor at

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MATHEMATICAL MODEL FOR M EMRISTOR RESISTANCE

In order to apply memristor with

w a specific resistance value,
two memristor mathematical models
m
have been used; a model
for a sinusoidal input and a moddel for DC input.

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RSM2013
Proc. 2013, Langkawi, Malaysia
previous memristor behavior grraph (Fig 6). Then t is input at
the model equation and that is how
h
the memristor resistance is
gained for the delay element.

Fig. 4 Basic circuit voltage controlled current starved

s
inverter

(a)Resistance versus timee for sinusoidal input with

Fig. 5 Memristor based current starved inverter

i

For a sinusoidal input, the instantaneeous resistance of

memristor for linear dopant f(x) as presenteed in [7] is shown
below:
(a)Resistance versus time for DC input with

where

is the initial memristoor resistance,

, is the dopant drift mobility, is the frequency,
is the amplitude for sine input. As we can seee, resistance R is a
time and input frequency dependent, which mean memristor
have different R for each time of applied volttage and also varies
according to the sine frequency.
For a DC input, the instantaneous resistannce of memristor as
presented in [8] is shown below:
where
is the DC signal voltage. For a memristor with a DC
input, the dopant boundary will move in one direction towards 0
or D limits depending on the sign of the innput voltage. Fig. 6
shows a comparison between calculation annd simulation value
of memristor resistance with (a) sinusoidal input and (b) DC
input based on memristor SPICE modelass presented in [9]
which we can see that they match to each otther. Here, as stated
before, once resistance reached the bounddary of the device,
memristor will act as constanst resistance tennds to
or
.
However, for DC input, the calculated matheematical model has
not taken window function f(x) for nonliinear dopant drift,
therefore the resistance keeps increasing withh times.
I . SIMULATION RESULT AND DISCUSSION
A memristor model as shown in Tablle 1 that includes
equation (6) and (7) is built to get specific R values to be used
in the delay element. Since the R is time dependent,
d
for each
preferred R will be at different t, thus t is estimated from

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87

Fig. 6 Comparison of memristance resistance between calculation and SPICE

simulation with (a) sinusoidal input and (b) DC input

TAB
BLE 1
SPICE MODEL FOR INSTA
ANTANEOUS RESISTANCE
* HP Memristor SPICE Model
* Instantaneous memristor resistancee *
**************************
* Ron, Roff - Resistance in ON / OFF States
* Rinit - Resistance at T=0
* D - Width of the thin film
* uv - Migration coefficient
* p - Parameter of the WINDOW-funnction
* for modeling nonlinear boundary conditions
c
* x - W/D Ratio, W is the actual widdth
* of the doped area (from 0 to D)
.SUBCKT Rmem plus minus PARAMS:
+ Ron=100 Roff=16K Rinit=1K D=110N uv=10F freq=1 Vo=1.2 t=xxxx
************************************************
* For sinusoidal input only
************************************************
;Rmem plus minus value={sqrt(Rinitt**2(sin(pi*t)**2)*2*Vo*(uv*Ron/D**22)*(Roff-Ron)/(pi*freq))}
************************************************
* For DC input only
************************************************
Rmem plus minus value={sqrt((Rinit**2+2*Vo*(uv*Ron/D**2)*(RoffRon)))}
.ENDS Rmem

RSM2013 Proc. 2013, Langkawi, Malaysia

In order to estimate R range, maximum
is derived from equation (5).

and minimum

,
and
Here,
. From value
,
, the current that flow through
capacitor can be calculated. Thus delay range can be estimated
by calculating
and
from equation (3).

s.
(b) memristor resistance R=10.5k and output delay
Fig 8. Delay output with maximum and minimum memristor resistance.

Here,
F. In order to simulate delay element in
SPICE, a circuit has been designed as shown in Fig. 7. Fig 8
shows a delayed output of (a) maximum memristor resistance
and (b) minimum memristor resistance. From simulation result,
we can see that calculated maximum and minimum resistance
and delay are matched with the simulation result. Therefore, we
can use calculation above to estimate any delay at any
resistance which is the main purpose of the proposed design.

CONCLUSION

A newly discovered element, memristor has been applied to a

conventional delay element. Using memristor ability to
remember its last state, the memristor resistance will never
change unless a bias is applied to it. This can help to reduce
power consumption and can be used as a variable resistor,
without adding up extra area. Though the delay is not quite
specific and nonlinear, this delay element still can be improved
and that will be the next to be discussed. The delay element
application can be as delay generator in delay locked loop and
as sample and hold circuit in analog to digital converter. Further
discussion on its application is also in progress.
ACKNOWLEDGEMENT
The authors would like to thanks Ministry of Higher Education
(MOHE) and Research Management Institute of Universiti
Teknologi MARA (UiTM) for providing financial support
under excellent fund grant 100-RMI/SF 1/16/2 (31/2012).
REFERENCES
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[3]
[4]

Fig.7. Memristor based delay element circuit design

[5]

[6]

[7]

[8]

[9]
(a) memristor resistance R=1k and output delay

s.

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