CSC 326 Transformer Protection Ied Technical Application Manual v1 02

CSC-326
Transformer Protection IED

Technical Application Manual
CSC-326 Transformer
Protection IED
Technical Application Manual
Compiled: Jin Rui

Checked: Hou Changsong
Standardized: Li Lianchang
Inspected: Cui Chenfan
Version V1.02
Doc.Code0SF.450.085(E)
Issued Date2014.12.25
VersionV1.02
Doc. Code0SF.450.085(E)
Issued Date2014.12
Copyright owner: Beijing Sifang Automation Co., Ltd
Note: the company keeps the right to perfect the instruction. If equipment does not agree
with the instruction at anywhere, please contact our company in time. We will provide you
with corresponding service.
is registered trademark of Beijing Sifang Automation Co., Ltd.

We reserve all rights to this document, even in the event that a patent is issued and a different
commercial proprietary right is registered. Improper use, in particular reproduction and dissemination to third parties, is not permitted.
This document has been carefully checked. If the user nevertheless detects any errors, he is
asked to notify us as soon as possible.
The data contained in this manual is intended solely for the product description and is not to be
deemed to be a statement of guaranteed properties. In the interests of our customers, we
constantly seek to ensure that our products are developed to the latest technological standards as a result; it is possible that there may be some differences between the hardware/software product and this information product.
Manufacturer:
Beijing Sifang Automation Co., Ltd.
Tel: +86-10-62961515
Fax: +86-10-62981900
Internet: http://www.sf-auto.com
Add: No.9, Shangdi 4th Street, Haidian District, Beijing, P.R.C.100085
Preface
Purpose of this manual
This manual describes the functions, operation, installation, and placing into service
of device CSC-326. In particular, one will find:
Information on how to configure the device scope and a description of the device
functions and setting options;
Instructions for mounting and commissioning;
Compilation of the technical specifications;
A compilation of the most significant data for experienced users in the Appendix.
Target Audience
Protection engineers, commissioning engineers, personnel concerned with
adjustment, checking, and service of selective protective equipment, automatic and
control facilities, and personnel of electrical facilities and power plants.
Applicability of this Manual

This manual is valid for SIFANG Distance Protection IED CSC-326; firmware version
V1.00 and higher
Indication of Conformity
Additional Support
In case of further questions concerning IED CSC-326 system, please contact
SIFANG representative.
Safety information
Strictly follow the company and international safety regulations.

Working in a high voltage environment requires serious approch to
aviod human injuries and damage to equipment
Do not touch any circuitry during operation. Potentially lethal

voltages and currents are present
Avoid to touching the circuitry when covers are removed. The IED
contains electirc circuits which can be damaged if exposed to static
electricity. Lethal high voltage circuits are also exposed when covers
are removed
Using the isolated test pins when measuring signals in open circuitry.
Potentially lethal voltages and currents are present
Never connect or disconnect wire and/or connector to or from IED

during normal operation. Dangerous voltages and currents are
present. Operation may be interrupted and IED and measuring
circuitry may be damaged
Always connect the IED to protective earth regardless of the

operating conditions. Operating the IED without proper earthing may
damage both IED and measuring circuitry and may cause injuries in
case of an accident.
Do not disconnect the secondary connection of current transformer

without short-circuiting the transformers secondary winding.
Operating a current transformer with the secondary winding open will
cause a high voltage that may damage the transformer and may
cause injuries to humans.
Do not remove the screw from a powered IED or from an IED

connected to power circuitry. Potentially lethal voltages and currents
are present
Using the certified conductive bags to transport PCBs (modules).

Handling modules with a conductive wrist strap connected to
protective earth and on an antistatic surface. Electrostatic discharge
may cause damage to the module due to electronic circuits are
sensitive to this phenomenon
Do not connect live wires to the IED, internal circuitry may be

damaged
When replacing modules using a conductive wrist strap connected to

protective earth. Electrostatic discharge may damage the modules
and IED circuitry
When installing and commissioning, take care to avoid electrical

shock if accessing wiring and connection IEDs
Changing the setting value group will inevitably change the IEDs
operation. Be careful and check regulations before making the
change
Contents
Chapter 1
Introduction .............................................................................................................1
1 Overview...............................................................................................................................2
2 Features................................................................................................................................3
Chapter 2
Basic protection elements.........................................................................................9
1 Startup element .................................................................................................................. 10
1.1
Introduction .......................................................................................................... 10
1.2
Sudden-change current startup element ........................................................... 10
1.3
Differential current startup element ................................................................... 10
2 Input and output signals .................................................................................................... 11
3 Settings ............................................................................................................................... 13
4 Report ................................................................................................................................. 16
Chapter 3
Differential protection ............................................................................................ 17
1 Introduction ......................................................................................................................... 18
2 Applications ........................................................................................................................ 18
3 Protection algorithm........................................................................................................... 20
3.1
Differential and restraint current calculation ........................................................... 21
3.2
Automatic Ratio compensation............................................................................... 23
3.3
Automatic Vector group and zero sequence current compensation .......................... 27
4 Protection principle ............................................................................................................ 34
4.1
Instantaneous differential protection characteristic ................................................. 34
4.2
Treble slope percent differential protection characteristic ....................................... 35
4.3
Selective inrush stabilization schemes .................................................................... 38
4.3.1
2nd harmonic stabilization ..................................................................................... 39
4.3.2
Fuzzy recognition of inrush based on the waveform ............................................... 40
4.4
Overexcitation stabilization .................................................................................... 41
4.5
CT Failure supervision ........................................................................................... 44
4.6
CT Saturation supervision ...................................................................................... 45
4.7
Differential current supervision .............................................................................. 47
6 Settings ............................................................................................................................... 50
7 Report ................................................................................................................................. 52
8 Technical data .................................................................................................................... 53
Chapter 4
Restricted earth fault protection.............................................................................. 54
1 Introduction ......................................................................................................................... 55
2 Applications ........................................................................................................................ 55
3 Protection principle ............................................................................................................ 57
3.1
Differential and restraint current calculation ........................................................... 58
3.2
Automatic Ratio compensation............................................................................... 60
3.3
Positive sequence current blocking ......................................................................... 62
3.4
Restricted earth fault current alarm......................................................................... 63
5 Settings ............................................................................................................................... 65
6 Report .................................................................................................................................67
7 Technical data ....................................................................................................................68
Chapter 5
Overexcitation protection .......................................................................................70
1 Introduction .........................................................................................................................71
2 Protection principle ............................................................................................................71
2.1
Protection principle ................................................................................................71
2.2
Voltage channel configuration ................................................................................77
3 Input and output signals ....................................................................................................78
4 Settings ...............................................................................................................................79
5 Report .................................................................................................................................80
6 Technical data ....................................................................................................................81
Chapter 6
Overcurrent protection ...........................................................................................82
1 Introduction .........................................................................................................................83
2 Protection principle ............................................................................................................83
2.1
Protection Elements ...............................................................................................83
2.2
Inrush Restraint Feature .........................................................................................85
2.3
Direction Determination Feature ............................................................................86
2.4
CBF initiation Feature ............................................................................................89
3 Input and output signals ....................................................................................................90
4 Setting .................................................................................................................................91
5 Report .................................................................................................................................98
6 Technical data .................................................................................................................. 100
Chapter 7
Earth fault protection ........................................................................................... 101
1 Protection principle .......................................................................................................... 102
1.1
Protection elements .............................................................................................. 102
1.2
Inrush Restraint Feature ....................................................................................... 104
1.3
Direction Determination Feature .......................................................................... 105
1.4
CBF initiation Feature .......................................................................................... 107
2 Input and output signals .................................................................................................. 108
3 Setting ............................................................................................................................... 109
4 Report ............................................................................................................................... 116
5 Technical data .................................................................................................................. 117
Chapter 8
Neutral earth fault protection ................................................................................ 120
1.1
Protection Elements ............................................................................................. 121
1.2
Inrush Restraint Feature ....................................................................................... 123
1.3
Direction Determination Feature .......................................................................... 123
1.4
CBF initiation Feature .......................................................................................... 126
3 Setting ............................................................................................................................... 127
4 Report ............................................................................................................................... 133
5 Technical data .................................................................................................................. 134
Chapter 9
Thermal overload protection ................................................................................ 135
1 Introduction ....................................................................................................................... 136

4 Setting ............................................................................................................................... 139
5 Report ............................................................................................................................... 140
6 Technical data .................................................................................................................. 141
Chapter 10 Overload protection ............................................................................................. 143
3 Setting ............................................................................................................................... 146
4 Report ............................................................................................................................... 148
Chapter 11 Overvoltage protection ......................................................................................... 149
1 Introduction ....................................................................................................................... 150
2.1
Phase to phase overvoltage protection .................................................................. 150
2.2
Phase to earth overvlotage protection ................................................................... 151
3 Logic diagram................................................................................................................... 151
5 Setting ............................................................................................................................... 152
6 Report ............................................................................................................................... 154
7 Technical data .................................................................................................................. 155
Chapter 12 Circuit breaker failure protection .......................................................................... 157
1 Introduction ....................................................................................................................... 158
3 Logic diagram................................................................................................................... 161
5 Setting ............................................................................................................................... 164
6 Report ............................................................................................................................... 167
7 Technical data .................................................................................................................. 167
Chapter 13 Dead zone protection ........................................................................................... 169
1 Introduction ....................................................................................................................... 170
2.1
Function description............................................................................................. 171
3 Logic diagram................................................................................................................... 171
5 Setting ............................................................................................................................... 173
6 Report ............................................................................................................................... 174
7 Technical data .................................................................................................................. 174
Chapter 14 STUB protection .................................................................................................. 175
1 Introduction ....................................................................................................................... 176
2.1
3 Logic diagram................................................................................................................... 177
5 Setting ............................................................................................................................... 178
6 Report ............................................................................................................................... 180

7 Technical data .................................................................................................................. 181
Chapter 15 Poles discordance protection ................................................................................ 183
1 Introdcution ....................................................................................................................... 184
2.1
3 Logic diagram................................................................................................................... 185
5 Setting ............................................................................................................................... 187
6 Report ............................................................................................................................... 188
7 Technical data .................................................................................................................. 188
Chapter 16 Distance protection .............................................................................................. 189
1 Introdcution ....................................................................................................................... 190
2.1
2.2
Auxiliary startup element ..................................................................................... 191
3 Logic diagram................................................................................................................... 192
5 Setting ............................................................................................................................... 193
6 Report ............................................................................................................................... 195
7 Technical data .................................................................................................................. 196
Chapter 17 Secondary system supervision .............................................................................. 197
1 VT failure supervision function........................................................................................ 198
2 Function principle ............................................................................................................. 198
4 Setting ............................................................................................................................... 202
5 Report ............................................................................................................................... 203
6 Technical data .................................................................................................................. 204
Chapter 18 External BIs to trip BOs ....................................................................................... 205
1 Introduction ....................................................................................................................... 206
2 Function principle ............................................................................................................. 206
3 BI Trigger Record ............................................................................................................. 207
4 BI Switch SetGroup ......................................................................................................... 208
5 BI Blk Rem Access and RELAY TEST ...................................................................... 208
6 BI BI_Config1~ BI_Config2 and BI TRIGGER DR1~ 10 ......................................... 209
7 Setting ............................................................................................................................... 209
Chapter 19 Station communication......................................................................................... 211
1 Overview ........................................................................................................................... 212
1.1
Protocol ............................................................................................................... 212
1.1.1
LON communication protocol.................................................................... 212
1.1.2
IEC61850-8 communication protocol ....................................................... 212
1.1.3
IEC60870-5-103 communication protocol ............................................... 213
1.2
Communication port ............................................................................................ 213
1.2.1
Front communication port.......................................................................... 213
1.2.2
RS485 communication ports ..................................................................... 213
1.2.3
Ethernet communication ports .................................................................. 213
1.3
Technical data ...................................................................................................... 213
Front communication port .......................................................................................................... 214
RS485 communication port ........................................................................................................ 214
2 Typicalcommunication scheme....................................................................................... 216
2.1
Typical substation communication scheme ........................................................... 216
2.2
Typical time synchronizing scheme ...................................................................... 216
Chapter 20 Hardware ............................................................................................................. 219
This chapter describes the IED hardware. ............................................................................ 219
1 Introduction ....................................................................................................................... 220
1.1
IED structure ....................................................................................................... 220
1.2
IED appearance.................................................................................................... 220
1.3
IED module arrangement ..................................................................................... 221
1.4
The rear view of the protection IED ..................................................................... 221
2 Local human-machine interface ..................................................................................... 222
2.1
Human machine interface..................................................................................... 222
2.2
LCD .................................................................................................................... 223
2.3
Keypad ................................................................................................................ 223
2.4
Shortcut keys and functional keys ........................................................................ 224
2.5
LED..................................................................................................................... 225
2.6
Front communication port .................................................................................... 226
3 Analog input module ........................................................................................................ 227
3.1
Introduction ......................................................................................................... 227
3.2
Terminals of Analogue Input Module (AIM) ........................................................ 227
3.3
Technical data ...................................................................................................... 229
3.3.1
Internal current transformer....................................................................... 229
3.3.2
Internal voltage transformer ...................................................................... 229
4 Communication module................................................................................................... 230
4.1
Introduction ......................................................................................................... 230
4.2
Substaion communication port ............................................................................. 230
4.2.1
4.2.2
4.2.3
Ethernet communication ports .................................................................. 230
4.2.4
Time synchronization port ......................................................................... 231
4.3
Terminals of Communication Module .................................................................. 231
4.4
Operating reports ................................................................................................. 232
4.5
Technical data ...................................................................................................... 232
4.5.1
Front communication port ......................................................................... 232
4.5.2
RS485 communication port ....................................................................... 233
4.5.3
Ethernet communication port .................................................................... 233
4.5.4
Time synchronization ................................................................................. 234
5 Binary input module ......................................................................................................... 235
5.1
Introduction ......................................................................................................... 235
5.2
Terminals of Binary Input Module (BIM) ............................................................. 235
5.3
Technical data ...................................................................................................... 237
6 Binary output module....................................................................................................... 238
6.1
Introduction ......................................................................................................... 238
6.2
Terminals of Binary Output Module (BOM) ......................................................... 238
6.2.1
Binary Output Module A............................................................................. 238
6.2.2
Binary Output Module C ............................................................................ 241
6.3
Technical data ...................................................................................................... 243
7 Power supply module ...................................................................................................... 244
7.1
Introduction ......................................................................................................... 244
7.2
Terminals of Power Supply Module (PSM) .......................................................... 244
7.3
Technical data ...................................................................................................... 246
8 Terminal diagram ............................................................................................................. 247
8.1
Typical Terminal diagram of CSC-326 ................................................................. 247
9 Techinical data ................................................................................................................. 248
9.1
Basic data ............................................................................................................ 248
9.1.1
Frequency ................................................................................................... 248
9.1.2
Internal current transformer....................................................................... 248
9.1.3
Internal voltage transformer ...................................................................... 248
9.1.4
Auxiliary voltage ......................................................................................... 248
9.1.5
Binary inputs ............................................................................................... 249
9.1.6
Binary outputs............................................................................................. 249
9.2
Type tests ............................................................................................................. 250
9.2.1
Product safety-related Tests...................................................................... 250
9.2.2
Electromagnetic immunity tests ................................................................ 251
9.2.3
DC voltage interruption test....................................................................... 253
9.2.4
Electromagnetic emission test .................................................................. 253
9.2.5
Mechanical tests ........................................................................................ 254
9.2.6
Climatic tests .............................................................................................. 255
9.2.7
CE Certificate ............................................................................................. 255
9.3
IED design ........................................................................................................... 255
Chapter 21 Appendix ............................................................................................................. 256
1 General setting list ........................................................................................................... 257
1.1
Function setting list .............................................................................................. 257
1.2
Binary setting list ................................................................................................. 276
2 General report list ............................................................................................................ 299
3 Time inverse characteristic ............................................................................................. 307
3.1
11 kinds of IEC and ANSI inverse time characteristic curves ................................ 307
3.2
User defined characteristic ................................................................................... 307
4 CT Requirement ............................................................................................................... 308
4.1
Overview ............................................................................................................. 308
4.2
Current transformer classification......................................................................... 308
4.3
Abbreviations (according to IEC 60044-1, -6, as defined) ..................................... 309
4.4
General current transformer requirements ............................................................. 310
4.4.1
Protective checking current....................................................................... 310
4.4.2
CT class ...................................................................................................... 311
4.4.3
Accuracy class ........................................................................................... 313
4.4.4
Ratio of CT ................................................................................................. 313
4.4.5
Rated secondary current ........................................................................... 313
4.4.6
Secondary burden...................................................................................... 313
4.5
Rated equivalent secondary e.m.f requirements .................................................... 314
4.5.1
Transformer differential protection ........................................................... 314
Chapter 1 Introduction
About this chapter

This chapter gives an overview of SIFANG transformer protection IED.
Overview
It is selective, reliable and high speed IED (Intelligent Electronic Device)
for transformer protection with powerful capabilities to cover following
applications:
For large and medium two- or three-winding transformers, and autotransformer
Used in a wide range of voltage levels, up to 1000kV
For single or multi-breaker arrangement
Up to 7 three-phase sets of CTs input (special ordering)
Work as main protection unit only or full functions unit for the
complicated application
Communication with station automation system
The IED is able to provide all main protection functions and backup protection functions in one case, including differential protection, restricted
earth fault (REF), overexcitation, thermal overload, overcurrent, earth
fault protection, etc.
The integrated flexible logic make the IED suitable to be applied to (auto)transformers with all the possible vector groups, with/without earthing
connection inside the protected zone.
The wide application flexibility makes the IED an excellent choice for both
new installations and retrofitting of the existing stations.
.
Features
Protection and monitoring IED with extensive functional library, user

configuration possibility and expandable hardware design to meet with
users special requirements
Inter-lock between two CPU modules, avoiding mal-operation due to

internal severe fault of one module
Transformer differential protection (87T)
Treble slope percent differential protection
Automatic CT ratio matching
Automatic vector group and zero sequence current compensation
Settable 2nd harmonic restraint function for transformer inrush
Fuzzy waveform recognition restraint function for transformer

inrush
3rd or 5th harmonic restraint for overexcitation
CT saturation detection
CT secondarycircuit supervison
Differential current alarm
Restricted earth fault protection (87N)
Two slope percent REF protection
Automatic CT ratio matching
CT saturation recognition
REF differential current supervision
Positive sequence current blocking
A complete protection functions library, include:

3
Transformer differential protection (87T)
Restricted earth fault protection (87N)
Overcurrent protection (50, 51, 67)
Earth fault protection (50N, 51N, 67N)
Neutral earth fault protection (50G, 51G, 67G)
Thermal overload protection (49)
Overload protection (50OL)
Delta winding overload protection (50OL)
Overexcitation protection (24)
Overvoltage protection (59)
Circuit breaker failure protection (50BF)
Poles discordance protection (50PD)
Dead zone protection (50SH-Z)
Voltage transformer secondary circuit supervision (97FF)
Current transformer secondary circuit supervision
2 sets external trip commands (BIs BOs)
Self-supervision to all modules in the IED
Complete information recording: tripping reports, alarm reports,

startup reports and general operation reports. Any kinds of reports can
be stored up to 2000 and be memorized in case of power
disconnection
Up to three electric /optical Ethernet ports can be selected to

communicate with substation automation system by IEC61850 or
IEC60870-5-103 protocols
Up to two electric RS-485 ports can be selected to communicate with
substation automation system by IEC60870-5-103 protocol
Time synchronization via network(SNTP), pulse and IRIG-B mode
Configurable LEDs and output relays satisfied users requirement
Versatile human-machine interface
Multifunctional software tool CSmart/CSPC for setting, monitoring,

fault recording analysis, configuration, etc.
Protection functions
IEC 61850
Description
ANSI Code
Logical Node
Name
IEC 60617
graphical symbol
Differential protection
Transformer differential protection
87T
PDIF
Restricted earth fault protection
87N
PDIF
Current protection
3I INV >
Overcurrent protection
50,51,67
PTOC
3I >>
3I >>>
I 0INV >
Earth fault protection
50N, 51N, 67N
PEFM
I 0 >>
I 0 >>>
Neutral earth fault protection
50G, 51G, 67G
Thermal overload protection
49
PTTR
Ith
Overload protection
50OL
PTOC
3I >OL
Delta Winding Overload Protection
50OL
U/f>
Voltage protection
Overexcitation protection
24
PVPH
Overvoltage protection
59
PTOV
3U>
3U>>
Breaker protection and control function

3I> BF
Breaker failure protection
50BF
RBRF
I 0 >BF
I 2 >BF
Dead zone protection
50SH-Z
3I< PD
Poles discordance protection
50PD
RPLD
I 0 >PD
I 2 >PD
Secondary system supervision

CT secondary circuit supervision
VT secondary circuit supervision
Other functions
2 sets external trip commands (BIs
BOs)
6
Monitoring functions
Description
Auxiliary contacts of circuit breaker supervision
Self-supervision
Fault recorder
Station communication
Description
Front communication port
Isolated RS232 port
Rear communication port
0-2 isolated electrical RS485 communication ports
0-3 Ethernet electrical/optical communication ports
Time synchronization port
Communication protocols
IEC 61850 protocol
IEC 60870-5-103 protocol
Digital communication network through converter
IED software tools

Functions
Reading measuring value
Reading IED report
Setting
IED testing
Disturbance recording analysis
IED configuration
Printing
Chapter 2 Basic protection elements
About this chapter

This chapter describes basic protection elements including
startup elements, phase selectors and directional elements.
Startup element
1.1
Introduction
Startup elements are designed to detect a faulty condition in the power
system and initiate all necessary procedures for selective clearance of
the fault. The main startup element of CSC-326 is current
sudden-change startup element(abrupt current), the backup startup
element is diffrential current startup elment.
Startup element includes:
1.2
Current sudden-change startup element(abrupt current)
Differential current startup element
Sudden-change current startup element

Sudden-change current startup element is the main startup element that
can sensitively detect most of faults. Its criteria are as followings:
i > I _ startup
i (t ) 2 i (t T ) + i (t 2T )
i=
where
I_startup is a fix threshold value(IQd =0.2A when the secondary
value of CT is 1A, and IQd =1A when secondary value of CT is 5A)
1.3
Differential current startup element

I d max > I _ diff startup
=
=
I d , a, b, c
I d max Max
I _ diff startup = 0.8 I _ percent diff

where
I_diff startup is the startup threshold of differential protection,
I_Percent Diff is a setting value, and Id is the phase differential current.
10
Input and output signals

Sudden-change current
startup element
IA1
Relay Startup
IB1
IC1
IA2
IB2
IC2
IA3
IB3
IC3
IA4
IB4
IC4
IA5
IB5
IC5
Figure 1 Sudden-change current startup element
11
Differential current
startup element
IA1
Relay Startup
IB1
IC1
IA2
IB2
IC2
IA3
IB3
IC3
IA4
IB4
IC4
IA5
IB5
IC5
Figure 2 Differential current startup element

Table 1 Analog input list
Signal
Description
IA1
Phase A current input of 1st CT set
IB1
Phase B current input of 1st CT set
IC1
Phase C current input of 1st CT set
IA2
Phase A current input of 2nd CT set
IB2
Phase B current input of 2nd CT set
IC2
Phase C current input of 2nd CT set
IA3
Phase A current input of 3th CT set
IB3
Phase B current input of 3th CT set
IC3
Phase C current input of 3th CT set
IA4
IB4
IC4
IA5
IB5
IC5
12

Table 2 Binary output list
Signal
Description
Relay Startup
Relay Startup
Settings
Table 3 Settings of basic protection element
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
Connection for HV
HV Wind Conn/Y-0
D-1
winding, 0:wye
connection, 1:delta
connection
MV Wind Conn/Y-0
Connection for MV
D-1
winding, 0:wye
(Only for
three-winding
connection, 1:delta
connection
transformers)
Connection for LV
LV Wind Conn/Y-0
D-1
winding, 0:wye
connection, 1:delta
connection
Vet Grp Angle

SN
MVA
HV VT Ratio
12
11
1.000
3000.
120
1.000
9999.
2200
HV CT Pri
50.00
9999.
1200.0
HV CT Sec
1.000
5.000
1.0
HV Voltage Chan
Sel
MV Voltage Chan
Sel
Vector Group Angle( VET

GRP ANGLE)
Capacity of the
transformer
Voltage transformer(VT)
Ratio in HV side
CT Primary(PRI) current
in HV side
CT Secondary(SEC)
current in HV side
HV voltage channel
location
MV voltage channel
location
13
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
Neutral CT (NCT)
HV NCT Pri(REF)
50.00
9999.
1200.0
Primary(PRI) current in
HV side for REF
Neutral CT (NCT)
HV NCT Sec(REF)
1.000
5.000
1.0
Secondary(SEC) current
in HV side for REF
Neutral CT (NCT)
HV NCT Pri(BU)
50.00
9999.
1200.0
HV side for backup
protection
Neutral CT (NCT)
HV NCT Sec(BU)
1.000
5.000
1.0
Secondary(PRI) current in
HV side for backup
protection
MV UN
kV
MV VT Ratio
1.000
1000.
110.0
1.000
9999.
1100.0
MV CT Pri
50.00
9999.
1200.0
MV CT Sec
1.000
5.000
1.0
MV NCT Pri(REF)
50.00
9999.
1200.0
Nominal voltage (UN) in

Middle voltage (MV)side
Ratio in MV side
in MV side
CT Secondary(SEC)
current in MV side
Neutral CT (NCT)
MV side for REF
Neutral CT (NCT)
MV NCT Sec(REF)
1.000
5.000
1.0
Secondary(SEC) current
in MV side for REF
Neutral CT (NCT)
MV NCT Pri(BU)
50.00
9999.
1200.0
MV side for backup
protection
Neutral CT (NCT)
MV NCT Sec(BU)
1.000
5.000
1.0
Secondary(PRI) current in
MV side for backup
protection
LV UN
LV VT Ratio
14
kV
1.000
1000.
10.50
1.000
9999.
105.0

Low voltage (LV)side
Ratio in LV side
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
LV CT Pri
50.00
9999.
3000.0
LV CT Sec
1.000
5.000
1.0
1.000
5.000
1.0
9999
LV Sec Inside
Delta
Description
(Ir:5A/1A)
in LV side
CT Secondary(SEC)
current in LV side
CT Secondary(SEC)
current in LV inside delta
Rated primary current for
HV Rated Cur Pri
HV side (calculated
value, read only)
Rated secondary current
HV Rated Cur Sec
9999
for HV side (calculated

value, read only)
HV ratio factor for differ-
Ratio Factor KTAH
9999
ential protection (calculated value, read only)

MV ratio factor for differ-
Ratio Factor KTAM
9999

LV ratio factor for differ-
Ratio Factor KTAL
9999

HV ratio factor, with zero-sequence current
Ratio REF KTAH
9999
calculated, for REF protection (calculated value, read only)

HV ratio factor with zero-sequence current di-
Ratio REF KNH
9999
rectly measured, for REF

protection (calculated
value, read only)
MV ratio factor, with zero-sequence current
Ratio REF KTAM
9999

MV ratio factor with zero-sequence current di-
Ratio REF KNM
9999

value, read only)
15

Table 4 Binary settings of basic protection
Setting
Unit
Min.
Max.
Default
setting
Description
Autotransformer not comm
Auto Trans
on transformer
1-autotransformer ;
0- not autotransformer
Two-winding(TWO WIND )
not three -winding trans-
Two-Wind Trans
former (TRANS)
1-two-winding trans;
0-three-winding trans
CT Fail Detect
VT Failure Detection On/Off

1-On, 0-Off.
Report
Table 5 Event report list
Information
Relay startup
16
Description
The relay is initiated by startup elements
Chapter 3 Differential protection
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
differential protection function.
17
Introduction
The numerical current differential protection represents the main protection function of the IED. It provides a fast short-circuit protection for
power transformers. The protected zone is selectively limited by the CTs
at its ends. The device is able to perform this function on 2 or 3 winding
transformers in a variety of voltage levels and protected object types.
Applications
The IED provides numerical differential protection function which can be
used to protect power transformers in various configurations. For example, it is possible to use it for a two-winding transformer, three-winding
transformer as well as auto-transformer. Examples for some of applications are illustrated in the below figure.
I A.1
HV
LV
Ia.2
I B.1
Ib .2
I C .1
Ic .2
a
b
B
C
CSC-326
Figure 3 Application of differential protection on a two-winding Yd

transformer
18

I A.1
A
B
Ia.2
IB.1
Ib .2
IC .1
Ic .2
CSC-326
Figure 4 Application of differential protection on an auto

transformer
I A.1
A
B
HV
LV
Ia.2
IB.1
Ib .2
IC .1
Ic .2
a
b
CSC-326
Figure 5 Application of differential protection on a two-winding Yd

transformer with earthing transformer inside the protected zone
19

MV
Ia.2
Ib .2
b
I A.1
Ic .2
HV
I B.1
B
I C .1
LV
Ia.3
Ib .3
b
Ic .3
CSC-326
Figure 6 Application of differential protection on a three-winding

Ydd transformer
Protection algorithm
This section describes basic principle of differential protection function.
First, the case of a single phase transformer with two windings is considered. The basic principle is based on current comparison at two sides
of the protected object. Indeed, the differential protection function makes
use of the fact that a protected object carries always the same current at
its two sides in healthy operation condition. This current flows into one
side of the protected object and leaves it from the other side. A difference
in currents is an indication of a fault within this section. An example of this
condition is shown in below figure, when a fault inside the protected zone
causes a current I1prim . + I2prim . flowing in from both sides of the protected
object.
20

Protected Zone
I2-prim.
I1-prim.
CT-1
CT-2
Protected
Transformer
I2
I1
CSC-326
Figure 7 Basic principle of differential protection for two ends

(single phase)
For protected objects with three or more sides, the basic principle is expanded in that the total of all currents flowing into the protected object is
zero in healthy operation, whereas in case of a fault the total in-flowing
current is equal to the fault current.
When an external fault causes a heavy current to flow through the protected transformer, differences in the magnetic characteristics of the
current transformers CT-1 and CT-2 under saturation condition may
cause a significant difference in the secondary currents I1 + I2 connected
to IED. If the difference is greater than the pickup threshold, the differential protection function can trip even though no fault occurred in the protected zone. To prevent the protection function from such erroneous operation, a restraint (stabilizing) current is brought in. For differential protection IED, the restraint current is normally derived from the I1 and I2.
The next subsection goes on to demonstrate how the differential and restraint currents are calculated.
3.1
Differential and restraint current calculation

The differential current Idiff and the restraining current Ires are calculated
by the following equation. The following definitions apply for each phase
of the protected object.
N
Ii
I diff =
i =1
N 1
1
I
I
I i (i j )
=
(max)
j
res
2
i =1
21

Equation 1
Where Ii is the current vector of side i, corresponding to HV, MV and LV
windings; N is total current inputs of the IED. In other words, it is number
of the protected object sides;
I j (max)
is the maximum current vector
among the N current inputs of the IED, suppose it is side j;
N 1
I i (i j )
i =1
is
the sum of the other current inputs of the IED, not including side j. Idiff is
derived from the fundamental frequency current and produces the tripping effect quantity, whereas Ires counteracts this effect. To clarify the
situation, three important operating conditions with ideal and matched
measurement qualities are examined.
(a) External fault under undisturbed conditions:
I1 flows into the protected zone, I2 leaves the protected zone, i.e. is
negative according to the definition of signs, therefore I2 = I1.
Idiff = I1 + I2 = I1 I1 = 0
Ires = 0.5| I1 - (I1) | = 0.5|2I1| = |I1|
No tripping effect (Idiff = 0); the restraint (Ires) corresponds to the external fault current flowing through the protected object.
(b) Internal fault, fed with equal currents from both sides:
The following applies I2 = I1
Idiff = I1 + I2 = I1 + I1 = 2 I1
Ires = 0.5| I1 - I1| = 0
Tripping effect (Idiff) corresponds to double the fault current, and restraint
value (Ires) are equal to zero.
(c) Internal fault, fed from one side only:
The following applies when assuming I2 = 0
Idiff = I1 + I2 = I1 + 0 = I1
22

Ires = 0.5|I1 - I2| =0.5 |I1 - 0| = 0.5|I1|=0.5 I1
Tripping quantity (Idiff) and restraint quantity (Ires) are equal and correspond to the single-sided fault current.
The results show that the device is capable to properly discriminate internal and external faults by using the definitions proposed for differential
and restraint current. However, the device is still subjected to some influences that induce differential currents even during normal operation
condition. These influences should be compensated in appropriate
manners. The specific treatments designed to cope with these influences
includes automatic ratio compensation and automatic vector group
compensation which are explored in the next subsections.
3.2
Automatic Ratio compensation

Differential protection of power transformers represents some problems
in the application of current transformers. CTs should be matched to the
current rating of each transformer winding, so that normal current through
the power transformer is equal on the secondary side of the CT on different windings. However, because only standard CT ratios are available,
this matching may not be exact. As a result, the secondary currents of the
current transformers are not generally equal when a current flows
through the power transformer. The difference between the currents
flowing through CTs secondary circuit depends on the transformation ratio of the protected power transformer, as well as the rated currents of the
current transformers. Therefore, the currents should be matched in order
to become comparable. To do so, the input currents of the IED are converted in relation to the power transformer rated currents. This is
achieved by entering the characteristic values of the power transformer
(i.e. rated apparent power and rated voltages) and primary rated currents
of CTs into the IED by using user-entered settings. As a result, matching
to various power transformer and current transformer ratios is performed
purely mathematically inside the device. Therefore, no external matching
transformer is required. In this context, the rated primary current of each
side, I1N, is calculated automatically according to below equation.
23
I 1N =
SN
3U 1N
Equation 2
Where SN is rated apparent power of the transformer and U1N is rated
voltage of the corresponding side.
The rated secondary current of each side, I2N, is then calculated.
I 2N =
I1N
nCT
Equation 3
Rated secondary current of the high voltage side is then taken as the
reference current. The currents of the other sides are automatically
matched to the rated current of the high voltage side by calculation of
correction factor KCT for MV and LV side, according to below equations,
respectively:
K CT MV =
/n
I 2 N HV
I
S / 3U 1N HV nCT MV U 1N MV nCT MV
= 1N HV CT HV = N
I 2 N MV I 1N MV / nCT MV S N / 3U 1N MV nCT HV U 1N HV nCT HV
Equation 4
K CT LV =
I 2 N HV I 1N HV / nCT HV S N / 3U 1N HV nCT LV U 1N LV nCT LV

=
=
I 2 N LV
I 1N LV / nCT LV
S N / 3U 1N LV nCT HV U 1N HV nCT HV
Equation 5
Where KCT-MV is the correction factor for middle voltage side and
KCT-LV is the correction factor for Low voltage side,
I1N is the primary rated current of the transformer (I1N-HV for high voltage side, I1N-MV for middle voltage side and I1N-LV for low voltage
24

side),
I2N is the secondary rated current of the transformer (I2N-HV for high
voltage side, I2N-MV for middle voltage side, I2N-LV for low voltage
side),
nCT is CT ratio of the transformer (nCT-HV for high voltage side, nCT-MV
for middle voltage side, nCT-LV for low voltage side),
U1N is rated voltage of the transformer (U1N-HV for high voltage side,
U1N-MV for middle voltage side, U1N-LV for low voltage side).
As mentioned previously, all of the calculations are automatically performed inside the IED by its CPU. The related settings can be found
under the menu Test Menu.
Below figure shows an example of automatic ratio compensation in case
of a two-winding transformer. The primary nominal currents of the HV and
LV sides, (I1N = 402A, I2N= 1466A) are calculated from the rated apparent power of the transformer (160MVA) and the nominal voltages of
each side (230kV and 63kV). Since the nominal currents of the current
transformers deviate from the nominal currents of the power transformer
sides, the secondary current of LV side is multiplied with the factor
KCT-LV. Subsequent to this matching, equal current magnitudes are
achieved at both sides under nominal conditions of the power transformer.
SN=160MVA
U1N-HV=230kV
CTRATIO=500/1A
U1N-LV=63kV
CTRATIO=2000/1A
Figure 8 Example of automatic ratio compensation in a two-winding

transformer
I1N HV =
160 MVA
I 2 N HV =
I 1N HV 402
=
= 0.804 A
nCT
500
I 1N LV =
3 230
160 MVA
3 63
= 402 A
= 1466 A
25

1466
= 0.733 A
2000
I 2 N LV =
K CT LV =
0.804
= 1.097
0.733
Concerning three-winding power transformers, the windings may have

different power ratings. In order to compare secondary currents in an
appropriate manner, all currents are matched to the rated secondary
current of HV winding having highest power rating. This apparent power
is nominated as the rated apparent power of the transformer.
Below figure shows an example of a three-winding power transformer.
HV winding and MV winding are rated for 160MVA. The rated primary
and secondary currents of these windings are calculated as shown in
previous example. However, the LV winding has 25MVA rating (e.g. for
auxiliary supply). The rated current of this winding may result in 721A.
However, differential protection has to process comparable currents.
Therefore, the currents of LV winding should be referred to the rated
apparent power of the transformer, i.e. 160MVA. This results in a rated
current of 4619A. This is the base value for the LV winding, which should
be further multiplied by KCT-LV to be used in calculation process of differential protection.
160MVA
160MVA
U1N-HV=230kV
U1N-MV=63kV
CTRATIO=2000/1A
CTRATIO=500/1A
U1N-LV=20kV
25MVA
CTRATIO=2500/1A
Figure 9 Example of automatic ratio compensation in a

three-winding transformer
I 1N LV =
160 MVA
3 20
= 4619 A
I 2 N HV =
I 1N LV 4619
=
= 1.848 A
nCT
2500
K CT LV =
0.804
= 0.435
1.848
If a three-winding transformer with a delta LV winding (with no CB in26

stalled) is used to supply substation LVAC loads, it may be desired that
LV current should not be integrated in differential protection. In this case,
Binary setting Diff Includes LV Cur is used to select whether LV current
should be included in differential protection calculation procedure or not.
By applying setting Diff Includes LV Cur to 0, only HV and MV currents
would be included in differential protection calculation. On the contrary,
when a three-winding transformer is equipped with three CBs in its sides,
it may be desired to include LV current in differential protection. This can
be achieved by applying setting Diff Includes LV Cur to 1 to respective
Binary setting.
3.3
Automatic Vector group and zero sequence

current compensation
Transformers have different vector groups, which cause a shift of the
phase angles between the primary and the secondary side. Without adequate correction, this phase shift would cause a false differential current.
Furthermore, the conditioning of the starpoint(s) of the power transformer
has a great impact on the resulting differential current during through fault
currents.
The IED removes this problem. To do so, all CTs at the power transformer are connected Wye (polarity markings pointing away from the
transformer). User-entered settings in the relay are then used to characterize the power transformer and allow the relay to automatically perform all necessary phase angles, and zero sequence compensation. This
section describes the procedures that perform this compensation inside
the relay and produce the required calculated quantities for transformer
differential protection. The phase angle compensation as well as zero
sequence current elimination procedure is performed by programmed
coefficient matrices which are capable to simulate the difference in phase
angle of currents flowing through transformer windings. Thus, compensation is possible for the entire commonly used transformer vector
groups. This simplifies application of the IED in various configurations, if
the setting corresponding to vector Group Angle, Vet Grp Angle, is
properly entered into the device, together with the settings for connection
type of transformer windings in each side, HV WIND CONN/Y-0 D-1,
MV WIND CONN/Y-0 D-1, LV WIND CONN/Y-0 D-1, which could be
set to 1-delta or 0-wye. The basic principle of numerical vector group and
zero-sequence compensation is shown through some examples. A
through review of all possible connection groups as well as device
treatment in each case is explored in Appendix.
27

(1). Take example for Yy0 connection, including similar ones of Yy0
(separate or auto-connected windings), YNy0, Yyn0, YNyn0 (separate or
auto-connected windings) and so on. Below figure shows an example in
case of Yy0 connection group with no earthed starpoint. The figure
shows the windings (left) and the vector diagrams of symmetrical currents (right).
A
C
A
a
Yy0
Figure 10 Vector Group and zero sequence compensation for Yy0

transformer
The equations including the coefficient matrix are as follow:
IA
1 -1
1
0 1
I B =
3
I
-1 0
C
0 IA

-1 IB
1 IC

Equation 6
Ia
1 -1
1
0 1
I b =
3
I
-1 0
c
0 Ia

-1 Ib
1 Ic

Equation 7
According to these matrices, if we deduct side 1 currents IA - IB , the resulting current IA has the same direction as IA on side 2. Multiplying it
28

with 1
3 , matches the absolute value. The matrices describe the con-
version for all three phases. Using these matrices, the elimination of zero
sequence currents are warranted regardless of starpoint earth connection.
As mentioned previously, the two above equations can be used similarly
for auto-transformers, as the auto-connected windings in auto-transformers can only be connected Y(N)y(n)0. If the starpoint is
earthed, both the auto-connected HV and LV windings are affected. The
zero sequence components in current flowing through both sides of the
transformer are then coupled because of the common starpoint. These
zero sequence components are eliminated by the application of the matrices presented in the above equations.
(2). Take example for Yd1 connection, including similar ones of Yd1 and
YNd1 without earthing transformer installed at delta side. Below figure
shows an example in case of Yd1 connection group with no earthed
starpoint.
C
A
a
Yd1
Figure 11 Vector Group compensation for Yd1 transformer
29

The equation including the coefficient matrix is as follows:
IA
1 0
1
-1 1
I B =
3
I
0 -1
C
-1 IA

0 IB
1 IC

Equation 8
If an earthing transformer/reactor is installed inside the protected zone on

delta side, the IED should be informed about it by Binary setting HV
D_side Eliminate I0, MV D_side Eliminate I0 or LV D_side Eliminate
I0. The Binary setting related to delta side with earthing connection
should be set to 1-eliminate in such condition. By taking example for
Yd1 connection with earthing transformer installed at delta side, Binary
setting LV D_side Eliminate I0 is set to 1-eliminate, and thus, device
performs a zero sequence current elimination on delta side. In this case,
the equations including the coefficient matrices are as follow:
IA
1 0
1
-1 1
I B =
3
I
0 -1
C
-1 IA

0 IB
1 IC

Equation 9

I
I
a
2 1 1 a
1
. I
I
.
1
2
1
=
b

b
3

1 1 2
I c
I c

Equation 10
(3). Take example for Ydd3 connection, including similar ones of Ydd3
and YNdd3 without earthing transformer installed at delta sides. Below
figure shows an example in case of Ydd3 connection group with no
earthed starpoint in Wye side.
30

A
A
c(c)
a(a)
Ydd3
C
c'
a'
b(b)
b'
Figure 12 Vector Group compensation for Ydd3 transformer

IA
0 1
1
-1 0
I B =
3
I
1 -1
C
-1 IA

1 IB
0 IC

Equation 11
(4). Take example for Yd5 connection, including similar ones of Yd5 and
YNd5 with earthing transformer installed at delta side. Below figure
shows an example in case of Yd5 connection group with no earthed
starpoint.
31

A
C
A
c
Yd5
Figure 13 Vector Group compensation for Yd5 transformer

By setting binary setting LV D_side Eliminate I0 to 1-eliminate, the
equations including the coefficient matrices are as follow:
IA
-1 1
1
0 -1
I B =
3
I
1 0
C
0 IA

1 IB
-1 IC

Equation 12
I a
2 -1 -1 I a

I b = 1 . -1 2 -1 . I b

3 -1 -1 2 I c
I
c

Equation 13
(5). Take example for Dy1 connection, including similar ones of Dy1 and
Dyn1 without earthing transformer installed at delta side. Below figure
shows an example in case of Dy1 connection group with no earthed
starpoint.
32

A
A
a
Dy1
c
b
Figure 14 Vector Group compensation for Dy1 transformer

Ia
1 -1
1
0
1
I b =
3
I
-1 0
c
0 Ia

-1 Ib
1 Ic

Equation 14
If an earthing transformer/reactor is installed inside the protected zone on

delta side, binary setting HV D_side Eliminate I0 is set to 1-eliminate,
and thus, device performs a zero sequence current elimination on delta
side. In this case, the equations including the coefficient matrices are as
follow:

I A
2 -1 -1 I A

I B = 1 . -1 2 -1 . I B

I 3 -1 -1 2 I C
C

Equation 15
33

Ia
1 -1
1
0
1
I b =
3
I
-1 0
c
0 Ia

-1 Ib
1 Ic

Equation 16
Subsequent to application of the magnitude, vector group and zero sequence compensation, the IED use the following calculated quantities
(per phase) to discriminate between internal and external faults: fundamental component of differential and restraint currents together with instantaneous value, 2nd and 5th harmonic contents of differential current.
The following sections go on to demonstrate the fault recognition criteria
using these derived quantities.
Protection principle
4.1
Instantaneous differential protection

characteristic
An instantaneous (unrestrained) differential characteristic which entails
an overcurrent protection is provided for fast tripping on heavy internal
faults. The characteristics can be enabled or disabled by using Binary
setting Func_Inst Diff (1-on, 0-off). If setting 1-on is selected, a trip
signal is issued regardless of the magnitude of the restraining current, as
soon as the differential current rises above the threshold ID>> (setting "
I_Inst Diff "). The generated trip signal is phase selective. it means that
the device issues event reports Inst Diff Trip A, Inst Diff Trip B or Inst
Diff Trip C, when the calculated differential current in phase A, B or C
exceeds the threshold ID>> (setting " I_Inst Diff "). The purpose of this
stage of differential protection is extremely fast operation in case of high
magnitude internal fault currents. This is always the case when the short
circuit current is higher than IN/Uk%, which indicates a fault inside the
power transformer. It should be noted that the magnitude of through fault
currents are always lower than IN/Uk%, when they are supplied via
power transformer. In this equation, IN is nominal current and Uk% is
short circuit voltage of the power transformer.
The logic diagram of instantaneous differential protection is shown in
below figure.
34

Ia>I_Inst Diff
AND
INST DIFF TripA
AND
INST DIFF TripB
AND
INST DIFF TripC
Func_Inst Diff on
Ib>I_Inst Diff
Ib>I_Inst Diff
Figure 15 Tripping logic of the instantaneous differential protection

As mentioned previously and can be seen from the figure, the stage operates as an unrestrained protection function. In other words, it is not inhibited by any of harmonic stabilization features of the percent differential
element as well as the CT failure detection. This means that it can operate even when, for example, a considerable second harmonic is present
in the differential current, which is caused by current transformer saturation by a DC component in the fault current, and which could be interpreted by the inrush inhibit function as an inrush current.
This high current stage evaluates the fundamental component of the differential current as well as the instantaneous values. Instantaneous value
processing ensures fast tripping even in case the fundamental component of the current is strongly reduced by current transformer saturation.
Fast trip area is shown in Figure 16.
4.2
Treble slope percent differential protection

characteristic
The percent differential protection uses a treble-slope dual break-point
operating characteristic with magnetizing inrush and overexcitation and
CT failure detection inhibits integrated. The treble slope characteristics
can be enabled or disabled by using Binary setting Func_Percent Diff
(1-on, 0-off). If setting 1-on is selected, the stage calculates differential
and restraint current separately in each phase to obtain operating point in
each operation condition. The derived point is then mapped into Idiff-Ires
plane to examine whether it lies in trip or block area which is defined
according to predefined operating characteristic. The operation characteristic is shown in below figure.
35
IDiff
Fast trip area
I_Inst Diff
Slope 3
Trip area
Slope 2
Slope 1
block area
IRest
I_Percent Diff
I_ResPoint1 Diff
I_ResPoint2 Diff
Restraint current
Figure 16 Differential protection characteristics for transformers

In this characteristic, branch 1 represents the sensitivity threshold of the
differential protection. The setting of ID> (setting "I_Percent Diff") defines
the minimum differential current required for operation. The setting is
chosen based on the amount of differential current that might be seen
under normal operating conditions which corresponds to constant error
currents such as magnetizing currents and CT errors under no-load conditions. The setting for slope of branch 1 is applicable for restraint currents of zero to the first break-point indicated on restraint axis (setting
"I_ResPoint1 Diff"). The slope (setting Slope1_Diff) defines the ratio of
differential to restraint current above which the percent differential stage
will operate. The first break-point on restraint axis defines the end of the
slope 1 region and the start of the second branch region. This setting
should be set just above the maximum operating current level of the
transformer. This level is somewhere between the maximum
forced-cooled rated current of the transformer and the maximum emergency overload current level.
Branch 2 considers current-proportional errors which may result from
transformation errors of the main CTs or the input CTs of the relay. This
may also contain the error caused by the influence of tap changers in
power transformers with voltage control. The setting for slope of branch 2
(setting Slope2_Diff) is applicable for restraint currents of the first
break-point to the second one on restraint axis, and defines the ratio of
differential to restraint current above which the element will operate. This
slope is set to ensure sensitivity to internal faults at normal operating
current levels. The second break-point on restraint axis (setting
I_ResPoint2 Diff) defines the end of the slope 2 region and the beginning of the slope 3 region. This setting should be set to the level at which
36

any of the protection CTs is probable to saturate.
In the range of high through fault currents which may give rise to high
differential currents as a result of CT saturation, branch 3 is applicable to
provide additional stabilization. The setting for the slope of this branch
(setting Slope3_Diff) is applicable up to the point at which the branch
intersects the characteristic of instantaneous differential protection.
As a summary of the fault detection using operating characteristics of the
above figure, the calculated differential and restraint currents, IDiff and
IRest, are compared by the differential protection with the operating
characteristic according to the following formula ,
I diff S1I res + I D >

I diff S2 ( I res I R1 ) + S1 I R1 + I D >
I diff S3 ( I res I R 2 ) + S2 ( I R 2 I R1 ) + S1 I R1 + I D >
I res I R1
I R1 < I res I R 2
I R 2 < I res
Equation 17
Where S1 is the slope of the branch 1 (setting Slope1_Diff),

S2 is the slope of the branch 2, (setting Slope2_Diff),
S3 is the slope of the branch 3, (setting Slope3_Diff),
ID> is the setting for the sensitivity threshold of the differential protection,
(setting I_Percent Diff),
IR1 is the setting for the first breakpoint restraint current, (setting
I_ResPoint1 Diff),
IR2 is the setting for the second breakpoint restraint current, (setting
I_ResPoint2 Diff).
If the operating point calculated from the quantities of differential and restraint current falls into the trip area, a trip signal is issued by the percent
differential protection. The issued signals are phase selective. They can
be found in event report as Per Diff Trip A, Per Diff Trip B and Per Diff
Trip C.
This stage cannot operate when there is an inrush or overexcitation stabilization or a restraint due to CT failure detection. This is illustrated in
37

below logic diagram.
Func_Percent Diff on
1
Phase-A
I diff - A , I rest - A
ID>
A
N
D
PER DIFF Trip A
A
N
D
PER DIFF Trip B
A
N
D
PER DIFF Trip C
PER DIFF BLK A

Phase-B
I diff - B , I rest - B
ID>
PER DIFF BLK B

Phase-C
I diff -C , I rest -C
ID>
PER DIFF BLK C
Block Diff at CT_Fail on
CT FAIL
Figure 17 Tripping logic of the percent differential protection

It should be noted that when the IED is delivered, both the instantaneous
and percent differential protection functions are switched off. Setting of
0-off is applied for Binary settings Func_Inst Diff and Func_Percent
Diff. This is because the fact that these protection functions should not
be used before at least the vector group and other essential parameters
for each side is correctly set. Without these settings the equipment may
show unpredictable behavior. (E.g. tripping)
4.3
Selective inrush stabilization schemes

In power transformers, high short-time magnetizing currents may be
present during power-up (inrush currents). The inrush current can
amount to a multiple of the rated current. These currents enter the protected zone. However, it does not exit again. They thus produce differential quantities, as they seem like single-end fed fault currents. Therefore,
they should be recognized in an appropriate manner. By this way, it is
possible to prevent false operation of differential protection caused by
inrush current. This possibility is provided in the IED. Selective inrush
stabilization can be enabled or disabled by Binary setting Block Diff at
Inrush, (1-Block, 0-Not Block). If setting 1-Block is applied, the function
monitors differential current to detect an inrush condition. If the condition
38

is detected, it is possible to block differential protection phase-selectively.
Furthermore, alarm report entitled Diff 2har Blk is issued whenever inrush detection impose a blocking condition to differential protection. It
should be noted that the latter, is generated when any condition (2nd
harmonic, 3rd/5th harmonic, CT fail) leads to blocking of differential protection.
The IED provides two schemes to detect inrush conditions. The first
scheme is 2nd harmonic stabilization; the second scheme is fuzzy
recognition of inrush conditions based on the waveform. The two
schemes are convenient for user to be selected by the setting 2nd HAR
NOT WAVE (1-2nd harmonic on; 0-waveform on). The two implemented
algorithm work alternatively. As soon as an inrush condition is recognized
by each of them, a restraint condition is applied to the respective phase
evaluation of percent differential protection. Since the applied restraint by
2nd harmonic detection operates individually per phase, the protection is
fully operative even when the protected transformer is switched onto a
single-phase fault, whereas inrush currents may possibly be present in
one of the healthy phases. It is, however, possible to set the protection in
a way that when the 2nd harmonic recognition is fulfilled only in one single phase, not only the phase with the inrush current, but also the remaining phases of the percent differential protection are blocked. This is
achieved by cross-blocking the differential protection for a certain period
to avoid spurious tripping. The setting corresponds to T_2nd Harm
Block. Within this time, all three phases are blocked as soon as an inrush current is detected in any one phase. After the timer is expired, only
the phase with inrush current content is blocked.
4.3.1
2nd harmonic stabilization

By selecting 1-Block for control-word Block Diff at Inrush and selecting1-2nd harmonic for Binary setting 2nd HAR NOT WAVE, inrush
current is recognized if the second harmonic content in the differential
current exceeds a selectable threshold (setting Ratio_2nd Harm). The
ratio between the 2nd harmonic and the fundamental frequency component is decisive to discriminate inrush conditions from the other operation
conditions. The ratio is calculated by the below equation. As soon as the
measured ratio exceeds the set thresholds, a restraint is applied to the
percent differential protection in respective phase.
39

I di 2
I di
> K 2
Equation 18
Where Idiff-2 is 2nd harmonics magnitude of differential current, K2 is
the setting for 2nd harmonics ratio, Idiff- is fundamental frequency
component of differential current.
4.3.2
Fuzzy recognition of inrush based on the waveform

By selecting 1-block in control-word Block Diff at Inrush, and selecting
0-waveform on for Binary setting 2nd HAR NOT WAVE, inrush current
is detected by a fuzzy recognition method based on waveform. In this
context, differential current waveform is sampled in each phase by 2n
number of samples per cycle, each of the samples is nominated as I(k),
k=1, 2, , 2n. Then the value of X(k) is calculated according to the below
equation.
X (k ) =
I ( k ) + I ( k + n)
I ( k ) + I ( k + n)
, k = 1,2,..., n
Equation 19
The smaller values of X(k) represent that the calculated point corresponds to fault condition with higher confidence level. Alternatively, the
larger values of X(k) gives a picture that there is large content of inrush
current in the waveform. Assume that X(k) belongs to inrush Fuzzy
class with membership function of A[X(k)]. Then, the fuzzy similarity coefficient for the n calculated values of X(k) in one cycle is defined as below equation.
n
N=
A[ X (k )] / n
k =1
Equation 20
The derived value of N is used in the IED to assess the differential current corresponds to inrush condition or not. To do so, the value of N is
compared with a threshold K, and inrush content is recognized in the
40

current waveform, if N>K.
Func_Percent Di on
1
I di A 2
I di A
I di B 2
I di B
I di C 2
I di C
2nd Harm Not Wave on
> K 2
> K 2
> K 2
A
N
D
T_2nd Harm Block
A
N
D
T_2nd Harm Block
A
N
D
O
R
Block Di at Inrush on
O
R
O
R
PER DIFF BLK A
PER DIFF BLK B
PER DIFF BLK C
T_2nd Harm Block
Figure 18 logic diagram of inrush stabilization schemes by 2nd harmonic
Func_Percent Diff on
Fuzzy Inrush
Recognition in
Ph-A
2nd Harm Not Wave off
Fuzzy Inrush
Recognition in
Ph-B
Fuzzy Inrush
Recognition in
Ph-C
A
N
D
A
N
D
A
N
D
T_2nd Harm Block
Block Diff at Inrush on
PER DIFF BLK A
T_2nd Harm Block
PER DIFF BLK B
T_2nd Harm Block
PER DIFF BLK C
Figure 19 logic diagram of inrush stabilization schemes by fuzzy

recognition
4.4
Overexcitation stabilization
Apart from the second harmonic, other harmonic contents can be selected in the IED to cause stabilization of percent differential protection.
This is because the fact that unwanted differential currents caused by
41

transformer overexcitation may result in false tripping of the percent differential protection. Since steady state overexcitation is characterized by
odd harmonics, the 3rd or the 5th harmonic can be selected in the IED to
judge for overexcitation stabilization. If it is desired to impose a blocking
condition to percent differential protection by these harmonics, Binary
setting Block Diff at Overexcit should be set to 1-on. By applying this
setting, alarm report entitled Diff 3/5har Blk is issued whenever 3rd or
5th harmonic detection impose a blocking condition to differential protection. It should be noted that the latter, is generated when any condition
(2nd harmonic, 3rd/5th harmonic, CT fail) leads to blocking of differential
protection.
It is possible to use Binary setting Overexcitation 3rd NOT 5th to select
whether 3rd or 5th harmonic detection is utilized for detection of overexcitation condition (1-3rd harmonic, 0-5th harmonic). Since the third harmonic is often eliminated in delta winding of power transformers, the fifth
harmonic is more commonly used.
Similar to the 2nd harmonic stabilization, the applied restraint by 3rd or
5th harmonic detection operates individually per phase. It is, however,
possible to set the protection in a way that when the 3rd or 5th harmonic
recognition is fulfilled only in one single phase, not only the phase with
the inrush current, but also the remaining phases of the percent differential protection are blocked. This is achieved by cross-blocking the differential protection for a certain period to avoid spurious tripping. The setting corresponds to T_3/5th Harm Block. Within this time, all three
phases are blocked as soon as an 3rd or 5th harmonic is detected in any
one phase. After the timer is expired, only the phase with 3rd or 5th
harmonic content is blocked.
The detection method used for 3rd or 5th harmonic is similar to those
applied for 2nd harmonic. However, setting Ratio_3/5th Harm is decisive in this case. It means that 3rd or 5th harmonic is recognized if the
ratio between third or fifth harmonic and the fundamental frequency
component of the differential current exceeds the setting threshold. The
ratio is calculated by the below equation.
I di 3 / 5
I di
> K 3 / 5
Equation 21
Where Idiff-3/5 is 3rd/5th harmonic magnitude of differential current,
42

K3/5 is the setting for 3rd/5th harmonic ratio, Idiff- is fundamental
frequency component of differential current. Below figure show logic diagram of overexcitation stabilization.
1
Block Diff at Overexcit on
I diff Af 3
I diff Af
I diff Af 5
I diff Af
I diff B f 3
I diff B f
I diff B f 5
I diff B f
I diff C f 3
I diff C f
I diff C f 5
I diff C f
> K 3 / 5
Overexcit 3rd NOT 5th on
> K 3 / 5
> K 3 / 5
Overexcit 3rd NOT 5th off
> K 3 / 5
O
R
A
N
D
O
R
A
N
D

> K 3 / 5
A
N
D

> K 3 / 5
O
R
T_3/5th Harm Block
T_3/5th Harm Block
O
R
PER DIFF BLK A
O
R
PER DIFF BLK B
O
R
PER DIFF BLK C
T_3/5th Harm Block
Figure 20 logic diagram of overexcitation stabilization
43

4.5
CT Failure supervision
During steady-state operation, the CT failure supervision monitors the
transient behavior of the currents flowing through secondary circuit of
each phase and thus registers failures in the secondary circuit of the
current transformers for each side of the power transformer. The function
can be enabled or disabled by using setting CT Fail Detect (1-On, 0-Off).
If setting 1-On is applied, IED issues the alarm report Ph_A CT Fail,
Ph_B CT Fail, Ph_C CT Fail, whenever a CT failure is detected. It is
also possible to set differential protection to be blocked or not at CT failure detection through setting "Block Diff at CT_Fail" (1-Block, 0-Not
Block). By setting 1-Block, the percent differential protection is blocked
immediately in all phases. Blocking condition is cancelled as soon as the
device is again supplied with a normal current in the relevant faulty
phase(s). It should be noted that the setting "Block Diff at CT_Fail" is not
useful if the differential current is very high (more than 1.2 Ie, Ie is the
rated current of high voltage side). In other words, blocking conditions
takes place only for treble slope percent differential protection. This
means that the instantaneous differential protection will issue trip if a differential current greater than setting I_Inst Diff is present, even if " Block
Diff at CT_Fail " is set to 1-Block.
The criteria for CT failure detection are as follow:
The currents flowing through all three phases of CT secondary are normal at each side of the protected object. As a result, the differential current is near to zero. When one or two phase current of one side is decreased to less than a threshold (half of the memory current), at the
same time all three phase currents in other side(s) are normal, and differential current is more than a threshold (>0.3I_Percent Diff) at least in
one phase, the condition maybe an indication of CT failure in the mutative phase(s). CT failure detection logic is illustrated in below figure.
44

CT Fail Detect on
1
Max {Idiff_A, Idiff_B, Idiff_C}>0.3I_Percent Diff

Among {IHV_A, IHV_B, IHV_C} only 1
or 2 phase current decreased
Among {IMV_A, IMV_B, IMV_C}
and {ILV_A, ILV_B, ILV_C} all
currents without changing
Among {IMV_A, IMV_B, IMV_C} only 1
Among {IHV_A, IHV_B, IHV_C} and
{ILV_A, ILV_B, ILV_C} all currents
without changing
Among {ILV_A, ILV_B, ILV_C} only 1
Among {IHV_A, IHV_B, IHV_C} and
{IMV_A, IMV_B, IMV_C} all currents
without changing
A
N
D
A
N
D
A
N
D
CT Fail
O
R
A
N
D
Figure 21 CT Fail detection logic
4.6
CT Saturation supervision
When Internal and external faults occurs, it is possible that transient and
steady fault currents induce the CT saturation. CT saturation may lead to
mal-operation of differential protection when an external fault occurs. In
order to avoid mal-operation of protection in such situations, CT saturation supervision element is integrated in IED.
When transient saturation of CT occurs, the 2nd harmonic content in the
corresponding phase current is dominant. Also whenever steady saturation of CT occurs, the 3rd harmonic content in the corresponding phase
current is dominant. Both 2nd and 3rd harmonic contents of all phase
currents of each side of the protected transformer are calculated to judge
whether CT saturation occurs or not. Comprehensive harmonic ratio is
calculated by below equation.
45

I 2
I
I 3
I
> K har
Equation 22
Where:
I2 is 2nd harmonic magnitude of phase current at each side,
I3 is 3rd harmonic magnitude of phase current at each side,
Khar is the setting for comprehensive harmonic ratio, fixed in the software.
If the 2nd and 3rd harmonic contents of any phase current are more than
Khar, then CT satisfies the above formulas and it is saturated. Usually
before the CT saturation status, there is a short time period in which CT
still works in its linear characteristic. By very fast CT saturation detection
of IED, it needs only 4ms before any CT saturation happening to detect
the fault which is internal or external fault. In order to distinguish saturation caused by internal faults and external faults effectively, percent differential protection based on sample values is used. If CT saturation is
induced by external fault, differential protection will be blocked. However
if CT saturation is induced by internal fault, differential protection will
send its trip signal.
The typical saturation figure of phase A CT saturation is shown in below
figure.
Figure 22 Typical phase A current transformer Saturation waveform
46

4.7
Differential current supervision

In normal operation condition, zero differential current is assumed in
each phase. The differential current supervision monitors the differential
currents and checks its value to be less than a threshold. An alarm report
is generated as Diff Cur Alarm after 5s, if the differential current exceeds the threshold value. The alarm is an indication of miss-connection
in CT secondary windings, and therefore is released to remind user to
detect the faulty connection in secondary circuit and remove it. The function can be enabled or disabled by using setting Func_Diff Alarm (1-On,
0-Off). The fixed threshold for releasing alarm is 0.3I_Percent Diff. However, to avoid incorrect alarm indications, the threshold value is increased
to 0.1A (in 1A nominal current inputs) and to 0.3A (in A nominal current
inputs), if 0.3I_Percent Diff<0.1A. This is shown in below equations.
=
=
I _ Percent Diff , 0.1A}
if I n 1A
I D.alarm max{0.3
=
=
I _ Percent Diff , 0.3 A}
if I n 5 A
I D.alarm max{0.3
Equation 23
Logic of differential current supervision is shown in below figure.
Func_Diff Alarm on
1
Idiff_A>ID.alarm
O
R
Idiff_B>ID.alarm
A
N
D
5s
DIFF Alarm
Idiff_C>ID.alarm
Figure 23 CT Fail detection logic

DANGER: Before Differential protection is put into operation on site, polarity of current transformer must have been checked right by an energizing test of every side of the transformer or a test of simulating an external
fault of the side in primary system. Otherwise a mal-operation may occur
during an external fault.
47

Differential Protection
IA1
Diff Alarm
IB1
Diff Trip
IC1
Inst Diff A Trip
IA2
Inst Diff B Trip
IB2
Inst Diff C Trip
IC2
Per Diff A Trip
IA3
Per Diff B Trip
IB3
Per Diff C Trip
IC3
Relay Startup
IA4
IB4
IC4
IA5
IB5
IC5
Figure 24 Transformer differention protection module, with up to 15

current inputs
48

Signal
Description
IA1
Phase A current input of 1st CT set
IB1
Phase B current input of 1st CT set
IC1
Phase C current input of 1st CT set
IA2
Phase A current input of 2nd CT set
IB2
Phase B current input of 2nd CT set
IC2
Phase C current input of 2nd CT set
IA3
IB3
IC3
IA4
IB4
IC4
IA5
IB5
IC5
Signal
Description
Diff Alarm
Differential alarm
Diff Trip
Differential trip
Inst Diff A Trip
Instantaneous differential phase A Trip
Inst Diff B Trip
Instantaneous differential phase B Trip
Inst Diff C Trip
Instantaneous differential phase C Trip
Per Diff A Trip
Percent differential phase A Trip
Per Diff B Trip
Percent differential phase B Trip
Per Diff C Trip
Percent differential phase C Trip
Relay Startup
Relay Startup
49
Settings
Table 8 Instruction for Vector Group Angle setting
Binary setting
values
0
odd
odd
even
even
odd
odd
Y-Y-D-1
Y-D-D-1
Y-Y-Y-
D-D-D-
D-D-Y-
D-Y-Y-
/3/5/7/9/
/3/5/7/9/
2/4/6/8
2/4/6/8/
1/3/5/7
1/3/5/7
11
11
/10/12
10/12
/9/11
/9/11
HV Wind Conn/Y-0 D-1

MV Wind Conn/Y-0 D-1
(Only for three-winding transformers)
LV Wind Conn/Y-0 D-1
Vet Grp Angle
Remarks
Table 9 Settings of Differential protection
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
Instantaneous Differential
I_Inst Diff
0.5Ir
20Ir
20
I_Percent Diff
0.08Ir
4Ir
2.1
I_ResPoint1 Diff
0.1Ir
Ir
I_ResPoint2 Diff
0.1Ir
10Ir
Slope1_Diff
0.2
0.2
the 1st slope
Slope2_Diff
0.2
0.7
0.5
the 2nd slope
Slope3_Diff
0.25
0.95
0.7
the 3rd slope
Ratio_2nd Harm
0.05
0.80
0.15
2nd harmonic(HAR) ratio
Ratio_3/5th Harm
0.05
0.80
0.35
50
(ID>>) current setting

Percentage Differential
(ID>) current setting
The 1st breakpoint restraint current (IR1)
The 2nd breakpoint restraint current (IR2)
3rd / 5th harmonic(HAR)

ratio
Unit
Setting
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
Within the delay 2nd
harmonic block all three
T_2nd Harm Block
20
20
phases. After the delay,

then only the local phase
is blocked.
Within the delay 5th harmonic block all three
T_3/5th Harm
Block
20
20

is blocked.
Table 10 Binary settings of Differential protection
Setting
Func_Inst Diff
Func_Percent Diff
Unit
Default
Min.
Max.
setting
Block Diff at Inrush
Description
Instantaneous differential
protection ON 1-on; 0-off.
Percentage differential protection ON 1-on; 0-off.
Inrush block differential pro-
tection
1-block; 0-not block.
2nd Harm Not
2nd harmonic (HAR) inhibit
Wave
not the fuzzy recognition

0
based on the waveform(WAVE)

1-2nd harmonic on; 0waveform on
Block Diff at
Overexcit
Overexcitation block differ0
ential protection
judgement
Overexcit 3rd NOT

5th
3rd or 5th harmonic (HAR)

inhibit on
1-3rd harmonic; 0-5th harmonic.
Differential current (DIFF)
Func_Diff Alarm
Alarming on
1-on; 0-off.
51

Setting
Unit
Min.
Max.
Default
setting
Description
Block differential protection
Block Diff at
CT_Fail
when there is CT failure

Eliminate calculated 3I0
HV D_side Elimi-
nate I0
when HV side winding is

connected in Delta mode
1- eliminate; 0-not eliminate
MV D_side Elimi-
nate I0
when MV side winding is

LV D_side Elimi-
nate I0
when LV side winding is

LV current is included in
calculation of the differential
Diff Includes LV
Cur
protection.
1- Diff Includes LV Cur;
0-Diff NOT Includes LV Cur
Report
Information
Description
Per Diff Trip A

Per Diff Trip B
Treble slope percent Differential protection (ID>) trip for phase A/B/C
Per Diff Trip C

Inst Diff Trip A
Inst Diff Trip B
Inst Diff Trip C
52
Instantaneous Differential protection (ID>>) trip for phase A/B/C

Table 12 Alarm report list
Information
Description
Ph_A Ct Fail
Phase A CT failure
Ph_B Ct Fail
Phase B CT failure
Ph_C Ct Fail
Phase C CT failure
Diff Cur Alarm
Imbalance differential current alarm
Diff 2har Blk
Differential protection is blocked by 2nd harmonic.
Diff 3/5har Blk
Differential protection is blocked by 3 or 5 harmonic.
rd
th
Table 13 Operation report list
Information
Description
Func_Diff On
Differential protection is switched ON (by CW)
Func_Diff Off
Differential protection is switched OFF (by CW)
Technical data
Table 14 Differential protection technical data
Item
Range or value
Tolerance
Instantaneous differential current
0.5 Ir to 20.00 Ir
3% setting or 0.02Ir
Percentage differential current
0.08 Ir to 4.00 Ir
3% setting or 0.02Ir,
Restraint current 1
0.1 Ir to 1 Ir
Restraint current 2
0.1 Ir to 10 Ir
Slope 1
0.0 to 0.2
Slope 2
0.2 to 0.7
Slope 3
0.25 to 0.95
2nd harmonic restraint ratio
0.05 to 0.80 of fundamental
3rd / 5th harmonic restraint ratio

Reset ratio of restrained differential
Operating time of restraint differential
Operating time of instantaneous
differential
Reset time
0.05 to 0.80
approx. 0.7
30ms at 200% setting, and
I Differential >2I Restraint
R
20ms typically at 200% setting

approx. 40ms
53
Chapter 4 Restricted earth fault protection
Chapter 4 Restricted earth fault

protection
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
restricted earth fault protection function.
54
Introduction
The restricted earth fault protection detects earth faults in power transformers with earthed starpoint or in non-earthed power transformers with
a starpoint former (earthing transformer/reactor) installed inside the protected zone. A precondition for using this function is that a CT should be
installed in the starpoint connection, i.e. between the starpoint and earth.
The starpoint CT and the phase CTs define the limits of the protected
zone by restricted earth fault protection.
Applications
The IED provides two restricted differential protection functions which
can be used independently at various locations. For example, it is possible to use them for both windings of YNyn transformer which is earthed at
both starpoints. Further, one of them can be implemented to protect an
earthed transformer winding and the other for an earthing transformer/reactor. In case of auto-transformers, one of them is sufficient to protect the auto-windings. Examples for some of applications are illustrated
in the below figure.
IA.2
A
B
LV
HV
a
IB.2
b
IC .2
C
3I02 = I A.2 + IB.2 + IC .2
CSC-326
3I01
Figure 25 Application of restricted earth fault protection on an

earthed transformer winding
55

HV
LV
Ia .2
Ib .2
Ic.2
a
b
c
3I01
= Ia .2 + Ib .2 + Ic.2
3I02
CSC-326

earthing transformer winding
IA.2
A
B
LV
HV
Ia .2
IB.2
Ib .2
IC .2
Ic.2
C
3I01
3I01
3I02 = I A.2 + IB.2 + IC .2
CSC-326
= Ia .2 + Ib .2 + Ic.2
3I02
Figure 27 Application of restricted earth fault protection on both

sides of transformer
56
a
b
c

IA.2
A
B
Ia.3
IB.2
Ib .3
IC .2
Ic .3
3I01
3I02 = I A.2 + IB.2 + IC .2
CSC-326
3I03 = Ia.3 + Ib.3 + Ic.3

auto-transformer
During healthy operation condition, no starpoint current 3I01 flows
through the starpoint CT. Furthermore, the sum of the phase currents 3I 02
=IA.2 + I B.2 + IC.2 is almost zero. In case of auto-transformer, both the residual currents 3I02 =I A.2 + I B.2 + I C.2 and 3I03 =I A.3 + IB.3 + IC.3 are zero.
With an earth fault inside the protected zone, a starpoint current 3I01
flows. Moreover, depending on the earthing conditions of the power
system outside the protected zone, a further earth current may be recognized in the residual current path of the phase CTs (3I02 and 3I03 ).
Since all the currents flowing into the protected zone are defined positive,
the residual current from the system (3I02 and 3I03 ) is more or less in
phase with the starpoint current (3I01 ). With an earth fault outside the
protected zone, a starpoint current 3I01 flows into the protected zone,
together with equal residual current 3I 02 and 3I03 which flows toward
outside of the protected zone, through the phase CTs. Keeping in mind
positive direction current flow, which is toward the protected zone, the
starpoint current is in phase opposition with 3I 02 and 3 I03 .
With the described situations, it may seem to be simple to discriminate an
internal fault from an external one. However, there are some difficulties to
do so. For instance, when a strong fault without earth connection occurs
outside the protected zone, a residual current may appear in the residual
current path of the phase CTs. The residual current is caused by different
degrees of saturation in phase CTs and could simulate a fault in the
protected zone. Thus, additional measures should be taken to prevent
this current to cause false tripping. To achieve this objective, the restricted earth fault protection provides a restraint quantity.
57

3.1
Differential and restraint current calculation

The differential current Idiff0 and the restraining current Irest0 are calculated
according to below figure.
I diff 0 = 3I01 + 3I02 + 3I03
I
= max 3I01 , 3I02 , 3I03
rest 0
}
Equation 24
Idiff0 and Irest0 are compared by the restricted earth fault protection with
a dual-slope operating characteristic defined by below equation and
shown in below figure.
I diff 0 I 0 D
I diff 0 S 0 D I res 0
if I res 0 I 0 D / S 0 D
if I res 0 > I 0 D / S 0 D
Equation 25
Where I0D is the setting for sensitivity threshold of restricted earth fault
protection (setting HV 3I0_REF, MV 3I0_REF or LV 3I0_REF), and
S 0D is slope of the branch (setting HV Slope_REF, MV Slope_REF or
LV Slope_REF).
This characteristic can be enabled or disabled by using Binary setting
HV Func_REF Trip, MV Func_REF Trip or LV Func_REF Trip). If
setting 1-on is selected, a trip signal is issued by restricted earth fault
protection when the operating point lies into tripping area (see below figure) and the preset time delay is expired (setting HV T_REF Trip, MV
T_REF Trip or LV T_REF Trip).
The trip logic for restricted earth fault protection is shown in below figure.
58

I Diff0
Trip area
Slope _ REF
3 I 0 _ REF
block area
I Res0
Figure 29 Characteristic of restricted earth fault protection
Func_REF Trip on
A
N
D
Func_REF Alarm on
Idiff0>HV 3I0_REF Alarm
A
N
D
T_REF Trip
T_REF Alarm
REF Trip
REF Alarm
Figure 30 Tripping logic of the restricted earth fault protection

To clarify the proper operation during various situations, three important
operating conditions are examined.
External fault:
3I01 enters the protected zone, whereas 3I02 leaves the protected zone,
i.e. is negative according to the definition of signs, therefore 3I02 = 3I01.
Idiff0 = |3I01 + 3I02 | = |3I 01 3I02 |= 0
Ires0 = max {|3I 01 |, |3I02 |} = |3I01 |
No tripping quantity (Idiff0 = 0); the restraint quantity (Irest0) corresponds
to the external fault current flowing through the starpoint connection.
Internal fault, fed only from the starpoint:
59

In this case, 3I02 =0, thus,
Idiff0 = |3I01 + 3I02 | = |3I 01 + 0| = |3I01 |
Ires0 = max {|3I 01 |, |3I02 |} = |3I01 |
Both the tripping (Idiff0) and the restraint (Irest0) quantities correspond to
the fault current flowing through the starpoint.
Internal fault, fed from the starpoint and from the system, e.g. with equal
earth current magnitude:
Both the 3I01 and 3I02 enter the protected zone, thus having positive sign.
The condition results in 3I02 = 3I01 .
Idiff0 = |3I01 + 3I02 | = |3I 01 + 3I02 |= 2|3I 01 |
Ires0 = max {|3I 01 |, |3I02 |} = |3I01 |
Tripping quantity (Idiff0) corresponds to double the fault current flowing
through the starpoint connection, and restraint quantity (Irest0) is equal to
the fault current.
The results show that the device is capable to properly discriminate internal and external earth faults by using the definitions proposed for differential and restraint current. However, the device is still subjected to
some influences that induce differential currents even during normal operation condition. These influences should be compensated in appropriate manner. The specific treatments designed to cope with these influences includes automatic ratio compensation which is explored as follows.
3.2
Automatic Ratio compensation

Restricted earth fault protection represents some problems in the application of current transformers regarding to matching between phase and
starpoint CTs. The problem is originated from different ratio of phase and
starpoint CTs. The difference may result in a differential current in normal
operation condition. To remove this problem, the input currents of the
relay from starpoint CTs should be converted according to primary rated
currents of phase and starpoint CTs. In the IED, this objective is achieved
by taking a common reference value and converting all secondary currents of starpoint CTs into the same reference. The conversion is per-
60

formed by calculation of ratio compensation factor for starpoint CTs. The
compensation factors are then multiplied by the secondary current of
starpoint CTs to make them comparable with those current measured at
phase CTs. The conversion procedure is performed inside the device.
The ratio compensation factors are calculated as follow:
K Starpo int HV =
nStarpo int HV
nPhase HV
Equation 26
K Starpo int MV =
nStarpo int MV
nPhase MV
Equation 27
K Starpo int LV =
nStarpo int LV
nPhase LV
Equation 28
Where K Starpo int HV is the ratio compensation factor for HV starpoint CT;
K Starpo int MV is the ratio compensation for MV starpoint CT and

K Starpo int LV is the ratio compensation for LV starpoint CT;
For auto-transformer, in addition to the common winding starpoint CT, the
measured current from phase winding of MV winding should also be
converted to the common reference current. In this context, the ratio
compensation factors are calculated as follow:
K MV =
nPhase MV
nPhase HV
Equation 29
61
K Starpo int =
nStarpo int
nPhase HV
Equation 30
Where K MV is the ratio compensation factor for MV phase CT, and
K Starpo int is the ratio compensation factor for common winding starpoint
CT.
The reference current is selected as is shown in below figure.
Table 15 Reference side selection for REF functions
Type
HV REF
MV REF
LV REF
2 winding
HV CT
---
LV CT
3 winding
HV CT
MV CT
---
Auto-transformer
HV CT
---
---
3.3
Function
Positive sequence current blocking

CT2
IA.2
A
B
LV
HV
a
IB.2
b
IC .2
C
3I02 = I A.2 + IB.2 + IC .2
CSC-326
3I01
When an external fault causes a heavy current to flow through the protected transformer, differences in the magnetic characteristics of the
current transformer CT2 under saturation condition may cause a significant difference in the secondary currents I02 connected to IED. If the
difference is greater than the pickup threshold, the REF protection function can trip even though no fault occurred in the protected zone. To
prevent the protection function from such erroneous operation, a restraint
(stabilizing) ratio, zero-sequence current divides positive-sequence cur62

rent, is brought in.
I0
> 15%
I1
Where I0 is zero-sequence current, I1 is positive-sequence current.

Only when the ratio is greater than 15% can the REF protection trip.
3.4
Restricted earth fault current alarm

In normal operation condition, zero differential current is expected for restricted earth fault protection. The Restricted earth fault current supervision monitors Idiff0 and checks its value to be less than a threshold. An
alarm report is generated as HV REF 3I0 Alarm, MV REF 3I0 Alarm or
LV REF 3I0 Alarm, after the preset time of HV T_REF Alarm, MV
T_REF Alarm or LV T_REF Alarm, if the differential current exceeds
the threshold value HV 3I0_REF, MV 3I0_REF or LV 3I0_REF. The
alarm is an indication of miss-connection in phase or starpoint CT secondary windings, and therefore is released to remind user to detect the
faulty connection in secondary circuit and remove it. The function can be
enabled or disabled by using setting HV Func_REF Alarm, MV
Func_REF Alarm or LV Func_REF Alarm, (1-On, 0-Off). The setting
range of the threshold differential current to release restricted earth fault
current alarm is on [0.08-10A]. However, to avoid incorrect alarm indications, the threshold value is increased to 0.1A (in 1A nominal current inputs) and to 0.3A (in 5A nominal current inputs), if the set value is less
than 0.1A.
DANGER: Before Restricted Earth Fault protection is put into operation on
site, polarity of neutral current transformer for REF must have been
checked right by an energizing test of every side of the transformer or a
test of simulating an external fault of the side in primary system. Otherwise
a mal-operation may occur during an external earth fault.
63

Restricted Earth
Fault Protection
IA1
REF Alarm
IB1
REF Trip
IC1
Relay Startup
IA2
IB2
IC2
IREF
Figure 31 Restricted earth fault protection module

Signal
Description
IA1
Phase A current input of CT of circuit breaker 1
IB1
Phase B current input of CT of circuit breaker 1
IC1
Phase C current input of CT of circuit breaker 1
IA2
IB2
IC2
IREF
Neutral point current for REF
Signal
Description
REF Alarm
Restricted Earth Fault alarm
REF Trip
Restricted Earth Fault trip
Relay Startup
Relay Startup
64
Settings
Table 18 Settings of Restricted earth fault protection for HV side of transformer
Setting
HV 3I0_REF
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.08Ir
2Ir
0.2
0.95
0.5
60
0.03
0.08Ir
2Ir
60
0.03
Unit
HV
Slope_REF
HV T_REF
Trip
HV 3I0_REF
Alarm
HV T_REF
Alarm
Default
Min.
setting
Description
(Ir:5A/1A)
Current setting for HV Restricted Earth Fault protection
Slope setting for HV Restricted Earth Fault protection
HV Restricted Earth Fault trip
time setting
HV Restricted Earth Fault
alarm current setting
alarm time setting
Table 19 Binary settings of restricted earth fault protection for HV side of

transformer
Setting
Unit
Min.
Max.
Default
setting
Description
HV Restricted earth fault
HV Func_REF
Trip
trip-stage ON
1-on; 0-off.
HV Func_REF
Alarm
Alarm-stage ON
1-on; 0-off.
Block HV REF
at HV CT_Fail
Block HV REF when CT failure,
1-Block;0-unblock
Table 20 Settings of Restricted earth fault protection for MV side of transformer
Setting
MV 3I0_REF
MV
Slope_REF
Unit
Default
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.08Ir
2Ir
0.2
0.95
0.5
setting
Description
(Ir:5A/1A)
Current setting for MV Restricted Earth Fault protection
Slope setting for MV Restricted Earth Fault protection
65
Setting
MV T_REF
Trip
MV 3I0_REF
Alarm
MV T_REF
Alarm
Default
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
60
0.03
0.08Ir
2Ir
60
0.03
Unit
setting
Description
(Ir:5A/1A)
MV Restricted Earth Fault trip
time setting
MV Restricted Earth Fault
MV Restricted Earth Fault
alarm time setting
Table 21 Binary settings of restricted earth fault protection for MV side of

transformer
Setting
Unit
Min.
Max.
MV Func_REF
Trip
Default
setting
Description
MV Restricted earth fault
trip-stage ON 1-on; 0-off.

MV Func_REF
Alarm
Alarm-stage ON
1-on; 0-off.
Block MV REF
at MV CT_Fail
Block MV REF when CT failure,
1-Block;0-unblock
Table 22 Settings of restricted earth fault protection for LV side of transformer
Setting
LV 3I0_REF
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.08Ir
2Ir
0.2
0.95
0.5
60
0.03
0.08Ir
2Ir
60
0.03
LV Slope_REF
LV T_REF Trip
LV 3I0_REF
Alarm
LV T_REF
Alarm
66
Default
Min.
Unit
setting
Description
(Ir:5A/1A)
Current setting for LV Restricted Earth Fault protection
Slope setting for LV Restricted Earth Fault protection
LV Restricted Earth Fault trip
time setting
LV Restricted Earth Fault
alarm time setting

Table 23 Binary settings of restricted earth fault protection for LV side of
transformer
Setting
Unit
LV Func_REF
Trip
LV Func_REF
Alarm
Max.
Default
setting
0
Description
LV Restricted earth fault trip-stage
ON 1-on; 0-off.
LV Restricted earth fault
Alarm-stage ON
1-on; 0-off.
Block LV REF at
LV CT_Fail
Min.
Block LV REF when CT failure,

1-Block;0-unblock
Report
Information
Description
HV REF Trip
HV Restricted Earth fault (REF) protection trip
MV REF Trip
MV Restricted Earth fault (REF) protection trip
LV REF Trip
LV Restricted Earth fault (REF) protection trip
Information
Description
HV REF 3I0 Alarm
MV REF 3I0 Alarm
LV REF 3I0 Alarm
Information
Description
HV Func_REF On
HV REF protection is switched ON (by CW)
HV Func_REF Off
HV REF protection is switched OFF (by CW)
MV Func_REF On
MV REF protection is switched ON (by CW)
67

MV Func_REF Off
MV REF protection is switched OFF (by CW)
LV Func_REF On
LV REF protection is switched ON (by CW)
LV Func_REF Off
LV REF protection is switched OFF (by CW)
Technical data
Table 27 Restricted earth fault protection technical data
Item
Rang or Value
0.08 Ir to 2.00 Ir
Slope
0.2 to 0.95
Time delay
0.00 to 60.00s, step 0.01s
Tolerance
1% setting or +40ms, at 200%

operating setting
Reset ratio
Approx. 0.7, at tripping
Operating time
30ms, at 200% setting
Reset time
approx. 40ms
68
Chapter 5 Overexcitation protection
69
About this chapter

This chapter describes the protection principle, input and output
signals, parameter, IED report and technical data for
overexciation protection function.
70
Introduction
The overexcitation protection is used to detect impermissible overexcitation
conditions which can endanger power transformers. An increase in transformer flux beyond the rated values leads to saturation of the iron core and to
large eddy current losses which cause impermissible temperature rise in
transformer core.
2.1
The overexcitation condition may occur in power plant transformers when a
load center is disconnected from the system, and the voltage regulator does
not operate sufficiently fast to control the associated voltage rise. Similarly,
the overexcitation condition may occur as result of a decrease in frequency,
e.g. in island system. To protect the power transformer in such conditions, the
overexcitation protection function should pick up when the permissible limit of
flux is exceeded in the transformer core. To do so, the overexcitation protection function measures the voltage/frequency (U/f) ratio which is proportional
to the flux density B in transformer core, and puts it in relation to the nominal
flux density BN. The decision is then made based on the calculated ratio as is
shown in below equation.
N=
U f
B
=
BN U N f
Equation 31
Where N is the ratio of volt/hertz calculated by the device.
U and f are the measured voltage and frequency, and UN and fN are the rated
voltage and frequency (50Hz or 60Hz) of the device. While the rated frequency is fixed to 50Hz or 60Hz in software, device is informed about rated
voltage by setting Reference Voltage which corresponds to nominal
phase-neutral voltage of the protected transformer when is transferred to
71

secondary value, using the turn ratio of voltage transformer. Thus, the use of
the overexcitation protection presumes that measured voltage is connected to
the device. Calculation of voltage/hertz ratio above is performed based on the
maximum voltage of the three phase-neutral or phase-phase voltages. Binary
setting V/F Voltage (0-VPP, 1-VPN) determines whether phase-to-phase
voltage or phase-neutral voltage should be used for overexcitation protection,
by setting 0-VPP or 1-VPN, respectively.
It should be mentioned that the overexcitation protection can operate properly,
only if frequency is in range of 0.5 - 1.3 times the rated frequency and voltage
is greater than 0.7 times the rated voltage. If frequency or voltage is out of the
specified range, an alarm report U or F EXCEED is generated by the device,
after a fixed time delay of 150ms, and the overexcitation protection is blocked.
The logic is shown in below figure.
V<0.7Un
f<0.5fn or
f>1.3fn
O
R
150ms
U or F EXCEED
Figure 32 Condition for generating U or F EXCEED alarm

The overexcitation protection includes two definite characteristics (alarm and
trip) and one thermal characteristic. The latter characteristic provides an approximate replica of the temperature rise caused by overexcitation in the
protected object. The definite alarm stage can be enabled or disabled by using Binary setting Func_Overexcit Alarm Def on. Similarly, the definite trip
stage can be enabled or disabled by using Binary setting Func_Overexcit
Trip Def on. Furthermore, the thermal characteristic can be set by Binary
setting Func_Overexcit Trip Inv on. It should be mentioned that the overexcitation protection can be applied at HV, MV or LV side of the protected
transformer. However, it is not recommended to apply the function on the
transformer side with variable winding turns such as the transformer side with
an installed tap changer. To enable the protection on a given side, setting of
HV Func_Overexcit on, MV Func_Overexcit on and LV Func_Overexcit
on should be applied to corresponding Binary settings. However, these settings should be applied to 1 only on one side at the same time. If any two of
HV Func_Overexcit, MV Func_Overexcit and HV Func_Overexcit are set
to 1 at the same time, alarm report Setting Err will be given by the device.
All the three available stages of the overexcitation protection use
phase-to-phase voltage or phase-neutral voltage of the corresponding side in
their calculations, based on the setting applied at Binary setting V/F Voltage
72

(0-VPP, 1-VPN).
If the definite alarm stage is enabled in one side, and the calculated volt/hertz
ration exceeds the threshold defined by setting Func_Overexcit Alarm Def,
an alarm report Def V/F Alarm is generated by the device, after the time
delay T_Definite Alarm elapsed. The logic for the definite alarm stage of
overexcitation protection is shown in below figure when it is applied to HV
side. The logic is the same when the protection function is applied to other
sides.
HV Func_Overexcit on
Func_Overexcit Alarm Def on
A
N
D
N (U AB _ Hv , f ) DEF Alarm V / F
N (U B C _ H v , f ) D EF Alarm V / F
O
R
N (U AC _ H v , f ) D EF Alarm V / F
A
N
D
V/F Voltage(0-VPP,1-VPN) on
O
R
DEF V/F Alarm
A
N
D
N (U A _ H v , f ) D E F A larm V / F
N (U B _ H v , f ) D E F A la rm V / F
T_Definite Alarm
O
R
N (U C _ H v , f ) D E F A la rm V / F
U or F EXCEED
Figure 33 Logic of the definite alarm stage for overexcitation protection

Similarly, if the definite trip stage is enabled in one side, and the calculated
volt/hertz ration exceeds the threshold defined by setting V/F_Definite Trip,
an event report Def V/F Trip is generated by the device, subsequent to the
73

expiration of time delay T_Definite Trip. Tripping Logic of the definite trip
stage of overexcitation protection is shown in below figure.
Func_Overexcit Trip Def on
A
N
D
N (U AB _ Hv , f ) D E F T rip V / F
`
N (U BC _ Hv , f ) D E F T rip V / F
O
R
N (U AC _ Hv , f ) DEF Trip V / F
A
N
D
V/F Voltage(0-VPP,1-VPN) on
O
R
DEF V/F Trip
A
N
D
N (U A _ Hv , f ) DEF Trip V / F
N (U B _ Hv , f ) DEF Trip V / F
T_Definite Trip
O
R
N (U C _ Hv , f ) DEF Trip V / F
U or F EXCEED
Figure 34 Tripping logic of the definite trip stage for overexcitation protection
If thermal characteristic is set to 1-on in one of transformer sides, it uses the
measured voltage and frequency of the corresponding side (depending on the
setting applied at Binary setting V/F Voltage (0-VPP,1-VPN)), together with
ten points derived from the manufacturer data. The points correspond to the
desired tripping times for a given volt/hertz ratios. Intermediate values are
determined by performing linear interpolation by the device. The ratios range
from N=1.05 to N=1.50. They are entered into the device by settings
74

T1_Inverse V/F=1.05, T2_Inverse V/F=1.10, T3_Inverse V/F=1.15,
T4_Inverse V/F=1.20, T5_Inverse V/F=1.25, T6_Inverse V/F=1.30,
T7_Inverse V/F=1.35, T8_Inverse V/F=1.40, T9_Inverse V/F=1.45 and
T10_Inverse V/F=1.50. The device uses these points to form an inverse
characteristic such as those shown in below figure.
u/f
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
T10 T9 T8 T7 T6 T5 T4
T3
T2
T1
t(s)
Figure 35 Thermal overexcitation characteristic

As can be seen from the above figure, N=1.05 works as a pickup threshold for
thermal stage. The thermal replica is implemented in IED by a counter which
is incremented from 0% to 100%, as soon as the calculated voltage/hertz ratio of exceeds the pickup threshold (N=1.05). If the counter reaches to 100%
corresponding to expiration of trip time delay according to the trip characteristic, the event report Inv V/F Trip is given. The trip signal is cancelled as
soon as the calculated voltage/hertz ratio falls below the pickup threshold
(N=1.05). However, the counter is decremented to zero according to cool
down time of the transformer (the time by which the thermal replica counter
reaches from 100% to 0%). The cool down time is informed to the device by
setting T_Cool Down.
Tripping Logic of the inverse thermal trip stage of overexcitation protection is
75
A
N
D
Func_Overexcit Trip Inv on

1
u/f
N (U AB HV , f )
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
T10T9 T8 T7 T6 T5 T4 T3 T2
T1
t(s)
u/f
N (U BC HV , f )
O
R
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
T10T9 T8 T7 T6 T5 T4 T3 T2
T1
t(s)
T10T9 T8 T7 T6 T5 T4 T3 T2
T1
t(s)
u/f
N (U AC HV , f )
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
A
N
D
V/F Voltage(0VPP,1VPN) on
O
R
u/f
N (U A HV , f )
5
1.
0
4
1.
45
1.
03
1.
53
1.
02
1.2
1.5
01
1.
1
5
1.
0
1.
5
T10T9 T8 T7 T6 T5 T4 T3 T2
Inv V/F Trip
A
N
D
T1 t(s)
u/f
N (U B HV , f )
5
1.
0
4
1.
45
1.
03
1.
53
1.
02
1.2
1.5
01
1.
1
5
1.
0
1.
5
O
R
T10T9 T8 T7 T6 T5 T4 T3 T2
T1 t(s)
T10T9 T8 T7 T6 T5 T4 T3 T2
T1 t(s)
u/f
N (U C HV , f )
5
1.
0
4
1.
45
1.
03
1.
53
1.
02
1.2
1.5
01
1.
1
5
1.
0
1.
5
U or F EXCEED
Figure 36 Tripping logic of the thermal trip stage for overexcitation protection
NOTE: If it is possible for a given transformers to operate continuously under
76

the condition of N=1.05, corresponding time delay setting (T1_Inverse
V/F=1.05) should be set to 9999s. The same approach can be taken when, for
example, it is permissible for a transformer to operate continuously under the
condition N=1.10, N=1.15 and so on. It means that the thermal characteristic is
compound of 10 points at most, and it maybe contains less than 10 points. The
thermal characteristic would be disabled if all the delay time settings are set to
9999s.
2.2
Voltage channel configuration

UA/B/C voltage input channel of 1st Analog input module (hereinafter is refered as AIM) is provided with the high accurate frequency measurement
hardware circuit. In order to offer the high performance overexcitation function
for HV, MV or LV side, the applied voltage input of HV side, MV side or LV
side must be connected with the UA/B/C voltage input channel of 1st Analog
input module (AIM1).
Only one of HV overexcitation, MV overexcitation or LV overexcitation functions could be enabled for one transformer, so settings of HV Voltage Chan
Sel and MV Voltage Chan Sel under Comm Para submenu are used to
select the voltage channel.
For example of HV side; the setting HV Voltage Chan Sel can be set as 1, 2
and 3 which means voltage channels are connected to the corresponding
analog input module (see below table).
Table 28 Voltage channel selection setting
Voltage Chan Sel
Voltage input channels, connected with external

volage inputs
UA/B/C voltage input channel of AIM1, which channels can

provide the frequency measurement hardware circuit.
UA/B/C voltage input channel of AIM2
UA/B/C voltage input channel of AIM3
If Binary setting HV Func_Overexcit is set 1 and HV Voltage Chan Sel is

set 2 or 3 (not 1), alarm report Setting Err will be given by the device. If Binary setting MV Func_Overexcit is set 1 and MV Voltage Chan Sel is set 2
or 3 (not 1), alarm report Setting Err will be given by the device. If LV
77

Func_Overexcit, anyone of HV Voltage Chan Sel and MV Voltage Chan
Sel is set 1, alarm report Setting Err will be given by the device.

Overexcitation
Protection
UA
Def V/F Alarm
UB
Def V/F Trip
UC
Inv V/F Trip

Relay Startup
Figure 37 Overexcitation protection module

Signal
Description
UA
Phase A voltage input
UB
Phase B voltage input
UC
Phase C voltage input
Signal
Def V/F Alarm

Def V/F Trip
Inv V/F Trip
Relay Startup
78
Description
Overexcitation protection(V/F) alarm with
definite (DEF) time characteristic
Overexcitation protection(V/F) tripping (Trip)
with definite (DEF) time characteristic
Overexcitation protection(V/F) tripping (Trip)
with inverse(IVR) time characteristic
Relay Startup
Settings
Table 31 Settings of overexcitation protection
Setting
Reference Voltage
Max.
(Ir:5A/1A)
(Ir:5A/1A)
40
130
57.3
1.5
1.1
0.1
9999
10
1.5
1.2
0.1
9999
0.1
9999
10
0.1
9999
90
0.1
9999
80
0.1
9999
70
0.1
9999
60
0.1
9999
50
0.1
9999
45
0.1
9999
40
0.1
9999
35
0.1
9999
30
0.1
9999
25
Unit
V/F_Definite
Alarm
T_Definite Alarm
V/F_Definite
Trip
T_Definite Trip
T1_Inverse
V/F=1.05
T2_Inverse
V/F=1.10
T3_Inverse
V/F=1.15
T4_Inverse
V/F=1.20
T5_Inverse
V/F=1.25
T6_Inverse
V/F=1.30
T7_Inverse
V/F=1.35
T8_Inverse
V/F=1.40
T9_Inverse
V/F=1.45
T10_Inverse
V/F=1.50
T_Cool Down
Default
Min.
setting
Description
(Ir:5A/1A)
Nominal phase voltage in
HV side
Alarming setting of
volt/hertz
Timer setting for volt/hertz
alarming stage
Tripping setting of definite
volt/hertz stage
Timer setting for definite
volt/hertz stage
Timer setting for
volt/hertz=1.05
Timer setting for
volt/hertz=1.10
Timer setting for
volt/hertz=1.15
Timer setting for
volt/hertz=1.20
Timer setting for
volt/hertz=1.25
Timer setting for
volt/hertz=1.30
Timer setting for
volt/hertz=1.35
Timer setting for
volt/hertz=1.40
Timer setting for
volt/hertz=1.45
Timer setting for
volt/hertz=1.50
Cool down time delay for
overexcitation protection
79

Table 32 Binary settings of overexcitation protection
Setting
Unit
Default
Min.
Max.
HV Func_Overexcit
MV Func_Overexcit
LV Func_Overexcit
Func_Overexcit
Alarm Def
setting
Description
HV Overexcitation (V/F) on
1-on; 0-off.
MV Overexcitation (V/F) on
1-on; 0-off.
LV Overexcitation (V/F) on
1-on; 0-off.
Definite Overexcitation (V/F)
Alarming on
1-on; 0-off.
Func_Overexcit Trip
Def
Definite (DEF)Overexcitation
0
(V/F) on
1-on; 0-off.
Func_Overexcit Trip
Inv
Inverse (IVR)Overexcitation
0
(V/F) on
1-on; 0-off.
Overexcitation protection uses
phase-to-phase voltage (VPP)
V/F Voltage(0-VPP,1-VPN)
or phase-to-earth voltage
(VPN)
0-VPP; 1-VPN.
Report
Information
Description
Def V/F Trip
Overexcitation protection(V/F) tripping (Trip) with definite (DEF)
Inv V/F Trip
and inverse(IVR) time characteristic
80
Information
Description
Def V/F Alarm
Overexcitation alarm
V or F Exceed
Voltage or frequency is out of the permissible range
Information
Description
(25-65Hertz, >0.7 Un)
Information
Description
Func_Overexc On
Overexcitation protection is switched ON (by CW)
Func_Overexc Off
Overexcitation protection is switched OFF (by CW)
Technical data
Table 36 Overexcitation protection technical data
Item
Rang or Value
Tolerance
Reference voltage UN
40 to 130V,
3 % setting or 1 V
Inverse time characteristic

Ratio:
1.00 to 1.50
2.5% of the setting or 0.01
Time delay
Pair of Values for characteristic
of V/f
Reset time,
0.1s to 9999s
1.05 /1.10 /1.15 /1.20 /1.25 /1.30
/1.35 /1.40 /1.45 /1.50
Approx. 70ms
5% setting or 70ms
Reset ratio
0.96
5% setting or 70ms
Definite time characteristic

Time delay T
0.1s to 9999s
Reset time,
Approx. 70ms
Reset ratio
0.96
5% setting or 70ms, at 200%

operating setting
81
Chapter 6 Overcurrent protection
About this chapter

signals, parameter, IED report and technical data for overcurrent
protection function.
82
Introduction
The non-directional overcurrent elements can be applied as backup protection functions for transformer as well as power system protection in networks
with radial nature and those which are supplied from a single source. The
directional overcurrent protection can also be applied in systems where protection coordination depends on both the magnitude of the fault current and
the direction of power flow to the fault location, for instance in case of parallel transformers supplied from a single source.
2.1
Protection Elements
Each voltage side of the protected transformer is provided with three overcurrent protection elements from which two elements operate as definite
overcurrent stages and the other one operates with inverse time-current
characteristic. All the elements can operate in conjunction with the integrated
inrush restraint and directional functions.
Various stages of the elements are independent from each other and can be
combined as desired. They can be enabled or disabled in each side using
dedicated Binary settings. These Binary settings include HV Func_OC1,
HV Func_OC2 and HV Func_OC Inv, for HV side overcurrent protection,
MV Func_OC1, MV Func_OC2 and MV Func_OC Inv, for MV side
overcurrent protection, LV Func_OC1, LV Func_OC2 and LV Func_OC
Inv, for LV side overcurrent protection. For example by applying setting
1-on to HV Func_OC1, respective stage of overcurrent protection would
be enabled in HV side.
Individual pickup value for each definite stage can be defined by setting HV
I_OC1 and HV I_OC2 for HV side, MV I_OC1 and MV I_OC2 for MV
side, LV I_OC1 and LV I_OC2 for LV side. By applying these settings, each
phase current is compared separately with the setting value for each stage. If
the respective value is exceeded, a trip time delay timer is started. The condition for start of the delay timer is expressed mathematically by below equation, in which a, b and c represent three phases.
I f > I set (f = a, b, c)
Equation 32
The timer is set to count up to a user-defined time delay. The time delay can
be set for each definite stage individually through settings HV T_OC1 and
83

HV T_OC2 for HV side, MV T_OC1 and MV T_OC2 for MV side, LV
T_OC1 and LV T_OC2 for LV side. After the user-defined time delays have
been elapsed, a trip signal is issued if the inrush restraint feature is applied
and no inrush current is detected or if inrush restraint is disabled. However,
the overcurrent protection would be blocked and therefore, no tripping takes
place if the inrush restraint feature is enabled and an inrush condition exists.
Further, an alarm report is issued as HV Inrush Blk BU, MV Inrush Blk BU
or LV Inrush Blk BU indicating that a blocking condition is imposed to overcurrent element by inrush condition detection.
The pickup value for the inverse time-current stage can be defined by setting
HV I_OC Inv, MV I_OC Inv and LV I_OC Inv for HV, MV and LV sides,
respectively. Each phase current is separately compared with corresponding
setting value. If a current exceeds 1.1 times the setting value, corresponding
stage picks up. If an inverse time-current stage picks up, the tripping time is
calculated from the actual fault current flowing, using the selected tripping
curve. Maximum tripping time is limited to 100s.
The time delay of time-inverse characteristic is calculated based on the type
of the characteristic, the magnitude of the current and a time multiplier. For
the time-inverse characteristic, both ANSI and IEC based standard curves are
available and any user-defined characteristic can be defined using the following equation:
A _ OC Inv
t = K _ OC Inv
+ B _ OC Inv
P _ OC Inv
I
-1
IS
Where I is the fault current;

Is is the current setting;
xV A_OC Inv: xV(HV/MV/LV) side time factor for inverse time stage
xV B_OC Inv: xV(HV/MV/LV) time delay for inverse time stage
xV P_OC Inv: xV(HV/MV/LV) index for inverse time stage
xV K_OC Inv: xV(HV/MV/LV) time multiplier Inrush restraint feature
(For detailed time inverse characteristic, refer to Appendix Time inverse
characteristic)
As mentioned previously, selection among the curves can be carried out by
settings HV Func_OC Inv, MV Func_OC Inv and LV Func_OC Inv for HV,
MV and LV sides, respectively. Furthermore, the time multiplier K_OC Inv can
be set by user to coordinate the integrated inverse time-current characteristic
of the device with other overcurrent relays installed for power system protec84

tion. This can be performed by settings HV K_OC Inv, MV K_OC Inv and
LV K_OC Inv in case of HV, MV and LV overcurrent elements, respectively.
By applying pickup current and time multiplier settings, the device calculates
the tripping time from the measured current in each phase separately, based
on the selected inverse curve. Once the calculated time has been elapsed, a
trip signal is issued provided that no inrush current is detected or inrush restraint is disabled. If the inrush restraint feature is enabled and an inrush
condition exists, the overcurrent protection would be blocked and therefore no
tripping takes place. However, an alarm report is generated as HV Inrush Blk
BU, MV Inrush Blk BU or LV Inrush Blk BU, indicating the blocking condition which is imposed to overcurrent element by detection of inrush condition.
The trip signals and corresponding event reports are available separately for
each stage. These include HV OC1 Trip, HV OC2 Trip and HV OC Inv
Trip for HV side, MV OC1 Trip, MV OC2 Trip and MV OC Inv Trip for MV
side, LV OC1 Trip, LV OC2 Trip and LV OC Inv Trip for LV side overcurrent elements.
2.2
Inrush Restraint Feature

The transformer overcurrent protection may detect large magnetizing inrush
currents flowing when transformer is energized. The inrush current may be
several times of the nominal current, and may last from several tens of milliseconds to several seconds. Inrush current comprises second harmonic as
well as considerable fundamental component. So it may affect the overcurrent protection which operates based on the fundamental component of the
measured current. Inrush blocking unit in overcurrent function is provided for
this purpose. It is possible to apply the inrush restraint feature separately to
each definite stage and inverse time-current stage of overcurrent element by
using Binary settings HV OC1 Inrush Block, HV OC2 Inrush Block and HV
OC Inv Inrush Block on for HV side, MV OC1 Inrush Block, MV OC2 Inrush
Block and MV OC Inv Inrush Block for MV side, LV OC1 Inrush Block, LV
OC2 Inrush Block and LV OC Inv Inrush Block for LV side. By applying setting 1-on to each of the mentioned Binary settings, no trip command would
be possible by corresponding stage, if an inrush condition is detected.
Since Inrush current contains a relatively large second harmonic component
which is nearly absent during a fault current, the inrush restraint feature operates based on the evaluation of the second harmonic content which is
present in the measured current. The inrush condition is recognized if the ratio of second harmonic current to fundamental component exceeds the setting values HV Ratio_I2/I1, MV Ratio_I2/I1 or LV Ratio_I2/I1 in each
phase. The setting is applicable to both the definite stages of overcurrent
protection element as well as the inverse time-current stage for each voltage
side of the protected transformer. As soon as the measured ratio exceeds the
set threshold, a restraint is applied to those stages for which corresponding
setting is applied to make them blocked in inrush condition detection (HV
OC1 Inrush Block, HV OC2 Inrush Block and HV OC Inv Inrush Block
for HV side, MV OC1 Inrush Block, MV OC2 Inrush Block and MV OC Inv
Inrush Block for MV side, LV OC1 Inrush Block, LV OC2 Inrush Block
and LV OC Inv Inrush Block for LV side.).
85

Since the applied restraint by second harmonic detection operates individually per phase, the protection is fully operative even when the protected
transformer is switched onto a single-phase fault, whereas inrush currents
may possibly be present in one of the healthy phases. It is, however, possible
to set the protection in a way that when the second harmonic recognition is
fulfilled only in one single phase, not only the phase with the inrush current,
but also the remaining phases of the overcurrent protection are blocked. This
is achieved by cross-blocking the overcurrent protection for a certain period to
avoid spurious tripping. The setting corresponds to HV T2h_Cross_Blk, MV
T2h_Cross_Blk, LV T2h_Cross_Blk. Within this time, the overcurrent protection in all three phases is blocked as soon as an inrush current is detected
in any one phase. After the timer is expired, the overcurrent protection is
blocked only in the phase with inrush current content. To put it more simply,
cross blocking is reset if there is no more inrush in any phase, or the cross
blocking time interval is elapsed. It should be noted that inrush currents
flowing in the earth/ground path will not cross-block tripping by the phase
elements.
Furthermore, if the fundamental component of phase current exceeds the
upper limit value HV Imax_2H_UnBlk, MV Imax_2H_UnBlk or LV
Imax_2H_UnBlk, the inrush restraint will no longer be effective in respective
side, since a high-current fault is assumed in this case. The setting can be
applied for each overcurrent element in each side of the protected transformer.
2.3
Direction Determination Feature

The integrated directional function can be applied to each stage of overcurrent element via dedicated Binary settings. These Binary settings include HV
OC1 Direction, HV OC2 Direction and HV OC Inv Direction for HV side
overcurrent stages, MV OC1 Direction, MV OC2 Direction and MV OC Inv
Direction for MV side overcurrent stages and LV OC1 Direction, LV OC2
Direction and LV OC Inv Direction for LV side overcurrent stages. Furthermore, the directional orientation can be set individually for each stage of
the overcurrent elements in various sides of the protected transformer. This
can be performed by using Binary settings HV OC1 Dir To Sys, HV OC2 Dir
To Sys and HV OC Inv Dir To Sys for HV side, MV OC1 Dir To Sys, MV
OC2 Dir To Sys and MV OC Inv Dir To Sys for MV side, LV OC1 Dir To Sys,
LV OC2 Dir To Sys and LV OC Inv Dir To Sys for LV side. The possible
settings for these Binary settings comprise 0-toward transformer and
1-toward system.
Basically, the direction determination is performed by determining the phase
angle between the fault current and a reference voltage. The direction of a
phase-directional element is detected by means of a cross-polarized voltage.
It means that the fault current of the corresponding phase is used together
with the healthy phase-to-phase voltage to determine direction of fault current.
This takes effect to all three phases. Below figure shows the assignment of
the measured values for the determination of fault direction for various types
of pickups in phase overcurrent elements.
NOTE: The direction mentioned above is based on that the positive polarity is
86

at the side of the busbar and the negative polarity is at the side the transformer.
Table 37 Voltage and current measurement used for direction determination
Phase
Current
Voltage
Ia
U bc
Ib
U ca
Ic
U ab
As can be seen, the healthy voltages are used in direction determination. This
allows for a correct direction determination even if the fault voltage has collapsed entirely because of a single-phase short-line fault. With three-phase
short-line faults, memory voltage values are used to clearly determine the
direction if the measurement voltages are not sufficient. The directional element of each side uses the voltage on itself side.
In a single-phase fault, the cross-polarized voltage (reference voltage) is 90
out of phase with the fault voltage. With phase-to-phase faults, the position of
the reference voltage changes up to 30, depending on the degree of collapse
in the fault voltages. In order to satisfy different network conditions and applications, the reference voltage can be rotated by an adjustable angle. For
each side of the protected transformer, the directional angle can be set independently. The settings include HV Angle_OC, HV Angle_OC and LV
Angle_OC, for HV, MV and LV sides, respectively.
Forward
90
IA
Bisector
Angle_Range
OC
Angle_OC
0
U BC_Ref
-IA
Figure 38 Overcurrent protection directional characteristic

where:
Angle_OC: The settable characteristic angle
87

Angle_Range OC: 85
During direction decision by directional function, a VT Fail condition (a short
circuit or broken wire in the voltage transformer's secondary circuit or operation of the voltage transformer fuse) may result in false or undesired tripping
by directional overcurrent elements. In such a situation, it is possible to select
operation status of the directional overcurrent protection elements in each
side by using a number of control worlds to block the overcurrent protection
elements or keep them in operational state with no direction decision (block
direction decision). The corresponding Binary settings include Block HV OC
at HV VT_FAIL, Block MV OC at MV VT_FAIL and Block LV OC at LV
VT_FAIL, for HV, MV and LV sides, respectively. When the Binary settings
are set as 0 to select HV OC1 Direction, corresponding overcurrent protection elements will not judge direction at the local side VT failure. When they
set as 1 to select Block OC at VT Fail, no operation is possible by the
overcurrent protection elements. It is noted that the Binary settings affect all
the stages of corresponding overcurrent elements at each side. For instance,
by applying setting 0- HV OC1 Direction, all the three stages of the overcurrent element will remain operative without direction determination in case
of any fault in secondary circuit of HV side voltage transformer. On the other
hand, setting 1- Blk HV OC at HV VT_Fail makes them blocked.
The logic for Definite and Inverse time IDMTL overcurrent protection is shown
in below figure.
1
HV OC Direction on
DIR Positive
VT failure
A
N
D
Direct OK at VT FAIL
O
R
Direction Unit OK
A
N
D
HV Func_OC1 (2) on
I>HV I_OC1 (2)
A
N
D
HV T_OC1(2)
OC 1 2Trip
Direction Unit OK
Inrush BLK OC
HV Func_OC Inv on
Inverse Curve>
Direction Unit
OK
A
N
D
OC Inv Trip
Inrush BLK OC
Figure 39 Tripping logic for overcurrent protection
88

2.4
CBF initiation Feature

It is possible to set whether the overcurrent protection elements can initiate
the integrated CBF protection or not. The available choices depend on the
voltage side of the power transformer at which overcurrent protection is applied. In this context, HV side overcurrent protection element always initiates
HV side CBF function with no additional setting. However, it is possible to
select whether it can initiate MV and LV CBF protection functions via Binary
settings HV OC Initiate LV CBF and HV OC Initiate MV CBF, respectively.
MV side overcurrent protection element always initiates MV side CBF function
with no additional setting. However, it is possible to select whether it can initiate HV side CBF protection function via Binary setting MV OC Initiate HV1
CBF.
LV side overcurrent protection element always initiates LV side CBF function
with no additional setting. However, it is possible to select whether it can initiate HV side CBF protection function via Binary setting LV OC Initiate HV1
CBF.
More detail information about the initiation conditions and related Binary settings can be found as below.
89

Overcurrent
Protection
IA1
OC1 Trip
IB1
OC2 Trip
IC1
OC Inv Trip
IA2
Relay Startup
IB2
IC2
UA
UB
UC
Figure 40 Overcurrent protection module
90
Signal
Description
IA1
IB1
IC1
IA2
IB2
IC2
UA
UB
UC

Signal
Description
OC1 Trip
Overcurrent stage 1 trip
OC2 Trip
Overcurrent stage 2 trip
OC Inv Trip
Overcurrent inverse stage trip
Relay Startup
Relay Startup
Setting
Table 40 Settings of overcurrent protection for HV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
HV overcurrent (O/C) current
HV I_OC1
0.05Ir
20Ir
HV T_OC1
60
60
HV I_OC2
0.05Ir
20Ir
HV T_OC2
60
60
12
Ref to appendix 3 page 307
0.05Ir
20Ir
0.05
999
HV Curve_OC
Inv
HV I_OC Inv
HV K_OC Inv
setting for Stage 1

Time setting for HV OC,
Stage 1
HV overcurrent (O/C) current
setting for Stage 2
Stage 2
HV A_OC Inv
200
0.14
HV B_OC Inv
60
10
0.02
90
45
HV P_OC Inv
HV Angle_OC
The angle setting for voltage

ahead of current.
st
The maximum 1 -harmonic
HV
Imax_2H_UnB
lk
0.25Ir
20Ir
current setting to remove the

inrush block, in HV O/C protection
91
Setting
Unit
Default
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
setting
Description
(Ir:5A/1A)
nd
Inrush 2 harmonic ratio set-
HV Ratio_I2/I1
0.07
0.5
0.2
ting for blocking HV O/C

protection
Inrush 2nd harmonic
HV
T2h_Cross_Blk
60
20
cross-block time for HV O/C

protection
Table 41 Binary settings of overcurrent protection for HV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
st
HV Func_OC1
The 1 stage of HV OC (OC_1)

0
protection is switched ON
1-on; 0-off.
HV OC1 Direction
Direction (DIR) detection of HV

0
OC Stage 1 is switched ON
1-on; 0-off.
HV OC1 Dir To
Direction unit of HV OC Stage 1
Sys
points to system
0
0 - point to the protected transformer

1- point to system
HV OC1 Inrush
Block
Inrush 2nd harmonic detection HV

0
1-on; 0-off.
HV Func_OC2
The 2nd stage of HV OC (OC_2)

0
1-on; 0-off.
HV OC2 Direction

0
1-on; 0-off.
HV OC2 Dir To
Direction unit of HV OC Stage 2
Sys
points to system
0

1- point to system
92

HV OC2 Inrush
Block
1-on; 0-off.
HV Func_OC
The IDMTL inverse time stage of
Inv
HV OC protection is switched ON
1-on; 0-off.
HV OC Inv Di-
rection
0
OC IDMTL inverse time is
switched ON
1-on; 0-off.
HV OC Inv Dir
Direction unit of HV OC IDMTL
To Sys
inverse time points to system

0
0 - point to the protected trans-
former
1- point to system
HV OC Inv Inrush Block

0
switched ON
1-on; 0-off.
Block HV OC at
Select to block HV OC protection
HV VT_Fail
or exit direction unit, when HV VT

0
fails
0- HV Direct OK at HV VT Fail
1- Blk HV OC at HV VT Fail
HV OC Initiate
HV OC protection initiate LV side
LV CBF
CBF
0 - initiate, 1 not initiate
HV OC Initiate
HV OC protection initiate MV side
MV CBF
CBF
Table 42 Settings of overcurrent protection for MV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
MV I_OC1
0.05Ir
20Ir
MV T_OC1
60
60
MV overcurrent (O/C) current

setting for Stage 1
Time setting for MV OC,
Stage 1
93

MV overcurrent (O/C) current
MV I_OC2
0.05Ir
20Ir
MV T_OC2
60
60
12
0.05Ir
20Ir
0.05
999
MV Curve_OC
Inv
MV I_OC Inv
MV K_OC Inv
setting for Stage 2

Stage 2
MV A_OC Inv
200
0.14
MV B_OC Inv
60
10
0.02
90
45
MV P_OC Inv
MV Angle_OC

ahead of current.
The maximum 1st -harmonic
MV
Imax_2H_UnB
0.25Ir
20Ir
inrush block, in MV O/C pro-
lk
tection
nd
Inrush 2 harmonic ratio set-
MV Ratio_I2/I1
0.07
0.5
0.2
ting for blocking MV O/C

protection
nd
Inrush 2 harmonic
MV
T2h_Cross_Blk
60
20
cross-block time for MV O/C

protection
Table 43 Binary settings of overcurrent protection for MV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
st
The 1 stage of MV OC (OC_1)
MV Func_OC1
0
1-on; 0-off.
MV OC1 Direction
Direction (DIR) detection of MV OC

0
Stage 1 is switched ON
1-on; 0-off.
MV OC1 Dir To
Direction unit of MV OC Stage 1
Sys
points to system
0

1- point to system
94

nd
Inrush 2 harmonic detection MV
MV OC1 Inrush
Block
1-on; 0-off.
nd
The 2 stage of MV OC (OC_2)
MV Func_OC2
0
1-on; 0-off.
MV OC2 Direction

0
1-on; 0-off.
MV OC2 Dir To
Direction unit of MV OC Stage 2
Sys
points to system
0

1- point to system
nd
MV OC2 Inrush
Block
Inrush 2 harmonic detection MV

0
1-on; 0-off.
MV Func_OC
Inv

0
MV OC protection is switched ON
1-on; 0-off.
MV OC Inv
Direction

0
IDMTL inverse time is switched ON

1-on; 0-off.
MV OC Inv Dir
Direction unit of MV OC IDMTL in-
To Sys
verse time points to system

0

1- point to system
Inrush 2nd harmonic detection MV
MV OC Inv
Inrush Block
0
OC IDMTL inverse time is switched

ON
1-on; 0-off.
Block MV OC
at MV VT_Fail
Select to block MV OC protection or

0
exit direction unit, when MV VT fails

0- MV Direct OK at MV VT Fail
1- Blk MV OC at MV VT Fail
MV OC Initiate
HV1 CBF
MV OC protection initiate HV1 side

0
CBF
95

Table 44 Settings of overcurrent protection for LV side of transformer
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
LV overcurrent (O/C) current
LV I_OC1
0.05Ir
20Ir
LV T_OC1
60
60
LV I_OC2
0.05Ir
20Ir
LV T_OC2
60
60
12
0.05Ir
20Ir
0.05
999
LV Curve_OC
Inv
LV I_OC Inv
LV K_OC Inv
setting for Stage 1

Time setting for LV OC,
Stage 1
LV overcurrent (O/C) current
setting for Stage 2
Stage 2
LV A_OC Inv
200
0.14
LV B_OC Inv
60
LV P_OC Inv
10
0.02
LV Angle_OC
90
45

ahead of current.
LV
0.25Ir
Imax_2H_UnBlk
20Ir

inrush block, in LV O/C protection
Inrush 2nd harmonic ratio set-
LV Ratio_I2/I1
0.07
0.5
0.2
ting for blocking LV O/C protection

nd
Inrush 2 harmonic
LV
T2h_Cross_Blk
60
20
cross-block time for LV O/C

protection
Table 45 Binary settings of overcurrent protection for LV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
st
LV Func_OC1
The 1 stage of LV OC (OC_1)

0
1-on; 0-off.
96

LV OC1 Direction
Direction (DIR) detection of LV

0
1-on; 0-off.
LV OC1 Dir To
Direction unit of LV OC Stage 1
Sys
points to system
0

1- point to system
LV OC1 Inrush
Block
Inrush 2nd harmonic detection

0
LV OC Stage 1 is switched ON
1-on; 0-off.
LV Func_OC2
The 2nd stage of LV OC (OC_2)

0
1-on; 0-off.
LV OC2 Direction

0
1-on; 0-off.
LV OC2 Dir To
Direction unit of LV OC Stage 2
Sys
points to system
0

1- point to system
LV OC2 Inrush
Block

0
LV OC Stage 2 is switched ON
1-on; 0-off.
LV Func_OC
Inv

0
LV OC protection is switched ON
1-on; 0-off.
LV OC Inv Di-
rection
0

switched ON
1-on; 0-off.
LV OC Inv Dir
Direction unit of LV OC IDMTL
To Sys

0

1- point to system
97

Inrush 2nd harmonic detection LV
LV OC Inv Inrush Block

0

switched ON
1-on; 0-off.
Block LV OC at
Select to block LV OC protection
LV VT_Fail
or exit direction unit, when LV VT

0
fails
0- LV Direct OK at LV VT Fail
1- Blk LV OC at LV VT Fail
LV OC Initiate
HV1 CBF
LV OC protection initiate HV1

0
side CBF
Report
Information
Description
HV OC Inv Trip
Inverse time stage of HV overcurrent protection trip
HV OC1 Trip
HV overcurrent stage 1 trip
HV OC2 Trip
MV OC Inv Trip
Inverse time stage of MV overcurrent protection trip
MV OC1 Trip
MV overcurrent stage 1 trip
MV OC2 Trip
LV OC Inv Trip
Inverse time stage of LV overcurrent protection trip
LV OC1 Trip
LV overcurrent stage 1 trip
LV OC2 Trip
98
Information
Description
HV Func_OC On
Overcurrent protection of HV side is switched ON (by CW)
HV Func_OC Off
Overcurrent protection of HV side is switched OFF (by CW)
MV Func_OC On
Overcurrent protection of MV side is switched ON (by CW)
MV Func_OC Off
Overcurrent protection of MV side is switched OFF (by CW)
Information
Description
LV Func_OC On
Overcurrent protection of LV side is switched ON (by CW)
LV Func_OC Off
Overcurrent protection of LV side is switched OFF (by CW)
99
Technical data
Table 48 Overcurrent protection technical data
Item
Rang or Value
Tolerance
Definite time characteristics

Current
0.08 Ir to 20.00 Ir
Time delay
0.00 to 60.00s, step 0.01s

operating setting
Reset time
approx. 40ms
Reset ratio
Approx. 0.95 at I/In 0.5

Inverse time characteristics
Current
0.08 Ir to 20.00 Ir
IEC standard
Normal inverse;
5% setting + 40ms, at 2
Very inverse;
<I/I SETTING < 20, in accordance
Extremely inverse;
with IEC60255-151
Long inverse
ANSI
Inverse;
Short inverse;
<I/ISETTING < 20, in accord-
Long inverse;
ance with ANSI/IEEE C37.112,
Moderately inverse;
Very inverse;
Extremely inverse;
Definite inverse
user-defined characteristic
<I/I SETTING < 20, in accordance
T=
with IEC60255-151
Time factor of inverse time, A
0.005 to 200.0s, step 0.001s
Delay of inverse time, B
0.000 to 60.00s, step 0.01s
Index of inverse time, P
0.005 to 10.00, step 0.005
set time Multiplier for step n: k
0.05 to 999.0, step 0.01
Minimum operating time
20ms
Maximum operating time
100s
Reset mode
instantaneous
Reset time
approx. 40ms,
Directional element
Operating area range
170
Characteristic angle
0 to 90, step 1
100
3, at phase to phase voltage >1V
Chapter 7 Earth fault protection
About this chapter

signals, parameter, IED report and technical data for earth fault
101
1.1
Protection elements
Each voltage side of the protected transformer is provided with three earth
fault protection elements from which two elements operate as definite earth
fault stages and the other one operates with inverse time-current characteristic. All the elements can operate in conjunction with the integrated inrush restraint and directional functions.
Various stages of each element are independent from each other and can be
dedicated Binary settings. These Binary settings include HV Func_EF1, HV
Func_EF2 and HV Func_EF Inv on, for HV side earth fault protection, MV
Func_EF1, MV Func_EF2 and MV Func_EF Inv, for MV side earth fault
protection, LV Func_EF1, LV Func_EF2 and LV Func_EF Inv, for LV side
earth fault protection. For example by applying setting 1-on to HV
Func_EF1, respective stage of earth fault protection would be enabled in HV
side.
3I0_EF1 and HV 3I0_EF2 for HV side, MV 3I0_EF1 and MV 3I0_EF2 for
MV side, LV 3I0_EF1 and LV 3I0_EF2 for LV side. By applying these settings, each earth current (quantity 3I0) calculated from the three phase currents is compared separately with the setting value for each stage. If the respective value is exceeded, a trip time delay timer is started. The condition for
start of the delay timer is expressed mathematically:
3I 0 > 3I 0 set
Equation 33
be set for each definite stage individually through settings HV T_EF1 and
HV T_EF2 for HV side, MV T_EF1 and MV T_EF2 for MV side, LV
T_EF1 and LV T_EF2 for LV side. After the user-defined time delay has
been elapsed, a trip signal is issued if the inrush restraint feature is applied
and no inrush current is detected or inrush restraint is disabled. The earth
fault protection would be blocked and therefore, no tripping takes place if the
inrush restraint feature is enabled and an inrush condition exists. However, an
alarm report is issued nominated as HV EF1 Inrush Block, HV EF2 Inrush
Block or HV EF Inv Inrush Block, indicating the blocking condition of earth
fault element caused by inrush condition detection.
Pickup value for the inverse time-current stage can be set by setting HV
3I0_EF Inv, MV 3I0_EF Inv and LV 3I0_EF Inv for HV, MV and LV sides,
respectively. Each earth current (quantity 3I0) calculated from the three phase
102

currents is separately compared with corresponding setting value. If a current
exceeds 1.1 times the setting value, corresponding stage picks up. When an
inverse time-current stage picks up, the tripping time is calculated from the
calculated quantity 3I0, using the selected tripping curve. Maximum tripping
time is limited to 100s.
The time delay of time-inverse characteristic is calculated based on the type
of the characteristic, the magnitude of the current and a time multiplier. For
the time-inverse characteristic, both ANSI and IEC based standard curves are
available and any user-defined characteristic can be defined using the following equation:
A
_
EF
Inv
t = K _ EF Inv
B
EF
Inv
+
_
HP _ EF Inv
I
-1
IS
Equation 34
Where I is the calculated earth fault current;
xV A_EF Inv: xV(HV/MV/LV) side time factor for inverse time stage
xV B_EF Inv: xV(HV/MV/LV) time delay for inverse time stage
xV P_EF Inv: xV(HV/MV/LV) index for inverse time stage
xV K_EF Inv: xV(HV/MV/LV) time multiplier Inrush restraint feature
By applying the desired setting values, the device calculates the tripping time
from the zero sequence current. Once the calculated time elapsed, report EF
Inv Trip will be issued.
As mentioned previously, selection among the curves can be carried out by
settings HV Curve_EF Inv, MV Curve_EF Inv and LV Curve_EF Inv for
HV, MV and LV sides, respectively. Furthermore, the time multiplier K_EF Inv
can be applied by user to coordinate the integrated inverse time-current
characteristic of the device with other earth fault relays installed for power
system protection. This can be performed by settings HV K_EF Inv, MV
K_EF Inv and LV K_EF Inv in case of HV, MV and LV earth fault elements.
By applying pickup current and time multiplier settings, the device determines
the tripping time from the calculated earth current, based on the selected inverse curve. Once the calculated time has been elapsed, a trip signal is issued provided that no inrush current is detected or inrush restraint is disabled.
If the inrush restraint feature is enabled and an inrush condition exists the
earth fault protection would be blocked and therefore no tripping takes place.
103

However, an alarm report is issued designated as HV Inrush Blk BU, MV
Inrush Blk BU or LV Inrush Blk BU, indicating the blocking condition of
overcurrent element caused by inrush condition detection.
each stage. They include HV EF_1 Trip, HV EF_2 Trip and HV IDMTL EF
Trip for HV side, MV EF_1 Trip, MV EF_2 Trip and MV IDMTL EF Trip for
MV side, LV EF_1 Trip, LV EF_1 Trip and LV IDMTL EF Trip for LV side
earth fault elements.
1.2

The transformer earth fault protection may detect large magnetizing inrush
currents flowing when transformer is energized. The inrush current may be
several times of the nominal current, and may last from several tens of milliseconds to several seconds.
Inrush current comprises second harmonic as well as a considerable fundamental component. So, it may affect earth fault protection which operates
based on the fundamental component of the measured current. Inrush
blocking unit in earth fault function is provided for this purpose.
It is possible to apply the inrush restraint feature separately to each definite
stage and inverse time-current stage of earth fault element by using Binary
settings HV EF1 Inrush Block, HV EF2 Inrush Block and HV EF Inv Inrush
Block for HV side, MV EF1 Inrush Block, MV EF2 Inrush Block and MV
EF Inv Inrush Block for MV side, LV EF1 Inrush Block, LV EF2 Inrush
Block and LV EF Inv Inrush Block on for LV side. By applying setting 1-on
to each of the mentioned Binary settings, no trip command would be possible
by corresponding stage, if an inrush condition is detected.
Since the inrush current contains a relatively large second harmonic component which is nearly absent during a fault current, the inrush restraint operates based on the evaluation of the second harmonic content which is present
in the phase currents. The inrush condition is recognized if the ratio of second
harmonic current to the fundamental component exceeds the setting value
HV Ratio_I2/I1_EF, MV Ratio_I2/I1_EF or LV Ratio_I2/I1_EF in each
phase current. The setting is applicable to both the definite stages of earth
fault protection element as well as the inverse time-current stage. As soon as
the measured ratio exceeds the set threshold, a restraint is applied to those
stages for which corresponding setting is applied to make them blocked in
inrush condition detection (HV EF1 Inrush Block, HV EF2 Inrush Block and
HV EF Inv Inrush Block on for HV side, MV EF1 Inrush Block, MV EF2
Inrush Block and MV EF Inv Inrush Block for MV side, LV EF_1 Inrush
Detect ON, LV EF1 Inrush Block, LV EF2 Inrush Block and LV EF Inv
Inrush Block for LV side).
Furthermore, if the fundamental component of each phase current exceeds
the upper limit value HV Ratio_I2/I1, MV Ratio_I2/I1 or LV Ratio_I2/I1,
the inrush restraint will no longer effective in respective side, since a
high-current fault is assumed in this case.
104

1.3

The integrated directional function can be applied to each stage of earth fault
elements via Binary settings. The Binary settings include HV EF1 Direction,
HV EF2 Direction and HV EF Inv Direction on for HV side earth fault
stages, MV EF1 Direction, MV EF2 Direction and MV EF Inv Direction for
MV side earth fault stages and LV EF1 Direction, LV EF2 Direction and LV
EF Inv Direction for LV side earth fault stages.
Furthermore, the directional orientation can be set individually for each stage
of earth fault elements in various sides of the protected transformer. This can
be performed by Binary settings HV EF1 Dir To Sys, HV EF2 Dir To Sys
and HV EF Inv Dir To Sys for HV side, MV EF1 Dir To Sys, MV EF2 Dir To
Sys and MV EF Inv Dir To Sys for MV side, LV EF1 Dir To Sys, LV EF2
Dir To Sys and LV EF Inv Dir To Sys for LV side. The possible settings for
these Binary setting comprise 0-toward transformer and 1-toward system.
Basically, the direction determination is performed by comparing the zero
sequence system quantities. In the current path, 3I0 current is calculated from
the sum of the three phase currents. In the voltage path, the device calculates
the zero sequence voltage 3V0 from the sum of the three phase voltages.
Contrary to the directional phase elements, which work with the un-faulted
voltage as reference voltage, the fault voltage itself is the reference voltage
for the directional ground element. Depending on the connection of the voltage transformer, this is the voltage 3V0 or VN. The directional element at
each side operates with the residual/ neutral voltage of the same side.
In order to satisfy different network conditions and applications, the reference
voltage can be rotated by an adjustable angle. For each side of the protected
transformer, the directional angle can be set independently. The settings include HV Angle_EF, MV Angle_EF and LV Angle_EF, for HV, MV and LV
sides, respectively. It should be noted that the settings affect all the directional
stages of the corresponding earth fault element.
NOTE: The direction mentioned above is based on that the positive polarities of
three phases CT. The voltage used by directional element is calculated by
three phase voltage. Details are shown as below.
Below figure shows an example of direction determination for a fault in phase

A. As can be seen from the figure, fault current 3I0 lags from fault voltage Va.
Accordingly, fault current -3I0 lags residual sequence voltage 3U0 by this
angle. The reference voltage 3U0 is rotated to be as close as possible to -3I0
current. Furthermore, the forward area is depicted in the figure.
105
3I 0
90
0
3U 0_Ref
Angle_EF
Angle_Range
EF
Forward
-3 I 0
Bisector
Figure 41 Characteristic of zero sequence directional element

where:
Angle_EF: The settable characteristic angle
Angle_Range EF: 80
circuit or broken wire in the voltage transformer's secondary system or an
operation of the voltage transformer fuse) may result in false or undesired
tripping by directional earth fault elements. In such a situation, it is possible to
select operation status of the directional earth fault protection elements in
each side by using a number of Binary settings to block the earth fault protection elements or keep them in operational state with no direction decision
(block direction decision). The Binary settings are designated as Block HV
EF at HV VT_Fail, Block MV EF at HV VT_Fail and Block LV EF at HV
VT_Fail, for HV, MV and LV sides, respectively. When the Binary settings are
set as 0 to select Direct OK at VT Fail, corresponding earth fault protection
elements will not judge direction at the local side VT failure. When they set as
1 to select Block EF at VT Fail, no operation is possible by the earth fault
protection elements. It is noted that the Binary settings affect all the stages of
corresponding earth fault elements at each side. For instance, by applying
setting Block HV EF at HV VT_Fail off, all the three stages of the earth fault
element will remain operative without direction determination in case of any
fault in secondary circuit of HV side voltage transformer. On the other hand,
setting Block HV EF at HV VT_Fail on makes them blocked.
It is possible to block earth fault protection elements in each side of the protected transformer if a CT fail is detected in the same side. This can be performed by Binary settings Block HV EF at HV CT_Fail, Blk MV EF at MV
CT_FAIL and Blk LV EF at LV CT FAIL in each voltage side. If setting 1 is
applied to these Binary settings, any CT fail detection in a given side of the
power transformer would bring blocking condition to all stages of the earth
106

fault element which is applied in the same side.
The logic for definite and inverse time IDMTL earth fault protection is shown in
below figure.
1
HV EF Direction on
DIR Positive
VT failure
A
N
D
O
R
E/F Direction Unit OK
A
N
D
HV Func_EF1 (2) on
3I0>HV 3I0_EF1(2)
A
N
D
HV T_EF1(2)
E/F Trip
Direction Unit OK
Inrush BLK EF
HV Func_EF Inv on
Inverse Curve>
E/F Direction OK
A
N
D
IDMTL E/F Trip
Inrush BLK EF
Figure 42 Tripping logic for earth fault protection
1.4

It is possible to set whether the earth fault protection elements can initiate the
integrated CBF protection or not. The available choices depend on the voltage side of the power transformer at which earth fault protection is applied. In
this context, HV side earth fault protection element always initiates HV side
CBF function with no additional setting. However, it is possible to select
whether it can initiate MV and LV CBF protection functions via Binary settings
HV EF Initiate LV CBF and HV EF Initiate MV CBF on, respectively.
MV side earth fault protection element always initiates MV side CBF function
with no additional setting. However, it is possible to select whether it can initiate HV side CBF protection function via Binary setting MV EF Initiate HV1
CBF on.
More detail information about the initiation conditions and related Binary settings can be found in below table.
107

Earth Fault
Protection
IA1
EF1 Trip
IB1
EF2 Trip
IC1
EF Inv Trip
IA2
Relay Startup
IB2
IC2
UA
UB
UC
Figure 43 Earth fault protection module

Signal
Description
IA1
IB1
IC1
IA2
IB2
IC2
UA
Phase A voltage input of VT of related winding of transformer
UB
Phase B voltage input of VT of related winding of transformer
UC
Phase C voltage input of VT of related winding of transformer
Signal
Description
EF1 Trip
Earth Fault stage 1 trip
EF2 Trip
Earth Fault stage 2 trip
EF Inv Trip
Earth Fault inverse stage trip
108
Signal
Description
Relay Startup
Relay Startup
Setting
Table 51 Settings of earth fault protection for HV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1
(Ir:5A/1
A)
A)
Default
setting
(Ir:5A/1
Description
A)
HV earth fault (E/F) protection
HV 3I0_EF1
0.05Ir
20Ir
HV T_EF1
60
60
HV 3I0_EF2
0.05Ir
20Ir
HV T_EF2
60
60
Time setting for HV E/F, Stage 2
12
0.05Ir
20Ir
1.2
0.05
999
200
0.14
60
10
0.02
90
45
current setting for Stage 1

Time setting for HV E/F, Stage 1
HV earth fault (E/F) current setting for Stage 2
HV
Curve_EF
Inv
HV 3I0_EF
Inv
HV K_EF
Inv
HV A_EF
Inv
HV B_EF
Inv
HV P_EF
Inv
HV Angle_EF
0.25Ir
20Ir
nBlk_EF
HV Ratio_I2/I1_EF
ahead of current.
st
The maximum 1 -harmonic cur-
HV
Imax_2H_U
rent setting to remove the inrush

block, in HV EF protection
st
0.07
0.5
0.2

109

Table 52 Binary settings of earth fault protection for HV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
st
The 1 stage of HV earth fault
HV Func_EF1
(EF_1) protection is switched ON

1-on; 0-off.
Direction (DIR) detection of HV EF
HV EF1 Direction
1-on; 0-off.
Direction unit of HV EF Stage 1
HV EF1 Dir To
Sys
points to system
0

1- point to system
HV EF1 Inrush
Block
nd
Inrush 2 harmonic detection HV
EF Stage 1 is switched ON
1-on; 0-off.
nd
The 2 stage of HV earth fault
HV Func_EF2

1-on; 0-off.
HV EF2 Direction
1-on; 0-off.
Direction unit of HV EF Stage 2
HV EF2 Dir To
Sys
points to system
0

1- point to system
HV EF2 Inrush
Block
nd
Inrush 2 harmonic detection HV
1-on; 0-off.
HV Func_EF Inv
HV EF protection is switched ON
1-on; 0-off.
HV EF Inv Direction
IDMTL inverse time is switched

ON
1-on; 0-off.
110

Direction unit of HV EF IDMTL
HV EF Inv Dir To
Sys

1- point to system
HV EF Inv Inrush
Block
EF IDMTL inverse time is

switched ON
1-on; 0-off.
Select to block HV EF protection
or exit direction unit, when HV VT
Block HV EF at
HV VT_Fail
fails
0 - HV Direct OK at HV VT Fail
1 - Blk HV EF at HV VT Fail
Block HV EF when there is HV CT
Block HV EF at
HV CT_Fail
failure
1-Block;
0-NOT block
HV EF protection initiate LV side
HV EF Initiate LV
CBF
CBF
HV EF protection initiate MV side
HV EF Initiate
MV CBF
CBF
Table 53 Settings of earth fault protection for MV side of transformer
Setting
MV
3I0_EF1
MV T_EF1
MV
3I0_EF2
MV T_EF2
Default
Min.
Max.
(Ir:5A/1
(Ir:5A/1
A)
A)
0.05Ir
20Ir
60
60
0.05Ir
20Ir
60
60
Time setting for MV E/F, Stage 2
12
0.05Ir
20Ir
Unit
setting
(Ir:5A/1
Description
A)
MV earth fault (E/F) protection
Time setting for MV E/F, Stage 1
MV earth fault (E/F) current setting for Stage 2
MV
Curve_EF
Inv
MV 3I0_EF
Inv
111

MV K_EF
0.05
999
200
0.14
60
10
0.02
90
45
Inv
MV A_EF
Inv
MV B_EF
Inv
MV P_EF
Inv
MV Angle_EF

ahead of current.
st
MV
Imax_2H_U
0.25Ir
20Ir
nBlk_EF

block, in MV E/F protection
MV Ra-
0.07
tio_I2/I1_EF
0.5
0.2
nd
Inrush 2 harmonic ratio setting
for blocking MV E/F protection
Table 54 Binary settings of earth fault protection for MV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
st
The 1 stage of MV earth fault
MV Func_EF1

1-on; 0-off.
Direction (DIR) detection of MV
MV EF1 Direction
1-on; 0-off.
Direction unit of MV EF Stage 1
MV EF1 Dir To
Sys
points to system
0

1- point to system
MV EF1 Inrush
Block

0
1-on; 0-off.
The 2nd stage of MV earth fault
MV Func_EF2

1-on; 0-off.
MV EF2 Direction
1-on; 0-off.
112

Direction unit of MV EF Stage 2
MV EF2 Dir To
Sys
points to system
0

1- point to system
MV EF2 Inrush
Block
1-on; 0-off.
MV Func_EF Inv
MV EF protection is switched ON
1-on; 0-off.
MV EF Inv Direction

switched ON
1-on; 0-off.
Direction unit of MV EF IDMTL
MV EF Inv Dir To
Sys

0

1- point to system
MV EF Inv Inrush
Block

switched ON
1-on; 0-off.
Select to block MV EF protection
or exit direction unit, when MV VT
Block MV EF at
MV VT_Fail
fails
0 - MV Direct OK at MV VT Fail
1 - Blk MV EF at MV VT Fail
Block MV EF when there is MV CT
Block MV EF at
MV CT_Fail
failure
1-Block;
MV EF Initiate
HV CBF
0-NOT block
MV EF protection initiate HV1 side

0
CBF
113

Table 55 Settings of earth fault protection for LV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1
(Ir:5A/1
A)
A)
Default
setting
(Ir:5A/1
Description
A)
LV earth fault (E/F) protection
LV 3I0_EF1
0.05Ir
20Ir
LV T_EF1
60
60
LV 3I0_EF2
0.05Ir
20Ir
LV T_EF2
60
60
Time setting for LV E/F, Stage 2
12
0.05Ir
20Ir
0.05
999

Time setting for LV E/F, Stage 1
LV earth fault (E/F) current setting
for Stage 2
LV
Curve_EF
Inv
LV 3I0_EF
Inv
LV K_EF Inv
LV A_EF Inv
200
0.14
LV B_EF Inv
60
10
0.02
90
45
LV P_EF Inv
LV Angle_EF

ahead of current.
st
LV
Imax_2H_U
0.25Ir
20Ir
nBlk_EF
block, in LV E/F protection
LV Ra-
Inrush 2 harmonic ratio setting
nd
0.07
tio_I2/I1_EF
0.5
0.2
for blocking LV E/F protection
Table 56 Binary settings of earth fault protection for LV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
st
The 1 stage of LV earth fault

LV Func_EF1

1-on; 0-off.
Direction (DIR) detection of LV EF
LV EF1 Direction
1-on; 0-off.
114

Direction unit of LV EF Stage 1
LV EF1 Dir To
Sys
points to system
0

1- point to system
LV EF1 Inrush
Block

0
1-on; 0-off.
The 2nd stage of LV earth fault
LV Func_EF2

1-on; 0-off.
LV EF2 Direction
1-on; 0-off.
Direction unit of LV EF Stage 2
LV EF2 Dir To
Sys
points to system
0

1- point to system
LV EF2 Inrush
Block

0
1-on; 0-off.
LV Func_EF Inv
LV EF protection is switched ON
1-on; 0-off.
LV EF Inv Direction
IDMTL inverse time is switched

ON
1-on; 0-off.
Direction unit of LV EF IDMTL
LV EF Inv Dir To
Sys

0

1- point to system
LV EF Inv Inrush
Block

switched ON
1-on; 0-off.
115

Select to block LV EF protection or
Block LV EF at
LV VT_Fail
exit direction unit, when LV VT

0
fails
0 - LV Direct OK at LV VT Fail
1 - Blk LV EF at LV VT Fail
Block LV EF at
LV CT_Fail
Block LV EF when there is LV CT

0
failure
1-Block;
LV EF Initiate HV
CBF
0-NOT block
LV EF protection initiate HV1 side

0
CBF
Report
Information
Description
HV EF Inv Trip
Inverse time stage of HV earth fault protection trip
HV EF1 Trip
HV earth fault stage 1 trip
HV EF2 Trip
MV EF Inv Trip
Inverse time stage of MV earth fault protection trip
MV EF1 Trip
MV earth fault stage 1 trip
MV EF2 Trip
LV EF Inv Trip
Inverse time stage of LV earth fault protection trip
LV EF1 Trip
LV earth fault stage 1 trip
LV EF2 Trip
Information
Description
HV Func_EF On
Earth fault protection of HV side is switched ON (by CW)
HV Func_EF Off
Earth fault protection of HV side is switched OFF (by CW)
MV Func_EF On
Earth fault protection of MV side is switched ON (by CW)
MV Func_EF Off
Earth fault protection of MV side is switched OFF (by CW)
LV Func_EF On
Earth fault protection of LV side is switched ON (by CW)
LV Func_EF Off
Earth fault protection of LV side is switched OFF (by CW)
116
Technical data
Table 59 Earth fault protection technical data
Item
Rang or value
Tolerance

Current
0.08 Ir to 20.00 Ir
Time delay
0.00 to 60.00s, step 0.01s

operating setting
Reset time
approx. 40ms
Reset ratio
Approx. 0.95 at I/Ir 0.5

Current
0.08 Ir to 20.00 Ir
IEC standard
Normal inverse;
IEC60255-151
Very inverse;
Extremely inverse;
<I/I SETTING < 20

R
Long inverse
ANSI
Inverse;
ANSI/IEEE C37.112,
Short inverse;
Long inverse;
<I/I SETTING < 20

R
Moderately inverse;
Very inverse;
Extremely inverse;
Definite inverse
IEC60255-151
T=
<I/I SETTING < 20

R
0.005 to 200.0s, step

0.001s
0.000 to 60.00s, step 0.01s
0.005 to 10.00, step 0.005
0.05 to 999.0, step 0.01
20ms
100s
Reset mode
instantaneous
Reset time
approx. 40ms
Directional element
Operating area range of zero

sequence directional element
160
0 to 90, step 1
Operating area range of negative
160
3, at 3U01V
3, at 3U22V
117

sequence directional element
118
50 to 90, step 1
119
Chapter 8 Neutral earth fault protection
Chapter 8 Neutral earth fault

protection
About this chapter

signals, parameter, IED report and technical data for neutral earth
fault protection function.
120
1.1
Protection Elements
Each voltage side of the protected transformer is provided with three neutral
earth fault protection elements from which two elements operate as definite
earth fault stages and the other one operates with inverse time-current characteristic. All the elements can operate in conjunction with the integrated inrush restraint and directional functions.
Various stages of each element are independent from each other and can be
dedicated Binary settings. These Binary settings include HV Func_Neu OC1,
HV Func_Neu OC2 and HV Func_Neu OC Inv, for HV side earth fault
protection, MV Func_Neu OC1, MV Func_Neu OC2 and MV Func_Neu
OC Inv, for MV side earth fault protection, LV Func_Neu OC1, LV
Func_Neu OC2 and LV Func_Neu OC Inv, for LV side earth fault protection.
For example by applying setting 1-on to HV Func_Neu OC1, respective
stage of neutral earth fault protection would be enabled in HV side.
3I0_Neutral OC1 and HV 3I0_Neutral OC2 for HV side, MV 3I0_Neutral
OC1 and MV 3I0_Neutral OC2 for MV side, LV 3I0_Neutral OC1 and LV
3I0_Neutral OC2 for LV side. By applying these settings, each neutral current
(quantity IN) measured from the installed neutral CT is compared separately
with the setting value for each stage. If the respective value is exceeded, a
trip time delay timer is started. The condition for start of the delay timer is expressed mathematically:
I N > I N _ set
Equation 35
be set for each definite stage individually through settings HV T_Neutral
OC1 and HV T_Neutral OC2 for HV side, MV T_Neutral OC1 and MV
T_Neutral OC2 for MV side, LV T_Neutral OC1 and LV T_Neutral OC2
for LV side. After the user-defined time delay has been elapsed, a trip signal is
issued if the inrush restraint feature is applied and no inrush current is detected or inrush restraint is disabled. The neutral earth fault protection would
be blocked and therefore, no tripping takes place if the inrush restraint feature
is enabled and an inrush condition exists. However, an alarm report is issued
nominated as HV Inrush Blk BU, MV Inrush Blk BU or LV Inrush Blk BU,
indicating the blocking condition of neutral earth fault element caused by inrush condition detection.
Pickup value for the inverse time-current stage can be set by setting HV
3I0_NOC Inv, MV 3I0_NOC Inv and LV 3I0_NOC Inv for HV, MV and LV
sides, respectively. Each neutral current (quantity IN) measured by installed
neutral CT is separately compared with corresponding setting value. If a current exceeds 1.1 times the setting value, corresponding stage picks up. When
121

an inverse time-current stage picks up, the tripping time is calculated from the
measured quantity IN, using the selected tripping curve. Maximum tripping
time is limited to 100s.
For Time-inverse characteristic, the pickup value can be defined by setting
3I0_NOC Inv. The measured zero sequence current is compared with corresponding setting value. If it exceeds the setting, related signal will be reported and the tripping time is calculated according to the pre-defined characteristic. The tripping curve can be set as IEC or ANSI standard curves or
any user-defined characteristic by following tripping time equation.
A _ NOC Inv
t = K _ NOC Inv
+
B
NOC
Inv
_
P _ NOC Inv
I
-1
IS
Equation 36
Where I is the calculated neutral current;
where:
xV A_NOC Inv: xV(HV/MV/LV) side time factor for inverse time stage
xV B_NOC Inv: xV(HV/MV/LV) time delay for inverse time stage
xV P_NOC Inv: xV(HV/MV/LV) index for inverse time stage
xV K_NOC Inv: xV(HV/MV/LV) time multiplier Inrush restraint feature
As mentioned previously, selection between the curves can be carried out by
settings HV Curve_NOC Inv, MV Curve_NOC Inv and LV Curve_NOC
Inv for HV, MV and LV sides, respectively. Furthermore, the time multiplier
K_NOC Inv can be applied by user to coordinate the integrated inverse
time-current characteristic of the device with other relays installed for power
system protection. This can be performed by settings HV K_NOC Inv, MV
K_NOC Inv and LV K_NOC Inv in case of HV, MV and LV neutral earth fault
elements.
By applying pickup current and time multiplier settings, the device determines
the tripping time from the measured neutral current, based on the selected
inverse curve. Once the calculated time has been elapsed, a trip signal is
issued provided that no inrush current is detected or inrush restraint is disabled. If the inrush restraint feature is enabled and an inrush condition exists,
the neutral earth fault protection would be blocked and therefore no tripping
takes place. However, alarm report of HV Inrush Blk BU, MV Inrush Blk BU
or LV Inrush Blk BU is issued, indicating the blocking condition of neutral
earth fault element caused by inrush condition detection.
each stage. They include HV Neu OC_1 Trip, HV Neu OC_2 Trip and HV
Neu OC IDMTL for HV side, MV Neu OC_1 Trip, MV Neu OC_2 Trip and
MV Neu OC IDMTL for MV side, LV Neu OC_1 Trip, LV Neu OC_1 Trip
122

and LV Neu OC IDMTL for LV side neutral earth fault elements.
1.2

The transformer neutral earth fault protection may detect large magnetizing
inrush currents flowing when transformer is energized. The inrush current
may be several times of the nominal current, and may last from several tens
of milliseconds to several seconds.
Inrush current comprises second harmonic as well as a considerable fundamental component. So, it may affect neutral earth fault protection which operates based on the fundamental component of the measured current. Inrush
blocking unit in neutral earth fault function is provided for this purpose.
It is possible to apply the inrush restraint feature separately to each definite
stage and inverse time-current stage of earth fault element by using Binary
settings HV Neu OC1 Inrush Block, HV Neu OC2 Inrush Block and HV
Neu OC Inv Inrush Block on for HV side, MV Neu OC1 Inrush Block, MV
Neu OC2 Inrush Block and MV Neu OC Inv Inrush Block on for MV side,
LV Neu OC1 Inrush Block, LV Neu OC2 Inrush Block and LV Neu OC Inv
Inrush Block on for LV side. By applying setting 1-on to each of the mentioned Binary settings, no trip command would be possible by corresponding
stage, if an inrush condition is detected.
Since the inrush current contains a relatively large second harmonic component which is nearly absent during a fault current, the inrush restraint operates based on the evaluation of the second harmonic content which is present
in the measured neutral current (quantity IN), or in the phase currents, based
on setting. The inrush condition is recognized if the ratio of second harmonic
current to the fundamental component exceeds the setting value HV Ratio_I2/I1_NOC, MV Ratio_I2/I1_NOC or LV Ratio_I2/I1_NOC in the
measured neutral current. The setting is applicable to both the definite stages
of neutral earth fault protection element as well as the inverse time-current
stage. As soon as the measured ratio exceeds the set threshold, a restraint is
applied to those stages for which corresponding setting is applied to make
them blocked in inrush condition detection (HV Neu OC1 Inrush Block, HV
Neu OC2 Inrush Block and HV Neu OC Inv Inrush Block for HV side, MV
Neu OC1 Inrush Block, MV Neu OC2 Inrush Block and MV Neu OC Inv
Inrush Block for MV side, LV Neu OC1 Inrush Block, LV Neu OC2 Inrush
Block and LV Neu OC Inv Inrush Block for LV side).
Furthermore, if the fundamental component of the measured neutral current
exceeds the upper limit value HV Imax_2H_UnBlk_NOC, MV
Imax_2H_UnBlk_NOC or LV Imax_2H_UnBlk_NOC, the inrush restraint
will no longer effective in respective side, since a high-current fault is assumed in this case.
1.3

The integrated directional function can be applied to each stage of neutral
earth fault elements via Binary settings. The Binary settings include HV Neu
OC1 Direction, HV Neu OC2 Direction and HV Neu OC Inv Direction on
for HV side earth fault stages, MV Neu OC1 Direction, MV Neu OC2 Direction and MV Neu OC Inv Direction for MV side earth fault stages and LV
123

Neu OC1 Direction, LV Neu OC2 Direction and LV Neu OC Inv Direction
for LV side earth fault stages.
Furthermore, the directional orientation can be set individually for each stage
of neutral earth fault elements in various sides of the protected transformer.
This can be performed by Binary settings HV Neu OC1 Dir To Sys, HV Neu
OC2 Dir To Sys and HV Neu OC Inv Dir To Sys for HV side, MV Neu OC1
Dir To Sys, MV Neu OC2 Dir To Sys and MV Neu OC Inv Dir To Sys for
MV side, LV Neu OC1 Dir To Sys, LV Neu OC2 Dir To Sys and LV Neu OC
Inv Dir To Sys for LV side. The possible settings for these Binary setting
comprise 0-toward transformer and 1-toward system.
Basically, the direction determination is performed by comparing the zero
sequence system quantities. In the current path, 3I0 current is measured from
the neutral CT installed at the transformer starpoint. In the voltage path, the
device calculates the zero sequence voltage 3V0 from the sum of the three
phase voltages. Contrary to the directional phase elements, which work with
the un-faulted voltage as reference voltage, in this application, the fault voltage itself is the reference voltage. Depending on the connection of the voltage transformer, this is the voltage 3V0 or VN. The directional element at
each side operates with the residual/ neutral voltage of the same side.
In order to satisfy different network conditions and applications, the reference
voltage can be rotated by an adjustable angle. For each side of the protected
transformer, the directional angle can be set independently. The settings include HV Angle_NOC, MV Angle_NOC and LV Angle_NOC, for HV, MV
and LV sides, respectively. It should be noted that the settings affect all the
directional stages of the corresponding neutral earth fault element.
3I 0
90
0
3U 0_Ref
Angle_EF
Angle_Range
EF
Forward
-3 I 0
Bisector
Figure 44 Neutral directional element characteristic

where:
Angle_OC: The settable characteristic angle
Angle_Range OC: 80
124

circuit or broken wire in the voltage transformer's secondary system or an
operation of the voltage transformer fuse) may result in false or undesired
tripping by directional neutral earth fault elements. In such a situation, it is
possible to select operation status of the directional neutral earth fault protection elements in each side by using a number of Binary settings to block
the neutral earth fault protection elements or keep them in operational state
with no direction decision (block direction decision). The Binary settings are
designated as Block HV NOC at HV VT_Fail, Block MV NOC at HV
VT_Fail and Block LV NOC at HV VT_Fail, for HV, MV and LV sides, respectively. When the Binary settings are set as 0 to select Direct OK at VT
Fail, corresponding neutral earth fault protection elements will not judge direction at the local side VT failure. When they set as 1 to select Blk NEU OC
at VT Fail, no operation is possible by the neutral earth fault protection elements. It is noted that the Binary settings affect all the stages of corresponding neutral earth fault elements at each side. For instance, by applying setting
Block HV NOC at HV VT_Fail off, all the three stages of the neutral earth
fault element will remain operative without direction determination in case of
any fault in secondary circuit of HV side voltage transformer. On the other
hand, setting Block HV NOC at HV VT_Fail on makes them blocked.
The logic for definite and inverse time IDMTL neutral earth fault protection is
Neu OC Direction on
1
Dir_Forward
And
Or
NOC Direction Unit OK
VT failure
And
Func_Neu OC12 on
1
3I0 > 3I0_Neutral OC12
1)
And
Neutral OC Trip
Inrush BLK NEF
Func_Neu OC Inv on
1
3I0>3I0_NOC Inv
And
NOC Inv Trip
Inrush BLK NOC

1) t: T_Neutral OC1(2)
Figure 45 Tripping logic for neutral earth fault protection
125

1.4

It is possible to set whether the neutral earth fault protection elements can initiate the integrated CBF protection or not. The available choices depend on
the voltage side of the power transformer at which neutral earth fault protection is applied. In this context, HV side neutral earth fault protection element
always initiates HV side CBF function with no additional setting. However, it is
possible to select whether it can initiate MV and LV CBF protection functions
via Binary settings HV Neu OC Init LV CBF and HV Neu OC Init MV CBF,
respectively.
MV side neutral earth fault protection element always initiates MV side CBF
function with no additional setting.

Neutral Earth
Fault Protection
INBK
NEF1 Trip
UA
NEF2 Trip
UB
NEF Inv Trip
UC
Relay Startup
Figure 46 Neutral earth fault protection module

Table 60 Analog output list
Signal
Description
INBK
UA
UB
UC
Neutral current input of HV side, MV side, or LV side of transformer

Phase A voltage input of HV side, MV side, or LV side of transformer
Phase B voltage input of HV side, MV side, or LV side of transformer
Phase C voltage input of HV side, MV side, or LV side of transformer

Signal
Description
NOC1 Trip
NOC2 Trip
NOC Inv Trip
Relay Startup
Neutral Earth Fault stage 1 trip

Neutral Earth Fault stage 2 trip
Neutral Earth Fault inverse stage trip
Relay Startup
126
Setting
Table 62 Settings of neutral earth fault protection for HV side of transformer
Setting
Unit
Min.
(Ir:5A/1
A)
Max.
(Ir:5A/1
A)
Default
setting
(Ir:5A/1
A)
0.05Ir
20Ir
HV neutral over-current (NOC)

protection current setting for
Stage 1
Description
HV
3I0_Neutral
OC1
HV
T_Neutral
OC1
HV
3I0_Neutral
OC2
HV
T_Neutral
OC2
HV
Curve_NOC
Inv
60
60
Time setting for HV NOC, Stage

1
0.05Ir
20Ir
HV neutral over-current (NOC)

Stage 2
60
60
Time setting for HV NOC, Stage

1
12
HV 3I0_NOC
Inv
0.05Ir
20Ir
0.05
999
HV K_NOC
Inv
HV A_NOC
Inv
200
0.14
HV B_NOC
Inv
60
10
0.02
90
45

ahead of current.
HV P_NOC
Inv
HV Angle_NOC
HV
Imax_2H_Un
Blk_NOC
HV Ratio_I2/I1_NO
C
0.25Ir
20Ir

inrush block, in HV NOC protection
0.07
0.5
0.2
Inrush 2nd harmonic ratio setting

for blocking HV NOC protection
127

Table 63 Binary settings of neutral earth fault protection for HV side of transformer
Setting
Unit
Min.
Max.
Default
setting
HV Func_Neu
OC1
HV Neu OC1 Direction
HV Neu OC1 Dir

To Sys
HV Neu OC1 Inrush Block
HV Func_Neu
OC2
HV Neu OC2 Dir

To Sys
HV Func_Neu OC
Inv
HV Neu OC Inv
Direction
HV Neu OC Inv Dir

To Sys
128
Description
The 1st stage of HV neutral OC
(OC_1) protection is switched
ON
1-on; 0-off.
neutral OC Stage 1 is switched
ON
1-on; 0-off.
Direction unit of HV neutral OC
Stage 1 points to system
1- point to system
HV neutral OC Stage 1 is
switched ON
1-on; 0-off.
The 2nd stage of HV neutral OC
ON
1-on; 0-off.
ON
1-on; 0-off.
1- point to system
switched ON
1-on; 0-off.
HV neutral OC protection is
switched ON
1-on; 0-off.
neutral OC IDMTL inverse time
stage is switched ON
1-on; 0-off.
IDMTL inverse time stage points
to system
1- point to system
HV Neu OC Inv
Inrush Block
Block HV NOC at
HV VT_Fail
HV Neu OC Init
MV CBF

HV neutral OC IDMTL inverse
time stage is switched ON
1-on; 0-off.
Select to block HV neutral OC
protection or exit direction unit,
when HV VT fails
0 - HV Direct OK at HV VT Fail
1 - Blk HV NOC at HV VT Fail
HV neutral OC protection initiate
LV side CBF
Table 64 Settings of neutral earth fault protection for MV side of transformer
Setting
MV
3I0_Neutral
OC1
MV
T_Neutral
OC1
MV
3I0_Neutral
OC2
MV
T_Neutral
OC2
MV
Curve_NOC
Inv
MV
3I0_NOC Inv
Unit
Min.
(Ir:5A/1
A)
Max.
(Ir:5A/1
A)
Default
setting
(Ir:5A/1
A)
0.05Ir
20Ir
MV neutral over-current (NOC)

Stage 1
60
60
Time setting for MV NOC, Stage

1
Description
0.05Ir
20Ir
MV neutral over-current (NOC)

Stage 2
60
60
Time setting for MV NOC, Stage

1
12
0.05Ir
20Ir
0.05
999
MV K_NOC
Inv
MV A_NOC
Inv
200
0.14
MV B_NOC
Inv
60
10
0.02
90
45

ahead of current.

inrush block, in MV NOC protection
MV P_NOC
Inv
MV Angle_NOC
MV
Imax_2H_Un
Blk_NOC
0.25Ir
20Ir
129

MV Ratio_I2/I1_NO
C
0.07
0.5
0.2

for blocking MV NOC protection
Table 65 Binary settings of neutral earth fault protection for MV side of transformer
Setting
Unit
Min.
Max.
Default
setting
MV Func_Neu
OC1
MV Neu OC1 Direction
MV Neu OC1 Dir

To Sys
MV Neu OC1 Inrush Block
MV Func_Neu
OC2
MV Neu OC2 Dir

To Sys
MV Func_Neu OC
Inv
MV Neu OC Inv
Direction
130
Description
The 1st stage of MV neutral OC
ON
1-on; 0-off.
ON
1-on; 0-off.
Direction unit of MV neutral OC
1- point to system
MV neutral OC Stage 1 is
switched ON
1-on; 0-off.
The 2nd stage of MV neutral OC
ON
1-on; 0-off.
ON
1-on; 0-off.
1- point to system
switched ON
1-on; 0-off.
MV neutral OC protection is
switched ON
1-on; 0-off.
1-on; 0-off.
MV Neu OC Inv
Dir To Sys
MV Neu OC Inv
Inrush Block
Block MV NOC at
MV VT_Fail
MV Neu OC Init
MV CBF

to system
1- point to system
nd
Inrush 2 harmonic detection
MV neutral OC IDMTL inverse
time stage is switched ON
1-on; 0-off.
Select to block MV neutral OC
when MV VT fails
0 - MV Direct OK at MV VT Fail
1 - Blk MV NOC at MV VT Fail
MV neutral OC protection initiate
LV side CBF
Table 66 Settings of neutral earth fault protection for LV side of transformer
Setting
Unit
Min.
(Ir:5A/1
A)
Max.
(Ir:5A/1
A)
Default
setting
(Ir:5A/1
A)
Description
LV
3I0_Neutral
OC1
0.05Ir
20Ir
LV neutral over-current (NOC)

Stage 1
LV T_Neutral
OC1
60
60
Time setting for LV NOC, Stage 1
LV
3I0_Neutral
OC2
0.05Ir
20Ir
LV neutral over-current (NOC)

Stage 2
LV T_Neutral
OC2
60
60
Time setting for LV NOC, Stage 1
12
0.05Ir
20Ir
0.05
999
LV
Curve_NOC
Inv
LV 3I0_NOC
Inv
LV K_NOC
Inv
LV A_NOC
Inv
200
0.14
LV B_NOC
Inv
60
10
0.02
LV P_NOC
Inv
131
LV Angle_NOC
LV
Imax_2H_Un
Blk_NOC
90
45

ahead of current.
0.25Ir
20Ir

inrush block, in LV NOC protection
0.07
0.5
0.2

for blocking LV NOC protection
LV Ratio_I2/I1_NO
C
Table 67 Binary settings of neutral earth fault protection for LV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
st
LV Func_Neu OC1
LV Neu OC1 Direction
LV Neu OC1 Dir To

Sys
LV Neu OC1 Inrush

Block
LV Func_Neu OC2
LV Neu OC2 Dir To

Sys
LV Neu OC2 Inrush

Block
LV Func_Neu OC
Inv
132
The 1 stage of LV neutral OC

ON
1-on; 0-off.
ON
1-on; 0-off.
Direction unit of LV neutral OC
1- point to system
ON
1-on; 0-off.
The 2nd stage of LV neutral OC
ON
1-on; 0-off.
ON
1-on; 0-off.
1- point to system
ON
1-on; 0-off.
LV neutral OC protection is
switched ON
1-on; 0-off.
LV Neu OC Inv Direction
LV Neu OC Inv Dir

To Sys
LV Neu OC Inv Inrush Block
Block LV NOC at LV
VT_Fail
LV Neu OC Init LV
CBF

1-on; 0-off.
to system
1- point to system
nd
Inrush 2 harmonic detection LV
1-on; 0-off.
Select to block LV neutral OC
when LV VT fails
0 - LV Direct OK at LV VT Fail
1 - Blk LV NOC at LV VT Fail
LV neutral OC protection initiate
LV side CBF
Report
Information
Description
HV NOC Inv Trip
Inverse time stage of neutral OC protection trip
HV NOC1 Trip
HV neutral OC stage 1 trip
HV NOC2 Trip
MV EF Inv Trip
Inverse time stage of MV neutral OC protection trip
MV EF1 Trip
MV neutral OC stage 1 trip
MV EF2 Trip
LV EF Inv Trip
Inverse time stage of LV neutral OC protection trip
LV EF1 Trip
LV neutral OC stage 1 trip
LV EF2 Trip

Information
Description
HV Func_NOC On
NOC protection of HV side is switched ON (by CW)
HV Func_NOC Off
NOC protection of HV side is switched OFF (by CW)
MV Func_NOC On
NOC protection of MV side is switched ON (by CW)
MV Func_NOC Off
NOC protection of MV side is switched OFF (by CW)

133
Information
Description
LV Func_NOC On
NOC protection of LV side is switched ON (by CW)
LV Func_NOC Off
NOC protection of LV side is switched OFF (by CW)
Technical data
Table 70 Neutral earth fault protection technical data
Item
Rang or value
Tolerance

Current
0.08 Ir to 20.00 Ir
Time delay
0.00 to 60.00s, step 0.01s
Reset time
approx. 40ms
Reset ratio
Approx. 0.95 at I/Ir 0.5

Current
IEC standard
0.08 Ir to 20.00 Ir
ANSI
Normal inverse;
Very inverse;
Extremely inverse;
Long inverse
Inverse;
Short inverse;
Long inverse;
Moderately inverse;
Very inverse;
Extremely inverse;
Definite inverse
operating setting
<I/I SETTING < 20, in accordance with
IEC60255-151
R
<I/ISETTING < 20, in accordance
with ANSI/IEEE C37.112,
<I/I SETTING < 20, in accordance with
IEC60255-151
T=
0.005 to 200.0s, step

0.001s
0.000 to 60.00s, step 0.01s
0.005 to 10.00, step 0.005
0.05 to 999.0, step 0.01
20ms
100s
Reset mode
instantaneous
Reset time
approx. 40ms
Directional element
160
0 to 90, step 1
160
0 to 90, step 1
134
3, at 3U01V
3, at 3U22V
Chapter 9 Thermal overload protection
Chapter 9 Thermal overload

protection
About this chapter

signals, parameter, IED report and technical data for thermal
overload protection function.
135
Introduction
The insulating material surrounding the transformer windings ages rapidly if
the temperature exceeds the design limit value. Furthermore, by using less
and less metal per MVA of transformed power, the designed limit value is
reduced in modern power transformers. Hence, it represents an essential
requirement to provide thermal protection to supplement the winding temperature device. The thermal overload protection estimates winding temperature
and therefore prevents damage to transformer caused by thermal overloading.
The thermal overload protection includes two stages (alarm and trip). They
work by using an approximate replica of the temperature rise in the protected
object caused by overload. The thermal replica is implemented based on
thermal models (Cold / Hot Curve) of IEC60255-8 Std., without ambient
temperature influence.
Both of the alarm and trip stages can be enabled or disabled by using Binary
setting HV Func_Thermal OvLd, MV Func_Thermal OvLd or LV
Func_Thermal OvLd on. The thermal overload protection can be assigned to
any desired side (HV, MV or LV) of the protected object. However, for transformers with tap changer, it is recommended to use the function on the
non-regulated side. To enable the protection on each side, setting of 1-on
should be applied to corresponding Binary setting.
Both of the thermal overload stages can use cold curve or hot curve in their
calculations, based on the setting applied at Binary setting HV Cold Curve,
MV Cold Curve or LV Cold Curve. If the protection is enabled in one side,
and the measured current in each phase of the protected transformer in corresponding side exceeds the threshold defined by setting HV I_Therm OL
Alarm, MV I_Therm OL Alarm or LV I_Therm OL Alarm, a counter is incremented from 0% to 100%. When the counter is accumulated to its alarm
setting which correspond to the expiration of alarm time delay according to
the selected cold/hot characteristic, the alarm report HV Load Alarm, MV
Load Alarm or LV Load Alarm is given to allow a preventive load reduction.
The alarm signal is cancelled as soon as the measured phase current falls
below the threshold defined by setting HV I_Therm OL Alarm, MV I_Therm
OL Alarm or LV I_Therm OL Alarm. However, the counter is decremented to
zero according to cool down time of the transformer (the time by which the
thermal replica counter reaches from 100% to 0%). The cool down time is
informed to the device by setting HV T_Const Cool Down, MV T_Const
Cool Down and LV T_Const Cool Down.
Similarly, if the measured current in each phase of the protected transformer
in corresponding side exceeds the threshold defined by setting HV I_Therm
OL Trip, MV I_Therm OL Trip or LV I_Therm OL Trip, a counter is incremented from 0% to 100%. If the counter reaches to 100% corresponding to
expiration of trip time delay according to the selected cold/hot characteristic,
the event report HV THERM Trip, MV THERM Trip or LV THERM Trip is
136

given. The alarm signal is cancelled as soon as the measured phase current
falls below the threshold defined by setting HV I_Therm OL Trip, MV
I_Therm OL Trip or LV I_Therm OL Trip. However, the counter is decremented to zero according to cool down time of the transformer which is entered into the device by setting HV T_Const Cool Down, MV T_Const Cool
Down and LV T_Const Cool Down.
The cold and hot curves used in each thermal overload stages, is based on
thermal curves defined in IEC 60255-8 Std.
The curves provide an operating current/time characteristic that corresponds
to the current overload characteristic of the transformer windings. The formulas corresponding to cold and hot curve is denoted by (1-46) and (1-47),
respectively. The cold curve provides no memory regarding to previous
thermal condition of the transformer, whereas, by using the hot curve, the
protection function is able to represent a memorized thermal profile of the
protected transformer.
2
I ph
= ln 2
2
I ph I
Equation 37
2
I ph
I P2
= ln 2
2
I ph I
Equation 38
Where,
t is alarm/trip time of thermal overload protection function in seconds,
is thermal time constant of heating for the power transformer, in seconds. It
is usually provided by the manufacturer. The device is informed about it by
settings HV T_Const Therm, MV T_Const Therm and H\LV T_Const
Therm.
Iph is the current flowing through corresponding side of the transformer, in
each phase. It means that the calculation is performed separately for each
phase, based on fundamental component measurement and also includes
the effect of harmonic contents up to 7th harmonic. Thus, the minimum calculated alarm/ trip time is decisive for evaluation of the thresholds.
I is the setting for alarm and trip stages of the thermal overload protection, in
rms. It should be set considering the maximum permissible thermal continuous overload current of the transformer windings and insulations. The setting
is applied by using HV I_Therm OL Alarm and HV I_Therm OL Trip for HV
side, MV I_Therm OL Alarm and HV I_Therm OL Trip for MV side, and
H\LV I_Therm OL Alarm and HV I_Therm OL Trip for LV side of the power
transformer.
IP is the prior current to overload, assuming sufficient time to reach
137

steady-state temperature.
NOTE: When Binary setting xx Curve/Hot Curve is set to 0, and fundamental
current is less than the settings, and the heat accumulation is cleared and set
as 0 automatically.

Thermal Overload
Protection
IA1
Therm OL Trip
IB1
Therm OL Alarm
IC1
Relay Startup
IA2
IB2
IC2
Figure 47 Thermal overload protection module

Signal
Description
IA1
IB1
IC1
IA2
IB2
IC2


Signal
Description
Therm OL Trip
Therm OL Alarm
Relay Startup
Thermal overload trip

Thermal overload alarm
Relay Startup
138
Setting
Table 73 Settings of thermal overload protection for HV side of transformer
Unit
Min.
(Ir:5A/
1A)
Max.
(Ir:5A/
1A)
Default
setting
(Ir:5A/
1A)
HV I_Therm OL Trip
0.1Ir
5Ir
Setting for HV-side thermal

overload trip-stage current
HV I_Therm OL Alarm
0.1Ir
5Ir
Setting for HV-side thermal

overload alarm-stage current
HV T_Const Therm
9999
10
Time const for HV-side

thermal overload protection
HV T_Const Cool
Down
9999
10

HV-side thermal overload
Setting
Description
Table 74 Binary settings of thermal overload protection for HV side of transformer

Min.
Max.
Default
setting
HV Func_Thermal
OvLd
HV Cold Curve
HV Thermal Init LV
CBF
HV thermal overload protection initiate LV side CBF

HV Thermal Init MV
CBF
HV thermal overload protection initiate MV side CBF

Setting
Unit
Description
Thermal overload in HV side
is switched on
0 - OFF, 1 - ON
HV side using hot/cold curve
type
0 Hot curve, 1 Cold curve
Table 75 Settings of thermal overload protection for MV side of transformer
Unit
Min.
(Ir:5A/
1A)
Max.
(Ir:5A/
1A)
Default
setting
(Ir:5A/
1A)
MV I_Therm OL Trip
0.1Ir
5Ir
MV I_Therm OL
Alarm
0.1Ir
5Ir
MV T_Const Therm
9999
10
Setting
Description
Setting for MV-side thermal
overload trip-stage current
Setting for MV-side thermal
overload alarm-stage current
Time const for MV-side
139
MV T_Const Cool
Down

MV-side thermal overload
10
9999
Table 76 Binary settings of thermal overload protection for MV side of transformer

Min.
Max.
Default
setting
MV Func_Thermal
OvLd
Thermal overload in MV side

is switched on
0 - OFF, 1 - ON
MV Cold Curve
MV side using hot/cold curve

type
MV Thermal Init HV1

CBF
MV thermal overload protection initiate HV side CBF

Setting
Unit
Description
Report
Information
Description
HV Therm OL Trip
HV Thermal (TEM) Overload(OVLD) tripping (Trip)
MV Therm OL Trip
MV Thermal (TEM) Overload(OVLD) tripping (Trip)

Information
Description
HV Therm OL Alm
HV Thermal overload Alarm
MV Therm OL Alm
MV Thermal overload Alarm

Information
Description
HV Func_Therm On
HV thermal overload protection is switched ON (by CW)
HV Func_Therm Off
HV thermal overload protection is switched OFF (by CW)
MV Func_Therm On
MV thermal overload protection is switched ON (by CW)
MV Func_Therm Off
MV thermal overload protection is switched OFF (by CW)
140
Technical data
Table 80 Thermal overload protection technical data
Item
Rang or Value
Current
0.1 Ir to 5.00 Ir
Thermal heating time constant
1 to 9999 s
Thermal cooling time constant
1 to 9999 s
Tolerance
IEC cold curve
I eq2
= ln 2
2
I eq I
IEC 602558,
5% setting or +40ms
IEC hot curve
I eq2 I P2
= ln 2
2
I eq I
IEC 602558,
5% setting or +40ms
141
142
Chapter 10 Overload protection
About this chapter

signals, parameter, IED report and technical data for overload
143
Overload protection is equipped for each voltage side and LV delta winding.
The function is to protect all sides of windings of transformer continuous
overload currents.
HV or MV or LV overload protection only comprises a definite time alarm
stage.
1
HV Func_OverLoad on
Max(IA,IB,IC)>HV
I_OverLoad
HV T_OverLoad
A
N
D
Load Alarm
Figure 48 The logic for HV overload protection

The LV winding overload includes one alarm and two definite time tripping
stages, namely low-setting tripping stage and high-setting tripping stage. The
two tripping stage can be set respective to initiate each side CBF or not
The logic for overload protection is shown in below figure.
1
LW Func_OvLd Alarm on
Max(IA,IB,IC)> I_OverLoad
&
T_OverLoad
LW Func_OvLd Low Trip on

1
Max(IA,IB,IC)> LW I_OvLd
Low Trip
&
LW T_OvLd
Low Trip
&
LW T_OvLd High
Trip
LW Func_OvLd High Trip on

1
Max(IA,IB,IC)>LW I_OvLd
High Trip
LW Load Alarm
LW Load Low_Stg
LW Load High_Stg
Figure 49 The logic for LV winding overload protection
144

Overload Protection
IA1
Overload Alarm
IB1
Relay Startup
IC1
IA2
IB2
IC2
Figure 50 Overload protection module for HV, MV, or LV side of

transformer
Delta Winding
Overload Protection
IA
Overload high set trip
IB
Overload low set trip
IC
Overload Alarm
Relay Startup
Figure 51 Overload protection module for LV delta winding of

transformer
Signal
Description
IA1
IB1
IC1
IA2
IB2
IC2


Signal
Description
Overload Alarm
Relay Startup
Overload Alarm
Relay Startup
145
Setting
Table 83 Setting of overload protection for HV side of transformer
Unit
Min.
(Ir:5A/
1A)
Max.
(Ir:5A/
1A)
Default
setting
(Ir:5A/1
A)
HV I_OverLoad
0.1Ir
4Ir
Overcurrent Setting of overload
HV T_OverLoad
0.1
3600
10
Time setting for overload
Setting
Description
Table 84 Binary settings of overload protection for HV side of transformer

Setting
Unit
Min.
Max.
Default
setting
HV Func_OverLoad
Description
Overload (LOAD) protection
in HV side is switched ON
1-on; 0-off.
Table 85 Setting of overload protection for MV side of transformer
Unit
Min.
(Ir:5A/
1A)
Max.
(Ir:5A/
1A)
Default
setting
(Ir:5A/
1A)
MV I_OverLoad
0.1Ir
4Ir
MV T_OverLoad
0.1
3600
10
Setting
Description
Table 86 Binary settings of overload protection for MV side of transformer

Setting
Unit
Min.
Max.
Default
setting
MV Func_OverLoad
Description
Overload (LOAD)in MV side
on
Table 87 Setting of overload protection for LV side of transformer
Unit
Min.
(Ir:5A/
1A)
Max.
(Ir:5A/
1A)
Default
setting
(Ir:5A/
1A)
LV I_OverLoad
0.1Ir
4Ir
LV T_OverLoad
0.1
3600
10
Setting
146
Description

Table 88 Binary settings of overload protection for LV side of transformer
Setting
Unit
LV Func_OverLoad
Min.
Max.
Default
setting
Description
Overload (LOAD)in LV side
on
Table 89 Setting of overload protection for LV delta winding of transformer
Setting
Unit
Min.
(Ir:5A/
1A)
Max.
(Ir:5A/
1A)
Default
setting
(Ir:5A/1
A)
Description
Alarm current setting of LV delta

winding overload protection
LW I_OvLd Alarm
0.1Ir
4Ir
20
LW T_OvLd Alarm
0.1
3600
10
0.1Ir
4Ir
20
0.1
3600
10
Low stage tripping time setting
0.1Ir
4Ir
20
High stage tripping current setting
0.1
3600
10
High stage tripping time setting
LW I_OvLd Low
Trip
LW T_OvLd Low
Trip
LW I_OvLd High
Trip
LW T_OvLd High
Trip
Alarm time setting of LV delta

winding overload protection
Low stage tripping current setting
Table 90 Binary settings of overload protection for LV delta winding of transformer

Setting
Unit
Min.
Max.
Default
setting
LW Func_OvLd
Alarm
LW Func_OvLd Low
Trip
LW Func_OvLd High
Trip
Low Trip Init HV1 CBF
High Trip Init HV1 CBF
Description
Alarm stage of LV delta
winding (LWIND) overload
(LOAD) protection is
switched ON.
1-on; 0-off.
Low-setting trip stage of LV
delta winding overload protection is switched ON.
1-on; 0-off.
High-setting trip stage of LV
1-on; 0-off.
delta winding overload protection initiate HV1 side CBF
147
Low Trip Init MV CBF
High Trip Init MV CBF

delta winding overload protection initiate MV side CBF
- initiate, 1 not initiate
Report
Information
Description
LW Load Low_Stg
LV delta winding (LWIND) overload (LOAD) protection low setting

trip
LV delta winding (LWIND) overload (LOAD) protection high setting
trip
LW Load High_Stg

Information
Description
HV Load Alarm
HV overload Alarm
MV Load Alarm
MV overload Alarm
LV Load Alarm
LV overload Alarm

Information
Description
HV Func_OL On
HV overload protection is switched ON (by CW)
HV Func_OL Off
HV overload protection is switched OFF (by CW)
MV Func_OL On
MV overload protection is switched ON (by CW)
MV Func_OL Off
MV overload protection is switched OFF (by CW)
LV Func_OL On
LV overload protection is switched ON (by CW)
LV Func_OL Off
LV overload protection is switched OFF (by CW)
148
Chapter 11 Overvoltage protection
About this chapter

signals, parameter, IED report and technical data used for overvoltage protection.
149
Introduction
Voltage protection has the function to protect electrical equipment against
overvoltage condition. Abnormally high voltages often occur e.g. in low
loaded, long distance transmission lines, in islanded systems when generator
voltage regulation fails, or after full load shutdown of a generator from the
system. Even if compensation reactors are used to avoid line overvoltage by
compensation of the line capacitance and thus reduction of the overvoltage,
the overvoltage will endanger the insulation if the reactors fail (e.g. fault
clearance). The line must be disconnected within very short time.
The protection provides the following features:
Two definite time stages
Each stage can be set to alarm or trip
Measuring voltage between phase-earth voltage and phase-phase (selectable)
Settable dropout ratio
2.1
Phase to phase overvoltage protection

All the three phase voltages are measured continuously, and compared with
the corresponding setting value. If a phase voltage exceeds the set thresholds, HV U_OV1 or HV U_OV2 for HV said, MV U_OV1 or MV U_OV2
for MV said, after expiry of the time delays, HV T_OV1 or HV T_OV2, and
MV T_OV1 or MV T_OV2, the protection IED will issue alarm signal or trip
command according to the users requirement.
There are two stages included in overvoltage protection, each stage can be
set to alarm or trip separately in binary setting, and the time delay for each
stage can be individually set. Thus, the alarming or tripping can be
time-coordinated based on how severe the voltage increase, e.g. in case of
high overvoltage, the trip command will be issued with a short time delay,
whereas for the less severe overvoltage, trip or alarm signal can be issued
with a longer time delay.
150

Additionaly, the dropout ratio of the overvoltage protection can be set in setting Dropout_OV. Therefore, the trip command of overvoltage is reset if the
measured voltage comes bellow the ratio value mentioned in this setting.
2.2
Phase to earth overvlotage protection

The phase to earth overvoltage protection operates just like the phase to
phase protection except that it detects phase to earth voltages.
Logic diagram
Ua>HV U_OV1
Ub>HV U_OV1
O
R
HV OV Chk PE on
Uc>HV U_OV1
HV OV1 Trip on
Trip
Uab>HV U_OV1
Ubc>HV U_OV1
O
R
HV OV Chk PE off
O
R
HV T_OV1
HV OV1 Trip off
Uca>HV U_OV1
Alarm
Figure 52 Logic diagram for overvoltage protection

Overvoltage Protection
UA
OV1 Trip
UB
OV2 Trip
UC
OV1 Alarm
OV2 Alarm
Relay Startup
Figure 53 Overvoltage protection module
151

Signal
Description
UA
UB
UC
Signal
Description
OV1 Trip
OV stage 1trip
OV2 Trip
OV stage 2trip
OV1 Alarm
OV stage 1 alarm
OV2 Alarm
OV stage 2 alarm
Relay Startup
Relay Startup
Setting
Table 96 Function setting list for overvoltage protection for HV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1
(Ir:5A/1
A)
A)
Default
setting
(Ir:5A/1
A)
HV U_OV1
40
200
200
HV T_OV1
60
60
HV U_OV2
40
200
200
HV T_OV2
60
60
0.9
0.99
0.95
HV Dropout_OV
152
Description
HV voltage setting for stage 1

of overvoltage protection
HV time setting for stage 1 of
overvoltage protection
HV voltage setting for stage 2
HV time setting for stage 2 of
HV dropout ratio for overvoltage protection

Table 97 Binary setting list for overvoltage protection for HV side of transformer
Setting
Unit
HV Func_OV1
HV Func_OV2
HV Func_OV2
HV OV2 Trip
Default
Min.
Max.
setting
Description
HV overvoltage stage 1 enabled
or disabled
HV overvoltage stage 1 trip or
alarm
HV overvoltage stage 2 enabled
or disabled
HV overvoltage stage 2 trip or
alarm
HV OV Chk PE
HV phase to phase voltage or

0
phase to earth measured for
Table 98 Function setting list for overvoltage protection for MV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1
(Ir:5A/1
A)
A)
Default
setting
(Ir:5A/1
A)
MV U_OV1
40
200
200
MV T_OV1
60
60
MV U_OV2
40
200
200
MV T_OV2
60
60
0.9
0.99
0.95
MV Dropout_OV
Description
MV voltage setting for stage 1

MV time setting for stage 1 of
MV voltage setting for stage 2
MV time setting for stage 2 of
MV dropout ratio for overvoltage protection
Table 99 Binary setting list for overvoltage protection for MV side of transformer
Setting
MV Func_OV1
MV Func_OV2
MV Func_OV2
Unit
Default
Min.
Max.
setting
Description
MV overvoltage stage 1 enabled
or disabled
MV overvoltage stage 1 trip or
alarm
MV overvoltage stage 2 enabled
or disabled
153

Setting
Unit
MV OV2 Trip
Min.
Max.
Default
setting
0
MV OV Chk PE
Description
MV overvoltage stage 2 trip or
alarm
MV phase to phase voltage or
phase to earth measured for

Report
Information
Description
HV OV1 Trip
HV overvoltage stage 1 trip
HV OV2 Trip
MV OV1 Trip
MV overvoltage stage 1 trip
MV OV2 Trip
Information
Description
HV OV1 Alarm
HV overvoltage stage 1 alarm
HV OV2 Alarm
HV overvoltage stage 2 alarm
MV OV1 Alarm
MV overvoltage stage 1 alarm
MV OV2 Alarm
MV overvoltage stage 2 alarm

Description of event
comment
HV Func_OV On
HV overvoltage protection is switched ON (by CW)
HV Func_OV Off
HV overvoltage protection is switched OFF (by CW)
MV Func_OV On
MV overvoltage protection is switched ON (by CW)
MV Func_OV Off
MV overvoltage protection is switched OFF (by CW)
154
Technical data
Table 103 Technical data for overvoltage protection
Item
Voltage connection
Rang or Value
Phase-to-phase voltages or
Tolerance
3 % setting or 1 V
phase-to-earth voltages
Phase to earth voltage
40 to 100 V, step 1 V
3 % setting or 1 V
Phase to phase voltage
80 to 200 V, step 1 V
3 % setting or 1 V
Reset ratio
0.90 to 0.99, step 0.01
3 % setting
Time delay
0.00 to 60.00 s, step 0.01s
1 % setting or +50 ms, at

120% energizing setting
Reset time
<40ms
155
156
Chapter 12 Circuit breaker failure protection
Chapter 12 Circuit breaker failure

protection
About this chapter

signals, parameter, IED report and technical data for circuit
breaker failure protection function.
157
Introduction
The circuit breaker failure (CBF) protection function monitors proper tripping
of the relevant circuit breaker. There are two separate CBF protection integrated in the IED. They are dedicated to HV and MV sides of the protected
transformer.
Normally, the circuit breaker should be tripped and therefore interrupt the fault
current whenever a short circuit protection function issues a trip command.
The circuit breaker failure protection provides rapid back-up fault clearance,
in the event of circuit breaker malfunction to respond to a trip command. This
feature can be enabled or disabled at each side of the protected transformer
via Binary settings HV1 CBF ON, MV CBF ON. If setting 1-On is applied
at these Binary settings, respective CBF protection will be switched on. In this
case, by operation of a protection function, and subsequent CBF initiation by
respective protection function, a report nominated as HV1 CBF INIT or MV
CBF INIT is generated by the IED. Furthermore, CBF initiation causes a
programmed timer to run toward a preset time delay limit. This time delay is
set by user under the settings HV1 T1_CBF or MV1 T1_CBF. If the circuit
breaker has not been opened after expiration of the preset time limit, the circuit breaker failure protection issues a command to trip circuit breaker (e.g.
via a second trip coil). Furthermore, event report of HV1 CBF T1 or MV
CBF T1is generated by the device. If the circuit breaker doesnt respond to
the repeated trip command, until another preset delay time which is set at
HV1 T2_CBF or MV1 T2_CBF, the protection issues a trip command to
isolate the fault by tripping other surrounding backup circuit breakers (e.g. the
other CBs connected to the same bus section as the faulty CB). Furthermore,
event report of HV1 CBF T2 or MV CBF T2 is generated in this case.
Initiation of CBF protection can be carried out by both the internal and external protection functions. If it is desired to initiate the CBF protection by means
of external protection functions, they should be marshaled to Binary input (BI)
of HV1 CBF EXT. INT or MV CBF EXT. INT for HV or MV CBF protection
respectively. Internal protection functions can initiate the CBF protection integrated in IED (HV and/or MV CBF), according to the mapping shown in
below table.
158

Table 104 Internal functions mapping to initiate CBF protection
CBF
PROTECTION FUNCTIONS
INITIATION
HV1
MV
Percent Differential Protection Trip [IDIFF>]
High-Set Differential Protection Trip [IDIFF>>]
HV Restricted Earth Fault Protection Trip
MV Restricted Earth Fault Protection Trip
LV Restricted Earth Fault Protection Trip
Overexcitation Protection INV Trip
Overexcitation Protection DEF Trip [U/f >>]
HV Thermal Overload Protection Trip
CW [0/1]
CW [0/1]
MV Thermal Overload Protection Trip
CW [0/1]
LV Thermal Overload Protection Trip
CW [0/1]
HV Overcurrent Protection Trip [INV / DEF (Stage-1,2)]
CW [0/1]
CW [0/1]
MV Overcurrent Protection Trip [INV / DEF Stage-1,2)]
CW [0/1]
LV Overcurrent Protection Trip [INV / DEF (Stage-1,2)]
CW [0/1]
HV Earth Fault Protection Trip [INV / DEF (Stage-1,2)]
CW [0/1]
CW [0/1]
MV Earth Fault Protection Trip [INV / DEF (Stage-1,2)]
CW [0/1]
LV Earth Fault Protection Trip [INV / DEF (Stage-1,2)]
CW [0/1]
HV Neutral Current Protection Trip [INV / DEF

(Stage-1,2)]
CW [0/1]
CW [0/1]
MV Neutral Current Protection Trip [INV / DEF

(Stage-1,2)]
CW [0/1]
LV Neutral Current Protection Trip [INV / DEF

(Stage-1,2)]
CW [0/1]
Overload Protection for LV Winding Low-Stage Trip

(Inside Delta)
CW [0/1]
CW [0/1]
Over Load Protection for LV Winding

(Inside Delta)
CW [0/1]
CW [0/1]
DI1 Trip
CW [0/1]
CW [0/1]
CW [0/1]
DI2 Trip
CW [0/1]
CW [0/1]
CW [0/1]
High-Stage Trip
159

In above table,
:means that the protection function working at a given side of the protected
transformer always initiate the CBF protection applied in specified side of the
power transformer. As can be seen, differential, restricted earth fault and
overexcitation protection functions initiate CBF protection in each side of
protected transformer with no additional settings.
The statement CW [0/1] means that the protection function can initiate CBF
protection according to the setting which is applied at respective Binary setting. The setting includes 1: Initiate the CBF and 0: Dont initiate the CBF.
Related Binary settings are available for specific functions which include
thermal overload, overcurrent, earth fault and neutral earth fault protections.
Furthermore, the dash sign means that it is not possible to initiate CBF protection of respective side by operation of a protection function working at a
given side of the protected transformer.
There are two criteria for breaker failure detection: the first one is to check
whether the actual current flow effectively disappeared after a tripping command had been issued. The second one is to evaluate the circuit breaker
auxiliary contact status. Since circuit breaker is supposed to be open when
current disappears from the circuit, the first criterion (current monitoring) is
the most reliable means for relay to be informed about proper operation of
circuit breaker. Therefore, current monitoring is applied to detect circuit
breaker failure condition. In this context, the monitored current of each phase
is compared with the pre-defined setting. The settings are applied at HV1
I_CBF OC or MV I_CBF OC, for HV or MV CBF protection.
Furthermore, it is possible to implement current checking in case of zero-sequence and negative-sequence currents via Binary setting HV1 3I0/3I2
Check On, MV1 3I0/3I2 Check On. If setting 1-On is applied at these Binary settings, zero-sequence and negative-sequence currents are calculated
and 3I0 = IA + IB + IC compared with user-defined settings. Corresponding
settings include HV 3I0_CBF ZS and MV 3I0_CBF ZS for zero-sequence
current, and HV 3I2_CBF NS and MV 3I2_CBF NS for negative-sequence
current.
For protection functions where the tripping criterion is not dependent on current, current flow is not a suitable criterion for proper operation of the breaker.
In this case, the position of the circuit breaker auxiliary contact should be
used to determine if the circuit breaker properly operated. It is possible to
evaluate the circuit breaker operation from its auxiliary contact status. To do
so, Binary settings HV1 CB Status Check On or MV CB Status Check On
160

should be set to 1-On to integrate circuit breaker auxiliary contacts into CBF
function..
It should be noted that evaluation of circuit breaker auxiliary contacts is carried out in CBF function only when the current flow monitoring has not picked
up. Once the current flow criterion has picked up during the running time of
CBF timers, the circuit breaker is assumed to be open as soon as the current
disappears, even if the associated auxiliary contacts dont indicate that the
circuit breaker has opened. This gives preference to the more reliable current
criterion and avoids over functioning due to a defect e.g. in the auxiliary contact mechanism or circuit.
Logic diagram
BI_HV1 CB EXT.INT
Inter 3Ph Init CBF
O
R
Init HV CBF
Figure 54 Internal and external initiation
161
Ia > HV1 I_CBF OC

HV 3I0/3I2 Check Off
3I0 > HV1 3I0_CBF ZS
3I2 > HV1 3I2_CBF NS
Ib >HV1 I_CBF OC
A
N
D
O
R
O
R
Curr. Crit. A
HV 3I0/3I2 Check On
Ic > HV1 I_CBF OC
Ib >HV1 I_CBF OC
Ic > HV1 I_CBF OC
A
N
D
O
R
HV 3I0/3I2 Check On
O
R
Curr. Crit. B
O
R
Curr. Crit. C
Ia >HV1 I_CBF OC
Ic >HV1 I_CBF OC
Ib > HV1 I_CBF OC
A
N
D
O
R
HV 3I0/3I2 Check On
Ia > HV1 I_CBF OC
O
R
Curr. Crit
Figure 55 Circuit breaker auxiliary contact evaluation
BI_HV1 CB Open A
A
N
D
BI_HV1 CB Open B
BI_HV1 CB Open C
Init HV CBF
Curr. Crit
O
R
A
N
D
A
N
D
Figure 56 The logic for CB close
162
CB is closed

CB is closed
CB Status Check On
Curr. crit.
O
R
A
N
D
Func_CBF on
T1_CBF
CBF stg1
T2_CBF
CBF stg2
Init HV CBF
Figure 57 The logic for CBF protection

Circuit Breaker
Failure Proteciton
IA
CBF Stage 1 Trip
IB
CBF Stage 2 Trip
IC
Relay Startup
CB Pole A Open
CB Pole B Open
CB Pole C Open
EXT. INT CBF
Figure 58 Circuit breaker protection module

Signal
Description
IA
Phase A current input
IB
Phase B current input
IC
Phase C current input
Table 106 Binary intput list
Signal
Description
CB Pole A Open
Circuit breaker(CB) pole A is open
163
Signal
Description
CB Pole B Open
CB Pole COpen
EXT.INT CBF
initiate the CBF protection by external protection
Signal
Description
CBF Stage1 Trip
CBF protection stage 1 trip
CBF Stage2 Trip
CBF protection stage 1 trip
Relay Startup
Relay Startup
Setting
Table 108 Settings of CBF protection for HV side of transformer
Setting
HV I_CBF
OC
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
(Ir:5A/1A)
Phase current setting value for
0.05Ir
20Ir
HVcircuit breaker failure (CBF)

protection
Negative sequence (NS) cur-
HV
3I2_CBF
Description
0.05Ir
20Ir
NS
rent setting 3I 2 value for HV

CBF protection
Zero sequence (ZS) current
HV
3I0_CBF ZS
0.05Ir
20Ir
setting 3I 0 value for HV1

CBF protection
HV T1_CBF
32
10
HV T2_CBF
0.1
32
10
164
Time setting value of Stage 1,

for HV CBF protection
for HV CBF protection

Table 109 Binary settings of CBF protection for HV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
HV Circuit breaker failure
HV Func_CBF
(CBF) protection is switched

ON
1-on; 0-off.
HV CBF protection detect
HV 3I0/3I2 Check
On
negative or zero sequence

current 3I0 or 3I2.
1-Detect; 0- Not Detect
HV CBF protection detect HV1
HV CB Status
Check On
CB status
Table 110 Settings of CBF protection for MV side of transformer
Setting
MVI_CBF
OC
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.05Ir
20Ir
Default
setting
Description
(Ir:5A/1A)
5

MV CBF protection
MV
3I2_CBF
0.05Ir
20Ir
NS
rent setting 3I 2 value for MV

CBF protection
MV
3I0_CBF ZS
0.05Ir
20Ir
setting 3I 0 value for MV CBF

protection
MV T1_CBF
32
10
MV T2_CBF
0.1
32
10

for MV CBF protection
Table 111 Binary settings of CBF protection for MV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
165

MV Circuit breaker failure
MV Func_CBF

ON
1-on; 0-off.
MV CBF protection detect
MV 3I0/3I2 Check
On

current 3I0 or 3I2.
MV CBF protection detect MV
MV CB Status
Check On
CB status
Table 112 Settings of CBF protection for LV side of transformer
Setting
Unit
LV I_CBF
OC
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.05Ir
20Ir
Default
setting
Description
(Ir:5A/1A)

LV CBF protection
LV 3I2_CBF
NS
0.05Ir
20Ir
rent setting 3I 2 value for LV

CBF protection
LV 3I0_CBF
ZS
0.05Ir
20Ir
setting 3I 0 value for LV CBF

protection
LV T1_CBF
32
10
LV T2_CBF
0.1
32
10

for LV CBF protection
Table 113 Binary settings of CBF protection for LV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
LV Circuit breaker failure (CBF)
LV Func_CBF
1-on; 0-off.
LV 3I0/3I2 Check
On
166
LV CBF protection detect neg0
ative or zero sequence current

3I0 or 3I2.

LV CB Status
Check On
LV CBF protection detect LV

0
CB status
Report
Information
Description
HV CBF1 Trip
HV circuit breaker failure protection stage 1 trip
HV CBF2 Trip
HV CBF Init
Internal or external initiate HV circuit breaker failure protection
MV CBF1 Trip
MV circuit breaker failure protection stage 1 trip
MV CBF2 Trip
MV CBF Init
Internal or external initiate MV circuit breaker failure protection
LV CBF1 Trip
LV circuit breaker failure protection stage 1 trip
LV CBF2 Trip
LV CBF Init
Internal or external initiate LV circuit breaker failure protection

Description of event
comment
HV Func_CBF On
HV circuit breaker failure protection is switched ON (by CW)
HV Func_CBF Off
HV circuit breaker failure protection is switched OFF (by CW)
MV Func_CBF On
MV circuit breaker failure protection is switched ON (by CW)
MV Func_CBF Off
MV circuit breaker failure protection is switched OFF (by CW)
LV Func_CBF On
LV circuit breaker failure protection is switched ON (by CW)
LV Func_CBF Off
LV circuit breaker failure protection is switched OFF (by CW)
Technical data
Item
phase current
Rang or Value
Tolerance
0.08 Ir to 20.00 Ir
0.00s to 32.00 s, step 0.01s
1% setting or +25 ms, at
Negative sequence current

zero sequence current
Time delay of stage 1
167

Time delay of stage 2
0.00s to 32.00 s, step 0.01s
Reset ratio
>0.95
Reset time
< 25ms
168
Chapter 13 Dead zone protection
About this chapter

signals, parameter, IED report and technical data used for dead
zone (short zone) protection function.
169
Introduction
The IED provides this protection function to protect dead zone, namely the
area between circuit breaker and CT in the case that CB is open. Therefore,
by occurrence of a fault in dead zone, the short circuit current is measured by
protection relay while CB auxiliary contacts indicate the CB is open.
Internal/ external initiation
Self-adaptive for bus side CT or line side CT
When one bus side CT of feeder is applied, once a fault occurs in the dead
zone, the IED trips the relevant busbar zone. Tripping logic is illustrated in
below figure.
In the case of feeders with bus side CTs, once a fault occurs in the dead zone,
the IED trips the relevant busbar zone CBs. Tripping concept is illustrated in
the below figure.
trip
Trip
Bus1
Bus1
IFAULT
IFAULT
T1
Ln
Ln
L1
L1
T1
Bus2
Bus2
Bus3
Bus3
Legend:
Legend:
Opened CB
Opened CB
Closed CB
Closed CB
Figure 59 Tripping logic for applying bus side CT and for applying line side CT
170

2.1
Function description
Internal/external initiation
Self-adaptive for bus side CT or line side CT. For bus side CTs, the dead
zone protection will select to trip breakers on other lines connected to the
same busbar. For line side CTs, the dead zone protection will select trip opposite side breakers on the same line.
Logic diagram
Func_HV CBF On
Init HV CBF
A
N
D
Curr. Crit.
BI_HV PhA CB Open
BI_HV PhB CB Open
BI_HV PhC CB Open
A
N
D
Func_Dead Zone On
T_Dead Zone
Dead Zone Trip
A
N
D
BI_HV 3Ph CB Close
Figure 60 Dead zone protection logic
171

Dear Zone
Protection
IA
DZ Trip
IB
Relay Startup
IC
CB Pole A Open
CB Pole B Open
CB Pole C Open
CB 3 Poles Close
Figure 61 Dead zone protection module

Signal
Description
IA
IB
IC
Table 117 Binary input list
Signal
Description
CB Pole A Open
CB Pole B Open
Circuit breaker(CB) pole B is open
CB Pole C Open
Circuit breaker(CB) pole C is open
CB 3 Poles Close
3 poles of circuit breaker(CB) is close
Signal
Description
DZ Trip
dead zone protection trip
Relay Startup
Relay Startup
172
Setting
Table 119 Dead zone protection function setting list for HV side of transformer
Setting
HV T_Dead Zone
Unit
Default
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
32
setting
Description
(Ir:5A/1A)
10
Time delay setting for HV

dead zone protection
Table 120 Dead zone protection binary setting list for HV side of transformer
Setting
Unit
Min.
Default
Max.
setting
Description
Dead zone protection is switched
HV Func_Dead
Zone
ON
1-on; 0-off.
Table 121 Dead zone protection function setting list for MV side of transformer
Setting
MV T_Dead Zone
Unit
Default
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
32
setting
Description
(Ir:5A/1A)
10
Time delay setting for MV

Table 122 Dead zone protection binary setting list for MV side of transformer
Setting
Unit
Min.
Max.
Default
setting
Description
Dead zone protection is switched
MV Func_Dead
Zone
ON
1-on; 0-off.
Table 123 Dead zone protection function setting list for LV side of transformer
Setting
LV T_Dead Zone
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
32
Default
setting
Description
(Ir:5A/1A)
10
Time delay setting for LV

173

Table 124 Dead zone protection binary setting list for LV side of transformer
Setting
Unit
LV Func_Dead Zone
Min.
Max.
Default
setting
Description
Dead zone protection is switched ON
1-on; 0-off.
Report
Information
Description
HV Dead Zone
HV Dead zone trip
MV Dead Zone
MV Dead zone trip
LV Dead Zone
LV Dead zone trip

Information
Description
HV Func_DZ On
HV DZ function on
HV Func_DZ Off
HV DZ function off
MV Func_DZ On
MV DZ function on
MV Func_DZ Off
MV DZ function off
LV Func_DZ On
LV DZ function on
LV Func_DZ Off
LV DZ function off
Technical data
NOTE:
Ir: CT rated secondary current, 1A or 5A;
Item
Rang or Value
Tolerance
Current
0.08 Ir to 20.00 Ir
Time delay
0.00s to 32.00s, step 0.01s

Reset ratio
174
>0.95
Chapter 14 STUB protection
About this chapter

signals, parameter, IED report and technical data used for STUB
175
Introduction
The STUB protection protects the zone between the CTs and the open disconnector. The STUB protection is enabled when the open position of the
disconnector is informed to the IED through connected binary input. The
function supports one definite stage with the logic shown inbelow figure.
2.1
Busbar A
CT1-1
CB1
CT1-2
Fault
Feeder1
Feeder 1 Disconnector
CT3-1
CB3
CT3-2
Feeder2
Feeder 2 Disconnector
CT2-1
CB2
CT2-2
Busbar B
Figure 62 STUB fault at circuit breaker arrangement

If IED detects short circuit current flowing while the line disconnector is open,
STUB fault is detected for the short circuit in the area between the current
transformers and the line disconnector. Here, the summation of CT1 and CT3
presents the short circuit current.
176

The STUB protection is an overcurrent protection which is only in service if
the status of the line disconnector indicates the open condition. The binary
input must therefore be informed via an auxiliary contact of the disconnector.
In the case of a closed line disconnector, the STUB protection is out of service. The STUB protection stage provides one definite time overcurrent stage
with settable delay time. This protection function can be enabled or disabled
via the binary setting Func_STUB. Corresponding current setting value can
be inserted in I_STUB setting. The IED generate trip command whenever
the time setting T_STUB is elapsed.
Logic diagram
Ia>I_STUB
O
R
Ib>I_STUB
Ic>I_STUB
A
N
D
Func_STUB on
BI_STUB Enable
T_STUB
Permanent trip
Figure 63 Logic diagram for STUB protection

STUB Protection
IA1
STUB Trip
IB1
Relay Startup
IC1
IA2
IB2
IC2
HV STUB Enable
Figure 64 STUB protection module
177

Signal
Description
IA1
IB1
IC1
IA2
IB2
IC2
Signal
Description
Feeder disconnector is open, to enable the
HV STUB Enable
STUB protection
Signal
Description
STUB Trip
STUB Trip
Relay Startup
Relay Startup
Setting
Table 130 Setting value list for STUB protection for HV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
(Ir:5A/1A)
HV I_STUB
0.05Ir
20Ir
100
HV T_STUB
60
60
178
Description
current threshold of STUB
protection
delay time of STUB protection

Table 131 Binary setting list for STUB protection for HV side of transformer
Setting
Unit
HV Func_STUB
Min.
Max.
Default
setting
0
HV STUB Init LV
Description
Enable or disable STUB
protection
STUB protection initiate
CBF
LV side CBF
HV STUB Init MV
CBF
HV side CBF
Table 132 Setting value list for STUB protection for MV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
MV I_STUB
0.05Ir
20Ir
100
MV T_STUB
60
60

protection
Table 133 Binary setting list for STUB protection for MV side of transformer
Setting
Unit
MV Func_STUB
Min.
Max.
Default
setting
0
MV STUB Init LV
Description
protection
CBF
LV side CBF
MV STUB Init MV
CBF
MV side CBF
Table 134 Setting value list for STUB protection for LV side of transformer
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
LV I_STUB
0.05Ir
20Ir
100
LV T_STUB
60
60

protection
179

Table 135 Binary setting list for STUB protection for LV side of transformer
Setting
Unit
LV Func_STUB
Min.
Max.
Default
setting
0
LV STUB Init LV
Description
protection
CBF
LV side CBF
LV STUB Init MV
CBF
LV side CBF
Report
Information
Description
HV STUB Trip
HV STUB protection trip
MV STUB Trip
MV STUB protection trip
LV STUB Trip
LV STUB protection trip

Information
Description
HV Func_STUB On
HV STUB function on
HV Func_STUB Off
HV STUB function Off
MV Func_STUB On
MV STUB function on
MV Func_STUB Off
MV STUB function Off
LV Func_STUB On
LV STUB function on
LV Func_STUB Off
LV STUB function Off
180
Technical data
NOTE:
Table 138 Technical data for STUB protection
Item
Rang or Value
Tolerance
Current
0.08 Ir to 20.00 Ir
Time delay
0.00s to 60.00s, step 0.01s

Reset ratio
>0.95
181
182
Chapter 15 Poles discordance protection
Chapter 15 Poles discordance

protection
About this chapter

signals, parameter, IED report and technical data for poles discordance protection.
183
Introdcution
Under normal operating condition, all three poles of the circuit breaker must
be closed or open at the same time. The phase separated operating circuit
breakers can be in different positions (close-open) due to electrical or mechanical failures. This can cause negative and zero sequence currents which
gives thermal stress on rotating machines and can cause unwanted operation
of zero sequence or negative sequence current functions.
Single pole opening of the circuit breaker is permitted only in the short period
related to single pole dead times, otherwise the breaker is tripped three pole
to resolve the problem. If the problem still remains, the remote end can be
intertripped via circuit breaker failure protection function to clear the unsymmetrical load situation.
The pole discordance function operates based on information from auxiliary
contacts of the circuit breaker for the three phases with additional criteria from
unsymmetrical phase current.
2.1
The CB position signals are connected to IED via binary input in order to
monitor the CB status. Poles discordance condition is established when binary setting HV Func_PD for HV said, or MV Func_PD for MV said is set
to 1/on, and at least one pole is open and at the same time not all three
poles are closed. The auxiliary contacts of the circuit breakers are checked
with corresponding phase currents for plausibility check. Error alarm CB Err
Blk PD is reported after 5 sec whenever CB auxiliary contacts indicate that
one pole is open but at the same time current is flowing through the pole.
Additionally the function can be informed via binary setting HV PD Chk
3I0/3I2 and MV PD Chk 3I0/3I2for additionaly zero and negative sequence
current as well as current criteria involved in CBF protection. Pole discordance can be detected when current is not flowing through all three poles.
When current is flowing through all three poles, all three poles must be closed
even if the breaker auxiliary contacts indicate a different status.
184
Logic diagram
BI_CB Open A
Ia > 0.06Ir
BI_CB Open B
Ib > 0.06Ir
BI_CB Open C
Ic > 0.06Ir
A
N
D
A
N
D
O
R
A
N
D
A
N
D
5s
CB Err Blk PD
BI_CB Open A
BI_CB Open B
BI_CB Open C
BI_CB Open A
Ia < 0.06Ir
BI_CB Open B
Ib < 0.06Ir
BI_CB Open C
Ic< 0.06Ir
3I2 > 3I2_PD

3I0 >3I0_PD
A
N
D
A
N
D
A
N
D
Curr. Crit. C
T_PD
O
R
PD Trip
A
N
D
O
R
Curr. Crit. A
Curr. Crit. B
Func_PD On
A
N
D
A
N
D
A
N
D
1
PD Chk 3I0/3I2 on
PD Chk 3I0/3I2 off
Figure 65 Logic diagram for poles discordance protection
185

Pole Discordance
Protection
IA
PD Trip
IB
Relay Startup
IC
INBK
CB Pole A Open
CB Pole B Open
CB Pole C Open
Figure 66 Poles discordance protection module

Signal
Description
IA
IB
IC
INBK
Neutral current input

Signal
Description
CB Pole A Open
CB Pole B Open
CB Pole C Open

Circuit breaker(CB) pole B is open
Circuit breaker(CB) pole C is open

Signal
Description
PD Trip
Relay Startup
PD Trip
Relay Startup
186
Setting
Table 142 Function setting list for poles discordance protection for HV side of
tranformer
Setting
Default
setting
Unit
Min.
Max.
HV 3I0_PD
0.05Ir
20Ir
HV 3I2_PD
0.05Ir
20Ir
HV T_PD
60
Description
zero sequence current threshold
of pole discordance protection
negative sequence current
threshold of pole discordance
protection
delay time of pole discordance
protection
10
Table 143 Binary setting list for poles discordance protection for HV side of
tranformer
Min.
Max.
Default
setting
MV Func_PD
MV PD Chk
3I0/3I2
Setting
Unit
Description
Enable or disable MV poles
discordance protection
Enable or disable 3I0/3I2
criteria
Table 144 Function setting list for poles discordance protection for MV side of
tranformer
Setting
Default
setting
Unit
Min.
Max.
MV 3I0_PD
0.05Ir
20Ir
MV 3I2_PD
0.05Ir
20Ir
MV T_PD
60
Description
zero sequence current threshold
of pole discordance protection
negative sequence current
threshold of pole discordance
protection
delay time of pole discordance
protection
10
Table 145 Binary setting list for poles discordance protection for MV side of
tranformer
Min.
Max.
Default
setting
MV Func_PD
MV PD Chk
3I0/3I2
Setting
Unit
Description
criteria
187
Report
Information
Description
HV PD Trip
MV PD Trip
HV poles discordance protection trip

MV poles discordance protection trip

Information
Description
CB Err Blk PD
Circuit breaker error block poles discordance protection

Information
HV Func_PD On
HV Func_PD Off
MV Func_PD On
MV Func_PD Off
Description
HV poles discordance function on
HV poles discordance function off
MV poles discordance function on
MV poles discordance function off
Technical data
NOTE:
Table 149 Technical data for pole discordance
Item
Rang or Value
Tolerance
Current
0.08 Ir to 20.00 Ir
Time delay
0.00s to 60.00s, step 0.01s

Reset ratio
>0.95
188
Chapter 16 Distance protection
About this chapter

signals, parameter, IED report and technical data for poles discordance protection.
189
Introdcution
Sub-transmission networks are being extended and often become more and
more complex, consisting of a high number of multi-circuit and/or multi terminal lines of very different lengths. These changes in the network will normally impose more stringent demands on the fault clearing equipment in order to maintain an unchanged or increased security level of the power system.
The distance protection function in the IED is designed to meet basic requirements for application on transformer and transmission lines.
2.1
Phase-to-phase distance protection has two settable distance stages; in addition, every stage can be switched over via binary setting and every stage
with 1 timer delay setting. Phase-to-phase distance calculations are based on
the three phase-to-phase voltages and phase-to-phase currents. The formula
is as follows:
U A U B
Z AB =
I A I B
U B U C
Z BC =
I B IC
Z CA = U C U A
IC I A
Where ZAB, ZBC, ZCA: phase-to-phase distance

Phase-to-earth distance protection has one settable distance stage, with 1
timer delay setting. The formula for calculation phase-to-earth distance is as
follow:
Z =
I + K 3I0
Where U - Phase voltage ( = A, B, C )

I - Phase current ( = A, B, C )
K - Zero sequence current compensation factors
In order to avoiding the mal-operation of the distance protection, it is blocked

when VT fuse failure occurs. Both distance characteristics are round.
190
X
XZNZ
XZ
RZ
RZNZ
RZNZ
RZ
XZNZ
a) Direction to transformer
XZ
b) Direction to system
Figure 67 Tripping characteristics of distance protection

The positive direction for distance protection can be switched over via binary
setting. For example, for phase-to-phase distance, if binary setting DIS_1
DIR TO SYS is set 1, it means direction for 1st stage phase-to-phase distance is to system; and setting is set 0, it means direction to transformer. It is
same to phase to earth distance.
2.2
Auxiliary startup element

In order to avoid unwanted operation of distance protection and to insure
correct operation when phase-to-phase fault and phase-to-earth fault occur.
Auxiliary startup elements including negative current element and abrupt
current element are adopted.
Auxiliary abrupt current startup element

When all kinds of faults occur in the protected section, current in HV or MV
side will be abrupt change. Abrupt current startup element is adopted in distance protection; the formula is as follows:
i > 0.2 I N
i = i (t ) i (t n) + 2i (t 2n)
Where i - abrupt current startup element
Auxiliary negative current startup element

When all kinds of faults occur in the protected section, current in HV or MV
side will be abrupt change. Abrupt current startup element is adopted in distance protection; the formula is as follows:
i > 0.2 I N
i = i (t ) i (t n) + 2i (t 2n)
191

Where i - abrupt current startup element
Auxiliary negative current startup element

When the imbalance fault occurs in the protected section, negative current
occurs at the same time. Using negative current is helpful to detect the imbalance faults. the formula is as follows:
I 2 > 0.2 I ie ( i = h, m )
(5-12)
Where I ie - rated current of HV or MV side.

Phase-to-phase distance and phase-to-earth distance have same logic.
Logic diagram
The typical logic of 1 stage of distance protection is shown in below figure.
DIS ON
I2>0.2Ie
>=1
Di > 0.2 I N
&
Distance Point
inside the Circle
VT failure
Figure 68 Tripping logic for distance protection

Distance Protection
IA1
IB1
IC1
IA2
HV DIS(Ph-N)Trip
HV DIS_1 Trip
HV DIS_2 Trip
Relay Startup
IB2
IC2
UA
UB
UC
Figure 69 Distance protection module
192
DIS Trip

Signal
Description
IA1
Phase A current input of CT of circuit breaker

1
Phase B current input of CT of circuit breaker
1
Phase C current input of CT of circuit breaker
1
Phase A current input of CT of circuit breaker
2
Phase B current input of CT of circuit breaker
2
Phase C current input of CT of circuit breaker
2
Phase A voltage input of VT of related winding
of transformer
Phase B voltage input of VT of related winding of transformer
Phase C voltage input of VT of related winding of transformer
IB1
IC1
IA2
IB2
IC2
UA
UB
UC

Signal
Description
Phase to Earth Distance (DIS Ph-N) tripping
in HV side
Phase to phase Distance (DIS) prot. Stage
1(_1) or Stage 2 (_2) tripping in HV side with
time delay T
Relay Startup
HV DIS(Ph-N)Trip
HV DIS_1 Trip
HV DIS_2 Trip
Relay Startup
Setting
Table 152 Function setting list for distance protection for HV side of tranformer
Setting Title
Setting
options
Default
setting
Comment
Phase-to-earth distance(DIS PH-N) setting X
Phase-to-earth distance(DIS PH-N) setting R
HV DIS PH-N X
0.1..125
10
HV DIS PH-N R
0.1..125
HV DIS OFFSET
RATIO
0.0..1.00
Offset ratio to setting
HV K FACTOR
0.0..99.0
zero sequence compensation coefficient
T HV DIS PH-N
0.1..20.0s
Timer setting for DIS PH-N
HV DIS1 PH-PH X1
0.1..125
10
HV DIS1 PH-PH R1
0.1..125
1st stage Phase-to-phase distance(DIS1) setting X

1st stage Phase-to-phase distance(DIS1) setting
193

8
9
10
11
12
13
HV DIS1 OFFSET
RATIO
0.0..1.00
Offset ratio to setting of 1st stage DIS1
T HV DIS1 PH-PH
0.1..20.0s
Timer setting for 1st stage DIS1
HV DIS2 PH-PH X2
0.1..125
10
HV DIS2 PH-PH R2
0.1..125
HV DIS2 OFFSET
RATIO
0.0..1.00
Offset ratio to setting of 2nd stage DIS2
T HV DIS2 PH-PH
0.1..20.0s
Timer setting for 2nd stage DIS2
2nd stage Phase-to-phase distance(DIS2) setting X

2nd stage Phase-to-phase distance(DIS2) setting
Table 153 Binary setting list for distance protection for HV side of tranformer
No
Setting Title
Setting
options
Default
setting
HV DIS PH-N ON
0/1
HV DIS PH-N DIR

TO SYS
0/1
HV DIS1 PH-PH
ON
0/1
HV DIS1 PH-PH
DIR TO SYS
0/1
HV DIS2 PH-PH
ON
0/1
HV DIS2 PH-PH
DIR TO SYS
0/1
Comment
Phase to earth distance(DIS PH-N) in
HV side on.
Phase to earth Distance (DIS PH-N)
direction(DIR) to system(SYS) in HV
side
1st stage phase to phase distance
(DIS1) in HV side on
1st stage Phase to phase Distance
(DIS1) direction(DIR) to system(SYS) in
HV side
2nd stage phase to phase distance
(DIS2) in HV side on
2nd stage Phase to phase Distance
HV side
Table 154 Function setting list for distance protection for MV side of tranformer
No
1
2
3
4
5
6
7
8
194
Setting
options
Default
setting
MV DIS PH-N X
0.1..125
10
MV DIS PH-N R
0.1..125
MV DIS OFFSET
RATIO
0.0..1.00
Offset ratio to setting
MV K FACTOR
0.0..99.0
zero sequence compensation coefficient
T MV DIS PH-N
0.1..20.0s
Timer setting for DIS PH-N
MV DIS1 PH-PH X1
0.1..125
10
MV DIS1 PH-PH R1
0.1..125
MV DIS1 OFFSET
RATIO
0.0..1.00
Setting Title
Comment
Phase-to-earth distance(DIS PH-N)
setting X
Phase-to-earth distance(DIS PH-N)
setting R
1st stage Phase-to-phase distance(DIS) setting X

1st stage Phase-to-phase distance(DIS) setting
Offset ratio to setting of 1st stage DIS1

9
10
11
12
13
T MV DIS1 PH-PH
0.1..20.0s
Timer setting for 1st stage DIS1
MV DIS2 PH-PH X2
0.1..125
10
MV DIS2 PH-PH R2
0.1..125
MV DIS2 OFFSET
RATIO
0.0..1.00
Offset ratio to setting of 2nd stage DIS2
T MV DIS2 PH-PH
0.1..20.0s
Timer setting for 2nd stage DIS2
2nd stage Phase-to-phase distance(DIS2) setting X

2nd stage Phase-to-phase distance(DIS2) setting R
Table 155 Binary setting list for distance protection for MV side of tranformer
NO
1
2
3
4
5
6
Setting Title
MV DIS PH-N
ON
MV DIS PH-N
DIR TO SYS
MV DIS1
PH-PH ON
MV DIS1
PH-PH DIR TO
SYS
MV DIS2
PH-PH ON
MV DIS2
PH-PH DIR TO
SYS
Setting
options
Default
setting
0/1
0/1
0/1
0/1
0/1
0/1
Comment
Phase to earth distance (DIS PH-N) in
MV side on.
Phase to earth Distance (DIS PH-N) direction(DIR) to system(SYS) in MV side
1st stage phase to phase distance (DIS1)
in MV side on
1st stage Phase to phase Distance
MV side
2nd stage phase to phase distance
(DIS2) in MV side on
2nd stage Phase to phase Distance
MV side
Report
Information
Description
HV DIS(Ph-N)Trip
HV DIS_1 Trip
HV DIS_2 Trip
Relay Startup
Phase to Earth Distance (DIS Ph-N) tripping in HV side

Phase to phase Distance (DIS) prot. Stage 1(_1) or Stage 2 (_2)
tripping in HV side with time delay T
Relay Startup

Information
HV Func_Dis On
MV Func_Dis On
HV Func_Dis Off
MV Func_Dis Off
Description
HV distance protection on
MV distance protection on
HV distance protection off
MV distance protection off
195
Technical data
NOTE:
Table 158 Technical data for distance protection
Item
Resistance setting range
Reactance setting range
Time delay of distance zones

Operation time
Dynamic overreaching
196
Rang or Value
0. 125, step 0.01, when
Ir=5A;
0. 5125, step 0.01, when
Ir=1A;
0. 125, step 0.01, when
Ir=5A;
0. 5125, step 0.01, when
Ir=1A;
0.1to 20.00s, step 0.01s
40ms typically at 70% setting of
zone
5%, at 0.5<SIR<30
Tolerance
5.0% static accuracy
Conditions:
Voltage range: 0.01 Ur to 1.2 Ur
Current range: 0.12 Ir to 20 Ir
1% or +20 ms
Chapter 17 Secondary system supervision
Chapter 17 Secondary system

supervision
About this chapter

signals, parameter, IED report and technical data for secondary
system supervision function.
197
VT failure supervision function

In the event of a measured voltage failure due to a broken conductor or a
short circuit fault in the secondary circuit of voltage transformer, those protection functions which work based on voltage criteria may mistakenly see a
voltage of zero. VT failure supervision function is provided to inform those
functions about a voltage failure.
Function principle
VT failure supervision function can be enabled or disabled in each side
through Binary setting HV VT Fail Detect, MV VT Fail Detect and LV VT
Fail Detect. By applying setting 1-On to these Binary settings, respective
VT failure supervision function would monitor the voltage transformer circuit
of corresponding side. Each VT failure supervision function is able to detect
single-phase broken, two-phase broken or three-phase broken faults in respective voltage transformer. There are three main criteria for VT failure detection; from them the first one is dedicated to detect three-phase broken
faults. The second and third one is dedicated to detect single or two-phase
broken faults in solid earthed and isolated/resistance earthed systems, respectively. A precondition to meet these three criteria is that the relay should
not be picked up and the calculated zero sequence and negative sequence
currents should be less than setting of HV 3I02_ VT Fail, MV 3I02_ VT Fail
or LV 3I02_ VT Fail. These criteria are as follows:
The calculated zero sequence voltage 3U0 as well as maximum of three
phase-to-earth voltages of respective side of the protected transformer are
less than the setting of HV Upe_VT Fail, MV Upe_VT Fail or LV Upe_VT
Fail and at the same time, maximum of three phase currents of respective
side is higher than setting of HV I_VT Fail, MV I_VT Fail or LV I_VT Fail.
This condition may correspond to three phase broken fault in secondary circuit of the voltage transformer in respective side of the protected transformer.
The calculated zero sequence voltage 3U0 of respective side of the protected
transformer is more than the setting of HV Upe_VT Fail, MV Upe_VT Fail
or LV Upe_VT Fail. This condition may correspond to single or two-phase
broken fault in secondary circuit of the voltage transformer in respective side
of the protected transformer, if the system starpoint is solidly earthed.
The calculated zero sequence voltage 3U0 of respective side of the protected
transformer is more than the setting of HV Upe_VT Fail, MV Upe_VT Fail
or LV Upe_VT Fail, and at the same time, the difference between the maximum and minimum phase-to-phase voltages of respective side is more than
the setting of HV Upp_VT Fail, MV Upp_VT Fail or LV Upp_VT Fail. This
condition may correspond to single or two-phase broken fault in secondary
circuit of the voltage transformer in respective side of the protected transformer, if the system starpoint is isolated or resistance earthed.
In addition to the mentioned conditions, the device has the capability to be
informed about the VT MCB failure through its binary inputs. These inputs include HV MCB FAIL BI, MV MCB FAIL BI and LV MCB FAIL BI. In this
198

context, VT fail is detected in corresponding side, if the respective binary inputs are active.
If VT failure supervision detects a failure in voltage transformer secondary
circuit, either by means of the above mentioned criteria or reception of a VT
MCB fail indication, all the protection functions which operate based on direction determination would be blocked in corresponding side of the protected
transformer, depending on the setting. Furthermore, an alarm report of HV
VT Fail, MV VT Fail or LV VT Fail, is issued after 10s delay time. The
blocking condition would be removed if one of the following conditions is met
within the 10s delay time.
Minimum phase voltage of corresponding side of the protected transformer
becomes more than setting of HV Upe_VT Normal, MV Upe_VT Normal or
LV Upe_VT Normal for 500ms.
Minimum phase voltage of corresponding side becomes more than setting of
HV Upe_VT Normal, MV Upe_VT Normal or LV Upe_VT Normal and at
the same time, the calculated zero sequence and negative sequence current
of corresponding side becomes more than the setting of HV 3I02_VT Fail,
MV 3I02_VT Fail or LV 3I02_VT Fail.
Subsequent to reporting VT fail alarm, the blocking condition of respective
protection functions would be removed if the minimum phase voltage of corresponding side becomes more than the setting of HV Upe_VT Normal, MV
Upe_VT Normal or LV Upe_VT Normal for a duration more than 10s.
Below figure shows logic diagram of VT failure supervision as it is implemented in the IED.
199
Max(Ia,Ib,Ic) > I_ VT Fail

A
N
D
Max{Ua,Ub,Uc} < Upe_VT Fail

3U0 < Upe_VT Fail-1
Solid Earth on
O
R
3U0 >= Upe_VT Fail-1)

Solid Earth off
A
N
D
A
N
D
Max{Uab,Ubc,Uca} - Min{Uab,Ubc,Uca}
> Upp_VT Fail
A
N
D
Relay Pickup
O
R
BI MCB Fail
A
N
D
HV VT Fail Detect on
1
VT Fail Detected
VT Fail Detected
Min{Ua,Ub,Uc} > Upe_VT Normal
A
N
D
A
N
D
500ms
3I0 > 3I02_VT Fail or

3I2 > 3I02_VT Fail
A
N
D
min{Ua,Ub,Uc} > Upe_VT Normal
A
N
D
O
R
A
N
D
No VT Fail
10s
Figure 70 Logic of VT Failure supervision
200
10s
Alarm report

VT Secondary
Circuit Supervision
IA1
VT Failure
IB1
Relay Startup
IC1
IA2
IB2
IC2
UA
UB
UC
V3P MCB Fail
Figure 71 VT Failure supervision module

Signal
Description
IA1
IB1
IC1
IA2
IB2
IC2
UA
UB
UC


Signal
Description
V3P MCB Fail
VT failure informed by BI

Signal
Description
VT Failure
Relay Startup
VT Failure
Relay Startup
201
Setting
Table 162 Settings of VT failure supervision for HV side of transformer
Default
setting
Setting Title
Unit
HV I_VT Fail
0.05Ir
0.2Ir
0.05
HV 3I02_ VT Fail
0.05Ir
0.2Ir
0.5
HV Upe_VT Fail
20
HV Upp_VT Fail
10
30
16
HV Upe_VT
Normal
40
65
40
Min.
Max.
Comment
Minimum Current of VT failure
for HV side
Minimum zero or negative Current of HV VT fail
Maximum phase to earth voltage
of HV VT fail
Maximum phase to phase voltage of HV VT fail
Minimum phase to phase voltage of HV VT normal
Table 163 Binary settings of VT failure supervision for HV side of transformer

Min.
Max.
Default
HV VT FAIL Detect
HV Solid Earth
Setting Title
Unit
Comment
HV VT Failure Detection On/Off
1-On, 0-Off.
HV Earthing mode:
1: Solid earthed system ;
0: isolated system or resistance
earthed.
Table 164 Settings of VT failure supervision for MV side of transformer

Setting Title
Unit
Min.
Max.
Default
setting
MV I_VT Fail
0.05Ir
0.2Ir
0.05
MV 3I02_VT Fail
0.05Ir
0.2Ir
0.5
MV Upe_VT Fail
20
MV Upp_VT Fail
10
30
16
MV Upe_VT
Normal
40
65
40
Comment
for MV side
Minimum zero or negative Current of MV VT fail
of MV VT fail
Maximum phase to phase voltage of MV VT fail
Minimum phase to phase voltage of MV VT normal
Table 165 Binary settings of VT failure supervision for MV side of transformer

Setting Title
MV VT FAIL Detect
MV Solid Earth
202
Unit
Comment
Max.
Min.
Default
MV VT Failure Detection
On/Off
1-On, 0-Off.
MV Earthing mode:
0: isolated system or resistance earthed.

Table 166 Settings of VT failure supervision for LV side of transformer
Default
setting
Setting Title
Unit
LV I_VT Fail
0.05Ir
0.2Ir
0.05
LV 3I02_VT Fail
0.05Ir
0.2Ir
0.5
LV Upe_VT Fail
20
LV Upp_VT Fail
10
30
16
LV Upe_VT
Normal
40
65
40
Min.
Max.
Comment
for LV side
Minimum zero or negative Current of LV VT fail
of LV VT fail
Maximum phase to phase voltage of LV VT fail
Minimum phase to phase voltage of LV VT normal
Table 167 Binary settings of VT failure supervision for LV side of transformer

Min.
Max.
Default
LV VT FAIL Detect
LV Solid Earth
Setting Title
Unit
Comment
LV VT Failure Detection
On/Off
1-On, 0-Off.
LV Earthing mode:
0: isolated system or
resistance earthed.
Report
Information
Description
HV VT Fail
MV VT Fail
LV VT Fail
HV VT Fail alarm
MV VT Fail alarm
LV VT Fail alarm

Information
HV Func_VT On
HV Func_VT Off
MV Func_VT On
MV Func_VT Off
LV Func_VT On
LV Func_VT Off
Description
HV VT failure supervision function on
HV VT failure supervision function off
MV VT failure supervision function on
MV VT failure supervision function off
LV VT failure supervision function on
LV VT failure supervision function off
203
Technical data
Item
Minimum current
Minimum zero or negative sequence current
Maximum phase to phase voltage
Normal phase to earth voltage
204
Range or value
0.08Ir to 0.20Ir, step 0.01A
0.08Ir to 0.20Ir, step 0.01A
Tolerances
7.0V to 20.0V, step 0.01V

10.0V to 30.0V, step 0.01V
3% setting or 1 V
3% setting or 1 V
40.0V to 65.0V, step 0.01V
3% setting or 1 V
Chapter 18 External Bis to trip BOs
Chapter 18 External BIs to trip BOs
About this chapter

signals, parameter, IED report and technical data for external BIs
to trip BOs function.
205
Introduction
Two special binary inputs (BI_Config1, BI_Config2) are provided which can
be used to activate respective binary outputs (BO1 and BO2), according to
the setting applied at Binary settings BI1 Enable BO1 and BI2 Enable BO2.
By applying setting 1-enable to these Binary settings, BO1 will be activated
if BI1 is energized. Similarly, BO2 will be activated if BI2 is energized.
Function principle
The external BIs can be used in conjunction with the mechanical protections
of the protected transformer (such as Buchholz, Winding temperature, and so
on). In this context, trip commands of the main and backup mechanical protections can be marshaled to BI1 and BI2, respectively. By doing so, the
output trip commands would be provided at BO1 and BO2 respectively.
Since the trip command of mechanical protection has latched nature, two
operating modes are provided for the BOs activation. The operating modes
include direct and pulse tripping modes. In direct tripping mode, each BO
contact is active as long as respective BI is energized, and after BI disappearance 20ms the BO contacts are deactivated. Whereas in pulse tripping
mode, by each up-edge of BI, respective BO contacts remain active during a
settable pulse time, and after the settable time, the BO contacts are inactive.
The tripping modes can be selected for the BOs by Binary settings BO1
Pulse Tripping and BO2 Pulse Tripping. Pulse tripping mode would be
possible if setting 1-Pulse Tripping is applied to the Binary settings. Similarly,
setting 0-Direct Tripping activates direct tripping mode for respective BOs.
The logic is shown in below figure.
BI Enable BO on
1
0
A
N
D
BIx up edge
Pulse Tripping Time

1
A
N
D
0
BI trip BO
20ms
BO Pulse Tripping
1
0
A
N
D
1
0
BI trip BO
A
N
D
Figure 72 Logic of external BIs to trip Bos
Furthermore, it is possible to set BIs to initiate CBF protection in HV, MV or LV

206

sides of protected transformer via a number of Binary settings. The Binary
settings include BI1 Init HV CBF, BI1 Init MV CBF and BI1 Init LV CBF on
for the first BI. Similarly, Binary settings BI2 Init HV CBF, BI2 Init MV CBF
and BI2 Init LV CBF correspond to the second BI.
BI Trigger Record
In the IED, it is possible for Binary inputs (BIs) to trigger disturbance record
(DR). The exceptions are Switch SetGroup, Blk Rem Access, Relay Test
and Reset. In this context, each Binary input can be set independently
whether it can trigger DR or not. Further, it is possible to set whether BI triggers DR in its up or down edge. Example logic of BI HV CB Open Status
triggering DR is given in below figure. The same logic is applied for the other
BIs.
BI HV CB Open Status
Change from 1to 0
Equipment parameter
HV CB OPEN STATUS DOWN = 1
(meaning DOWN edge)
A
N
D
O
R
BIHV CB OPEN STATUS ENABLE=1
BI HV CB Open Status
Change from 0to 1
Equipment parameter
HV CB OPEN STATUS DOWN = 0
(meaning UP edge)
Trigger
Record
A
N
D
Figure 73 Logic of BI trigger record
207
BI Switch SetGroup
BI Switch SetGroup is used to switch setting group of the device. Both BI
SetGrp Switchand Normal Set Switch are selected by making change in the
content of special Binary setting BI SetGrp Switch which can be set under
Common Para submenu. When the Binary setting is set to 1, BI setting
group switch mode is applied, on the contrary, Normal setting group switch
mode (shortcut key or operate through the menu) is applied. For BI SetGrp
Switch mode, When BI Switch SetGroup is deactivated, the content of Binary setting BI SetGrp Switch is set to 0 and it means that no switching in
setting groups is desired. In this case, Group 1 is applied to the device. When
the BI is activated, the content of Binary setting BI SetGrp Switch is set to 1
and it means that BI SetGrp Switch mode is applied. Thus, the current setting-value would automatically be switched to Group 2. For the other switch
mode, whether the BI is activated or not, setting group change is valid for
shortcut key or operate through the menu.
BI Blk Rem Access and RELAY

TEST
There are two methods to block remote access to the device, BI Blk Rem
Access or making change in the content of special Binary setting NOT Blk
Remote Access which can be set under Common Para submenu.
When BI Blk Rem Access is activated, or the content of Binary setting NOT
Blk Remote Access is set to 0, SCADA remote access is blocked to the device and therefore, only local operation is permitted.
When BI Blk Rem Access is deactivated, and the content of Binary setting
NOT Blk Remote Access is set to 1, both SCADA commands and local operation can be executed by the device.
Similarly, there are two methods to select test or normal operating mode of
the device, BI Relay Test or making change in the content of special Binary
setting Relay Test Mode which can be set under Common Para submenu.
When BI Relay Test is activated, or the content of Binary setting Relay Test
Mode is set to 1, the relay is in test mode.
When BI Relay Test is deactivated, and the content of Binary setting Relay
Test Mode is set to 0, the relay is in normal operation mode
208
BI BI_Config1~ BI_Config2 and BI

TRIGGER DR1~ 10
Both BI_Config1~ BI_Config2 and BI Trigger DR1~ BI Trigger DR10 are
binary inputs which can be recorded. BI_Config1~ BI_Config2 can operate to
binary output X10 and X11. The names of these BIs can be modified by
CSPC tools according to actual situation.
Setting
Table 170 Setting of external BIs to trip BOs
Setting
T_Pulse
Tripping
Unit
Default
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.2
setting
Description
(Ir:5A/1A)
5
Table 171 Binary settings of external DIs to trip DOs
Setting Title
BI1 Enable
BO1
Setting
Default
options
setting
Comment
To select whether the 1st binary input (BI1) trip
1/0
st
the 1 binary output (BO1) or not.
1-enable, 0-disable
To select BO1 tripping in pulse mode or in direct
BO1 Pulse
Tripping
1/0
mode
0- BO1 Direct Tripping, without delay
1- BO1 Pulse Tripping, with preset delay time
BI2 Enable
BO2
To select whether the 2nd binary input (BI2) trip

1/0
nd
the 2 binary output (BO2) or not.

1-enable, 0-disable
To select BO2 tripping in pulse mode or in direct
BO2 Pulse
Tripping
1/0
mode
0- BO2 Direct Tripping, without delay
1- BO2 Pulse Tripping, with preset delay time
BI1 Init HV
CBF
BI1 Init MV
CBF
1/0
1/0
whether BI1 initiate HV side CBF or not

whether BI1 initiate MV side CBF or not
209

Setting Title
BI1 Init LV
CBF
BI2 Init HV
CBF
BI2 Init MV
CBF
BI2 Init LV
CBF
210
Setting
Default
options
setting
1/0
1/0
1/0
1/0
Comment
whether BI1 initiate LV side CBF or not
whether BI2 initiate HV side CBF or not
whether BI2 initiate MV side CBF or not
whether BI2 initiate LV side CBF or not
Chapter 19 Station communication
About this chapter

This chapter describes the communication possibilities in a
SA-system.
211
Overview
Each IED is provided with a communication interface, enabling it to connect to
one or many substation level systems or equipment.
The following communication protocols are available:
LON communication protocol
IEC 61850-8-1 communication protocol
60870-5-103 communication protocol
The IED is able to connect to one or more substation level systems or

equipments simultaneously, through the communication ports and supported
protocols.
1.1
Protocol
1.1.1
LON communication protocol

The LON protocol is specified in the LonTalkProtocol Specification Version 3
from Echelon Corporation. This protocol is designed for communication in
control networks and is a peer-to-peer protocol where all the devices connected to the network can communicate with each other directly.
1.1.2
IEC61850-8 communication protocol

IEC 61850-8-1 allows two or more intelligent electronic devices (IEDs) from
one or several vendors to exchange information and to use it in the performance of their functions and for correct co-operation.
GOOSE (Generic Object Oriented Substation Event), which is a part of IEC
61850-8-1 standard, allows the IEDs to communicate state and control information amongst themselves, using a publish-subscribe mechanism. That
is, upon detecting an event, the IED(s) use a multi-cast transmission to notify
those devices that have registered to receive the data. An IED can, by publishing a GOOSE message, report its status. It can also request a control action to be directed at any device in the network.
212

1.1.3
IEC60870-5-103 communication protocol

The IEC 60870-5-103 communication protocol is mainly used when a protection IED communicates with a third party control or monitoring system. This
system must have software that can interpret the IEC 60870-5-103 communication messages.
The IEC 60870-5-103 is an unbalanced (master-slave) protocol for coded-bit
serial communication exchanging information with a control system. In IEC
terminology a primary station is a master and a secondary station is a slave.
The communication is based on a point-to-point principle. The master must
have software that can interpret the IEC 60870-5-103 communication messages. For detailed information about IEC 60870-5-103, refer to the
IEC60870 standard part 5: Transmission protocols, and to the section 103:
Companion standard for the informative interface of protection equipment.
1.2
Communication port
1.2.1

There is a serial RS232 port on the front plate of all IEDs. Through this port,
the IED can be connected to the personal computer for setting, testing, and
configuration using the dedicated Sifang software tool.
1.2.2
RS485 communication ports

Up to 2 isolated electrical RS485 communication ports are provided to connect with substation automation system. These two ports can work in parallel
for IEC60870-5-103.
1.2.3
Ethernet communication ports

Up to 3 electrical or optical Ethernet communication ports are provided to
connect with substation automation system. These two out of three ports can
work in parallel for protocol, IEC61850 or IEC60870-5-103.
1.3
Technical data
213

Item
Data
Number
Connection
Isolated, RS232; front panel

9-pin subminiature connector, for CSmart
Communication speed
9600 baud
Max. length of communication cable
15 m
RS485 communication port

Item
Data
Number
0~2
Connection
2-wire connector
Rear port in communication module
1.0 km

Communication speed
Factory setting 9600 baud

Min. 1200 baud, Max. 19200 baud
Ethernet communication port

Item
Data
Electrical communication port
Number
0~3
Connection
RJ45 connector
100m
IEC 61850 protocol

Communication speed
100 Mbit/s

Communication speed
100 Mbit/s
Optical communication port ( optional )
Number
0~3
Connection
SC connector
214

Item
Data
Optical cable type
Multi-mode
2.0km
IEC 61850 protocol

Communication speed
100 Mbit/s

Communication speed
100 Mbit/s
Time synchronization
Item
Data
Mode
Pulse mode
IRIG-B signal format
IRIG-B000
Connection
2-wire connector
Voltage levels
differential input
215
2 Typicalcommunication scheme
2.1
Typical substation communication scheme

Server or
Work Station 1
Work Station 3
Server or
Work Station 2
Switch
Work Station 4
Net 1: IEC61850/IEC103,Ethernet Port A
Switch
Net 2: IEC61850/IEC103,Ethernet Port B
Switch
Switch
Switch
Gateway
or
converter
Switch
Gateway
or
converter
Net 4: IEC103, RS485 Port B

Net 3: IEC103, RS485 Port A
Figure 74 Connection example for multi-networks of station automation system
2.2
Typical time synchronizing scheme

All IEDs feature a permanently integrated electrical time synchronization port.
It can be used to feed timing telegrams in IRIG-B or pulse format into the
IEDs via time synchronization receivers. The IED can adapt the second or
minute pulse in the pulse mode automatically.
Meanwhile, SNTP network time synchronization can be applied.
Below figure illustrates the optional time synchronization modes.
216
SNTP
Ethernet port
IRIG-B
IRIG-B port
Pulse
Binary input
Figure 75 Time synchronizing modes
217
218
Chapter 20 Hardware
Chapter 20 Hardware
About this chapter

This chapter describes the IED hardware.
219
Chapter 20 Hardware
Introduction
1.1
IED structure
The enclosure for equipment is 19 inches in width and 4U in height according
to IEC 60297-3.
The equipment is flush mounting with panel cutout and cabinet.
Connection terminals to other system on the rear.
The front panel of equipment is aluminium alloy by founding in integer
and overturn downwards. LCD, LED and setting keys are mounted on the
panel. There is a serial interface on the panel suitable for connecting to PC.
Draw-out modules for serviceability are fixed by lock component.
The modules can be combined through the bus on the rear board. Both
the equipment and the other system can be combined through the rear interfaces.
1.2
IED appearance
Figure 76 Protection IED front view

220
Chapter 20 Hardware
1.3
IED module arrangement
X1
X2
X3
X4
X5
X6
AIM
AIM
AIM
AIM
COM
BIM
X7
X8
X9
X10
X11
X12
BOM1 BOM2 BOM3 BOM4
X13
PSM
Power supply module
Spare slot
Binary output module 4
Spare slot
Binary input module
Communication mod-
ule
Spare slot
Analogue Input module
Figure 77 Module arrangement front view, when open the front panel
1.4
The rear view of the protection IED
Test port
X13
PSM
X12
For BIM and BOM
X11
X10
X9
X8
Ethernet ports
X7
X6
X5
COM
X3
AIM
X2
AIM
X1
AIM
Figure 78 Rear view of the protection IED
221
Chapter 20 Hardware
Local human-machine interface

Setting operation and interrogation of numerical protection systems can be
carried out via the integrated membrane keyboard and display panel located
on the front plate. All the necessary operating parameters can be entered and
all the information can be read out from here,e.g. display, main menu, debugging menu. Operation is, additionally, possible via interface socket by
means of a personal computer or similar.
2.1
Human machine interface

Front panel adopts little arc streamline and beelines sculpt, and function keys
for MMI are reasonably distributed in faceplate. Panel layout are shown as
below figures.
222
Chapter 20 Hardware
4
CSC-326
Figure 79 Front panel layout for 8 LEDs
4
CSC-326
Figure 80 Front panel layout for 20 LEDs
2.2
LCD
The member of keyboard and display panel is externally arranged similar to a
pocked calculator.
2.3
Keypad
The keypad is used to monitor and operate the IED. The keypad has the
223
Chapter 20 Hardware
same look and feel in all IEDs in the CSC series. LCD screens and other
details may differ but the way the keys function is identical. The keys used to
operate the IED are described below.
Table 172 function of keys of the keypad
Key
SET
function
SET key:
Enters main menu or sub-menu, and confirms the setting changes
QUIT
QUIT key:
Navigates backward the upper menu.
Cancels current operation and navigates backward the upper

menu.
Returns normal rolling display mode
Locks and unlocks current display in the normal scrolling display

mode; (the locked display mode is indicated by a key type icon
on the upright corner of LCD.)
Right arrow key:
Moves right in menu.
Left arrow key:
Moves left in menu.
Up arrow key:
Moves up in menu
Page up between screens
Increases value of setting.
Down arrow key
Moves down in menu
Page down between screens
Decreases the value of setting.
RESET key:
RESET
2.4
Reset LEDs
Return to normal scrolling display mode directly
Shortcut keys and functional keys

The shortcut keys and functional keys are below the LCD on the front panel. These
keys are designated to execute the frequent menu operations for users convenience.
The keys used to operate the IED are described below.
224
Chapter 20 Hardware
Table 173 function of Shortcut keys and functional keys
Key
function
F1
Reserved
F2
F3
Reserved
Reserved
F4
Reserved
Plus key:
Switch next setting group forward as active setting group meaning
the number of setting group plus one.
Minus key
Switch next setting group backward as active setting group , meaning the number of setting group subtracted one.
2.5
LED
The definitions of the LEDs are fixed and descrbed below.
Table 174 Definition of 8 LEDs
No
LED
Color
Description
Steady lighting: Operation normally
Run
Green
Flashing: IED startup
Steady lighting: Alarm II, meaning abnormal situation,
only the faulty function is out of service. Power supply
for tripping output is not blocked.
Alarm
Red
Flashing: Alarm I, meaning severe internal fault, all
protections are out of service. And power supply for
tripping outputs is blocked as well.
The definitions of the LEDs are fixed and described below for 20 LEDs.
Table 175 Definition of 20 LEDs
No
LED
Color
Description
Steady lighting: Operation normally
Run
Green
Flashing: IED startup
225
Chapter 20 Hardware
No
LED
Color
Description
Steady lighting: Alarm II, meaning abnormal situation,
only the faulty function is out of service. Power supply
for tripping output is not blocked.
11
Alarm
Red
Flashing: Alarm I, meaning severe internal fault, all
protections are out of service. And power supply for
tripping outputs is blocked as well.
The other LEDs which are not described above can be configured.
2.6

There is a serial RS232 port on the front plate of all the IEDs. Through this
port, the IED can be connected to the personal computer for setting, testing,
and configuration using the dedicated Sifang software tool.
226
Chapter 20 Hardware
Analog input module
3.1
Introduction
The analogue input module is used to galvanically separate and transform the
secondary currents and voltages generated by the measuring transformers.
There are two types of current transformer: Rated current 5A with linearity
range 50mA150A and rated current 1A with linearity range 100mA30A
(please indicate clearly when order the product).
3.2
Terminals of Analogue Input Module (AIM)

b
b01
a01
b02
a02
b03
a03
b04
a04
b05
a05
b06
a06
b07
a07
b08
a08
b09
a09
b10
a10
b11
a11
b12
a12
Figure 81 Terminals arrangement of AIM E
227
Chapter 20 Hardware
Table 176 Description of terminals of AIM E
Terminal
228
Analogue
Input
Remark
a01
IA
Star point
b01
IA
a02
IB
b02
IB
a03
IC
b03
IC
a04
IN
b04
IN
a05
INM
b05
INM
a06
Null
b06
Null
a07
Null
b07
Null
a08
Null
b08
Null
a09
Null
b09
Null
a10
U4
b10
U4
a11
UB
Star point
b11
UC
Star point
a12
UA
Star point
b12
UN
Star point
Star point
Star point
Star point
Star point
Star point
Star point
Star point
Chapter 20 Hardware
3.3
Technical data
3.3.1
Internal current transformer

Item
Standard
IEC 60255-1
Rated current I r
R
Data
1 or 5 A
Nominal current range
0.05 I r to 30 I r
Nominal current range of sensitive
0.005 to 1 A
CT
0.1 VA at I r = 1 A;
Power consumption (per phase)
0.5 VA at I r = 5 A
R
0.5 VA for sensitive CT
IEC 60255-1
100 I r for 1 s
IEC 60255-27
4 I r continuous
Thermal overload capability for
IEC 60255-27
100 A for 1 s
sensitive CT
DL/T 478-2001
3 A continuous
Thermal overload capability
3.3.2
Internal voltage transformer

21B
Item
Standard
IEC 60255-1
Rated voltage V r (ph-ph)

R
Nominal range (ph-e)
Data
100 V /110 V
0.4 V to 120 V
Power consumption at V r = 110 V

R
IEC 60255-27
0.1 VA per phase
DL/T 478-2001
IEC 60255-27
2 V r , for 10s
(phase-neutral voltage)
DL/T 478-2001
1.5 V r , continuous
229
Chapter 20 Hardware
Communication module
4.1
Introduction
The communication module performs communication between the internal
protection system and external equipments such as HMI, engineering workstation, substation automation system, RTU, etc., to transmit remote metering,
remote signaling, SOE, event reports and record data.
Up to 3 channels isolated electrical or optical Ethernet ports and up to 2
channels RS485 serial communication ports can be provided in communication module to meet the communication demands of different substation automation system and RTU at the same time.
The time synchronization port is equipped, which can work in pulse mode or
IRIG-B mode. SNTP mode can be applied through communication port.
In addition, a series printer port is also reserved.
4.2
Substaion communication port
4.2.1

There is a serial RS232 port on the front plate of all the IEDs. Through this
port, the IED can be connected to the personal computer for setting, testing,
and configuration using the dedicated Sifang software tool.
4.2.2

Up to 2 isolated electrical RS485 communication ports are provided to connect with substation automation system. These two ports can work in parallel
for IEC60870-5-103.
4.2.3
Ethernet communication ports

Up to 3 electrical or optical Ethernet communication ports are provided to
connect with substation automation system. Two out of these three ports can
230
Chapter 20 Hardware
work in parallel for protocol, IEC61850 or IEC60870-5-103.
4.2.4
Time synchronization port

All IEDs feature a permanently integrated electrical time synchronization port.
It can be used to feed timing telegrams in IRIG-B or pulse format into the
IEDs via time synchronization receivers. The IED can adapt the second or
minute pulse in the pulse mode automatically.
Meanwhile, SNTP network time synchronization can also be applied.
4.3
Terminals of Communication Module

01
02
Ethernet port A
03
04
05
06
07
Ethernet port B
08
09
10
11
12
Ethernet port C
13
14
15
16
Figure 82 Terminals arrangement of COM

Table 177 Definition of terminals of COM
Terminal
Definition
01
Null
02
Null
03
Null
04
Null
231
Chapter 20 Hardware
05
Optional RS485 port - 2B
06
Optional RS485 port - 2A
07
Optional RS485 port - 1B
08
Optional RS485 port - 1A
09
10
Time synchronization GND
11
Null
12
Null
13
Null
14
Null
15
Null
16
Null
Ethernet
Port A
Optional optical fiber or RJ45

port for station automation system
Ethernet
Port B

Ethernet
Port C

4.4
Operating reports
Information
Description
DI Comm Fail
DI communication error
DO Comm Fail
DO communication error
4.5
Technical data
4.5.1

Item
Data
Number
Connection
Isolated, RS232; front panel,

9-pin subminiature connector, for software tools
232
Chapter 20 Hardware
Communication speed
9600 baud
15 m
4.5.2
RS485 communication port

Item
Data
Number
0 to 2
Connection
2-wire connector
1.0 km
Test voltage
500 V AC against earth
For IEC 60870-5-103 protocol

Communication speed
Factory setting 9600 baud,

Min. 1200 baud, Max. 19200 baud
4.5.3
Ethernet communication port

Item
Data
Electrical communication port
Number
0 to 3
Connection
RJ45 connector
100m
For IEC 61850 protocol

Communication speed
100 Mbit/s
For IEC 60870-5-103 protocol

Communication speed
100 Mbit/s
Optical communication port ( optional )
Number
0 to 2
Connection
SC connector
Optical cable type
Multi-mode
2.0km
IEC 61850 protocol

Communication speed
100 Mbit/s

Communication speed
100 Mbit/s
233
Chapter 20 Hardware
4.5.4
Item
Data
Mode
Pulse mode
IRIG-B signal format
IRIG-B000
Connection
2-wire connector
Voltage levels
234
differential input
Chapter 20 Hardware
Binary input module
5.1
Introduction
The binary input module is used to connect the input signals and alarm signals such as the auxiliary contacts of the circuit breaker (CB), etc.
The negative terminal of power supply for BI module, 220V or 110V, should
be connected to the terminal.
5.2
Terminals of Binary Input Module (BIM)

c
c02
a02
c04
a04
c06
a06
c08
a08
c10
a10
c12
a12
c14
a14
c16
a16
c18
a18
c20
a20
c22
a22
c24
a24
c26
a26
c28
a28
c30
a30
c32
DC -
DC -
a32
Figure 83: Terminals arrangement of BIM A
235
Chapter 20 Hardware
Table 178 Definition of terminals of BIM A
236
Terminal
Definition
Remark
a02
BI1
BI group 1
c02
BI2
BI group 2
a04
BI3
BI group 1
c04
BI4
BI group 2
a06
BI5
BI group 1
c06
BI6
BI group 2
a08
BI7
BI group 1
c08
BI8
BI group 2
a10
BI9
BI group 1
c10
BI10
BI group 2
a12
BI11
BI group 1
c12
BI12
BI group 2
a14
BI13
BI group 1
c14
BI14
BI group 2
a16
BI15
BI group 1
c16
BI16
BI group 2
a18
BI17
BI group 1
c18
BI18
BI group 2
a20
BI19
BI group 1
c20
BI20
BI group 2
a22
BI21
BI group 1
c22
BI22
BI group 2
a24
BI23
BI group 1
c24
BI24
BI group 2
a26
BI25
BI group 1
c26
BI26
BI group 2
a28
BI27
BI group 1
c28
BI28
BI group 2
a30
BI29
BI group 1
c30
BI30
BI group 2
a32
DC - Input
Common terminal of BI group 1
c32
DC - Input
Common terminal of BI group 2
Chapter 20 Hardware
5.3
Technical data
Item
Input voltage range
Standard
IEC60255-1
Data
110/125 V DC
220/250 V DC
Threshold1: guarantee oper-
IEC60255-1
ation
Threshold2: uncertain opera-
77V, for 110V/125V DC

IEC60255-1
tion
Response time/reset time
154V, for 220/250V DC
132V, for 220/250V DC;

66V, for 110V/125V DC
IEC60255-1
Software provides de-bounce

time
Power consumption, energized
IEC60255-1
Max. 0.2 W/input, 24V DC

Max. 1 W/input, 220V DC
237
Chapter 20 Hardware
Binary output module
6.1
Introduction
The binary output modules mainly provide tripping output contacts, initiating
output contacts and signaling output contacts. All the tripping output relays
have contacts with a high switching capacity and are blocked by protection
startup elements.
Each output relay can be configured to satisfy the demands of users.
6.2
Terminals of Binary Output Module (BOM)
6.2.1
Binary Output Module A

The module provides 16 output relays for tripping or initiating, with total 16
contacts.
238
Chapter 20 Hardware
R
3
R
1
R
5
R
7
R
9
R
11
R
13
R
15
c02
a02
c04
a04
c06
a06
c08
a08
c10
a10
c12
a12
c14
a14
c16
a16
c18
a18
c20
a20
c22
a22
c24
a24
c26
a26
c28
a28
c30
a30
c32
a32
R
2
R
4
R
6
R
8
R
10
R
12
R
14
R
16
Figure 84 Terminals arrangement of BOM A
239
Chapter 20 Hardware
Table 179 Definition of terminals of BOM A
240
Terminal
Definition
Related relay
a02
Trip contact 1-0
Output relay 1
c02
Trip contact 1-1
Output relay 1
a04
Trip contact 2-0
Output relay 2
c04
Trip contact 2-1
Output relay 2
a06
Trip contact 3-0
Output relay 3
c06
Trip contact 3-1
Output relay 3
a08
Trip contact 4-0
Output relay 4
c08
Trip contact 4-1
Output relay 4
a10
Trip contact 5-0
Output relay 5
c10
Trip contact 5-1
Output relay 5
a12
Trip contact 6-0
Output relay 6
c12
Trip contact 6-1
Output relay 6
a14
Trip contact 7-0
Output relay 7
c14
Trip contact 7-1
Output relay 7
a16
Trip contact 8-0
Output relay 8
c16
Trip contact 8-1
Output relay 8
a18
Trip contact 9-0
Output relay 9
c18
Trip contact 9-1
Output relay 9
a20
Trip contact 10-0
Output relay 10
c20
Trip contact 10-1
Output relay 10
a22
Trip contact 11-0
Output relay 11
c22
Trip contact 11-1
Output relay 11
a24
Trip contact 12-0
Output relay 12
c24
Trip contact 12-1
Output relay 12
a26
Trip contact 13-0
Output relay 13
c26
Trip contact 13-1
Output relay 13
a28
Trip contact 14-0
Output relay 14
c28
Trip contact 14-1
Output relay 14
a30
Trip contact 15-0
Output relay 15
c30
Trip contact 15-1
Output relay 15
a32
Trip contact 16-0
Output relay 16
c32
Trip contact 16-1
Output relay 16
Chapter 20 Hardware
Binary Output Module C
6.2.2
The module provides 16 output relays for signal, with total 19 contacts.
R
6
R
7
R
1
R
2
R
3
R
5
R
4
c02
a02
c04
a04
c06
a06
c08
a08
c10
a10
c12
a12
c14
a14
c16
a16
c18
a18
c20
a20
c22
a22
c24
a24
c26
a26
c28
a28
c30
a30
c32
a32
R
8
R
9
R
10
R
11
R
12
R
13
R
14
R
15
R
16
Figure 85 Terminals arrangement of BOM C
241
Chapter 20 Hardware
Table 180 Definition of terminals of BOM C
Terminal
242
Definition
a02
Signal 1-0, Common terminal of signal contact group 1
c02
Related relay
a04
Signal contact 1-1
Output relay 1
c04
Signal contact 2-1
Output relay 1
a06
Signal contact 1-2
Output relay 2
c06
Signal contact 2-2
Output relay 2
a08
Signal contact 1-3
Output relay 3
c08
Signal contact 2-3
Output relay 3
a10
c10
a12
Signal contact 3-1
Output relay 4
c12
Signal contact 4-1
Output relay 6
a14
Signal contact 3-2
Output relay 5
c14
Signal contact 4-2
Output relay 7
a16
Signal contact 5-0
Output relay 8
c16
Signal contact 5-1
Output relay 8
a18
Signal contact 6-0
Output relay 9
c18
Signal contact 6-1
Output relay 9
a20
Signal contact 7-0
Output relay 10
c20
Signal contact 7-1
Output relay 10
a22
Signal contact 8-0
Output relay 11
c22
Signal contact 8-1
Output relay 11
a24
Signal contact 9-0
Output relay 12
c24
Signal contact 9-1
Output relay 12
a26
Signal contact 10-0
Output relay 13
c26
Signal contact 10-1
Output relay 13
a28
Signal contact 11-0
Output relay 14
c28
Signal contact 11-1
Output relay 14
a30
Signal contact 12-0
Output relay 15
c30
Signal contact 12-1
Output relay 15
a32
Signal contact 13-0
Output relay 16
c32
Signal contact 13-1
Output relay 16
Chapter 20 Hardware
6.3
Technical data
Item
Standard
Data
Max. system voltage
IEC60255-1
250V DC/AC
Current carrying capacity
IEC60255-1
5 A continuous,
42A1s ON, 9s OFF
Making capacity
IEC60255-1
1100 W(DC) at inductive load

with L/R>40 ms
1000 VA(AC)
Breaking capacity
IEC60255-1
1000 cycles
DC220V, 0.15A t=L/R40 ms
DC110V, 0.30A t=L/R40 ms
Unloaded mechanical endur-
IEC60255-1
ance
Specification state verification
50,000,000 cycles (3 Hz
switching frequency)
IEC60255-1
UL/CSATV
IEC60255-23
IEC61810-1
Contact circuit resistance
IEC60255-1
measurement
IEC60255-23
30m
IEC61810-1
Open Contact insulation test
IEC60255-1
(AC Dielectric strength)
IEC60255-27
Maximum temperature of parts
IEC60255-1
AC1000V 1min
55
and materials
243
Chapter 20 Hardware
Power supply module
7.1
Introduction
The power supply module is used to provide the correct internal voltages and
full isolation between the terminal and the battery system. Its power input is
DC 220V or 110V (according to the order code), and its outputs are five
groups of power supply.
(1) 24V two groups provided: Power for inputs of the corresponding binary inputs of the CPU module
7.2
(2) 12V:
Power for A/D
(3) + 5V:
Power for all micro-chips
Terminals of Power Supply Module (PSM)

c
c02
c04
a
DC 24V +
OUTPUTS
a04
a06
c06
a08
c08
c10
a02
DC 24V OUTPUTS
a10
c12
a12
c14
a14
c16
a16
c18
a18
c20
c22
AUX.DC +
INPUT
c24
c26
c28
a20
a22
a24
AUX. DC INPUT
a26
a28
c30
a30
c32
a32
Figure 86 Terminals arrangement of PSM
244
Chapter 20 Hardware
Table 181 Definition of terminals of PSM
Terminal
Definition
a02
AUX.DC 24V+ output 1
c02
a04
c04
a06
Isolated terminal, not wired
c06
a08
AUX.DC 24V- output 1
c08
a10
c10
a12
c12
a14
Alarm contact A1, for AUX.DC power input failure
c14
Alarm contact A0, for AUX.DC power input failure
a16
Alarm contact B1, for AUX.DC power input failure
c16
Alarm contact B0, for AUX.DC power input failure
a18
c18
a20
AUX. power input 1, DC +
c20
a22
c22
a24
c24
a26
AUX. power input 1, DC -
c26
a28
c28
a30
c30
a32
Terminal for earthing
c32
Terminal for earthing
245
Chapter 20 Hardware
7.3
Technical data
Item
Data
Rated auxiliary voltage V aux
110~250V DC
Permissible tolerance
%20 U aux
Power consumption
Normal operation
30 W
Tripping condition
50 W
246
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Not Used
SIG-4COM(+) SIG-3COM(+)
HV OL Alarm MV OL Alarm
LV OL Alarm LW OL Alarm
Relay Startup
Inst Diff A Trip
Inst Diff B Trip
Inst Diff C Trip
Per Diff A Trip
Per Diff B Trip
Per Diff C Trip
HV OV1 Alm
HV OV2 Alm
Not Used
HV REF Alarm-2 HV REF Alarm-1
Diff Alarm-2 Diff Alarm-1
a
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
DC- Input
Not Used
Not Used
HV VT Fail MV VT Fail
CT Fail
LV VT Fail
HV Thermal OL Alarm
MV Thermal OL Alarm
Over Excit DEF Alarm
BO_Config1
BO_Config2
Relay Fault-1
Relay Fault-2
Run Alarm-1
Run Alarm-2
HV REF Trip-2 HV REF Trip-1
Diff Trip-2 Diff Trip-1
A
RX
A
TX
B
RX
B
TX
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
a
Diff Trip
HV REF Trip
Not Used
Def V/F Trip
Inv V/F Trip
HV OC1 Trip
HV OC2 Trip
HV OC Inv Trip
HV EF1 Trip
HV EF2 Trip
HV EF Inv Trip
HV NOC1 Trip
HV NOC2 Trip
HV NOC Inv Trip
HV STUB Trip
HV Therm OL Trip
X8(BO Module)
12 U1N U1A
12 U2N U2A
12 U3N U3A
X9(BO Module)
11 U1C U1B
10
8 INBKH'INBKH
11 U2C U2B
10
11 U3C U3B
10 UL0' UL0
7 IREFH'IREFH
6 IH2C' IH2C
6 IM2C' IM2C
6 ILWC' ILWC
7
5 IH2B' IH2B
5 IM2B' IM2B
5 ILWB' ILWB
c
a
HV OV1 Trip
HV OV2 Trip
HV DIS(Ph-N) Trip
MV DIS(Ph-N) Trip
MV OC1 Trip
MV OC2 Trip
MV OC Inv Trip
MV EF1 Trip
MV EF2 Trip
MV EF Inv Trip
LV OC1 Trip
LV OC2 Trip
LV OC Inv Trip
HV DIS (Ph-Ph) Trip
MV DIS (Ph-Ph) Trip
MV Therm OL Trip
3 IH1C' IH1C
3 IM1C' IM1C
3 ILC' ILC
4 IH2A' IH2A
2 IH1B' IH1B
2 IM1B' IM1B
2 ILB' ILB
4 IM2A' IM2A
a
b
1 IH1A' IH1A
a
b
1 IM1A' IM1A
a
b
1 ILA' ILA
4 ILWA' ILWA
X1(AI Module)
X2(AI Module)
X3(AI Module)
Terminal diagram
8.1
Typical Terminal diagram of CSC-326
DC- Input
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
X11(BO Module)
DC- Input
LV VT MCB Fail HV STUB Enable
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
100M BASE-FX
X5(Master Module)
NOT USED
232-TRAN
232-RECV
232-GND
485-2B
485-2A
485-1B
485-1A
GPS
GPSGND
LON-2A
LON-2B
LONGND
LON-1A
LON-1B
NOT USED
X10(BO Module)
Not Used
BI_Trigger_DR9
Not Used
Not Used
BI_Trigger_DR8
MV VT MCB Fail
Not Used
BI_Trigger_DR7
Not Used
Not Used
BI_Trigger_DR6
Not Used
Not Used
BI_Trigger_DR5
HV VT MCB Fail
Not Used
BI_Trigger_DR4
BI_Trigger_DR10
Not Used
BI_Trigger_DR3
Reset
Switch SetGroup
BI_Trigger_DR2
Relay Test
BI_Config2
Blk Rem Access
BI_Trigger_DR1
BI_Config1
DC+ Input
DC Failure
DC Failure
R24V- Out
R24V+ Out
X13(Power)
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
BASE-T
10/100M
X6(BI Module)
Chapter 20 Hardware
247
Chapter 20 Hardware
Techinical data
9.1
Basic data
9.1.1
Frequency
Item
Data
System rated frequency
50 Hz or 60Hz
Internal current transformer
9.1.2
24B
Item
Data
Rated current I r
1 or 5 A
Nominal current range
(0.05 20)x I r
Power consumption (per phase)
0.1 VA at I r = 1 A;
0.5 VA at I r = 5 A
R
100 x I r for 1 s
R
4 x I r continuous
R
Internal voltage transformer
9.1.3
25B
Item
Data
Rated voltage V r (ph-ph)
100-120
Nominal range (ph-e)
0.4 V to 120 V
Power consumption at V r = 110 V
0.1 VA per phase
Thermal overload capability (phase-neutral
2V r , for 10s
voltage)
1.5V r , continuous
9.1.4
Auxiliary voltage
26B
Item
Standard
Data
Rated auxiliary voltage V aux
IEC60255-1
110 to 250V DC
Permissible tolerance
IEC60255-1
%20 U aux
248
Chapter 20 Hardware
Item
Standard
Power consumption at quies-
Data
IEC60255-1
50 W
IEC60255-1
60 W
IEC60255-1
T 10 ms/I 25 A
cent state
Power consumption at maximum load
Inrush Current
Binary inputs
9.1.5
Item
Input voltage range
Standard
IEC60255-1
Data
110/125 V DC
220/250 V DC
Threshold1: guarantee oper-
IEC60255-1
ation
154V, for 220/250V DC

77V, for 110V/125V DC
Threshold2: uncertain opera-
IEC60255-1
tion
132V, for 220/250V DC;

66V, for 110V/125V DC
Response time/reset time
IEC60255-1
Software provides de-bounce

time
Power consumption, ener-
IEC60255-1
gized

Max. 1 W/input, 220V DC
9.1.6
Binary outputs
28B
Item
Standard
Data
Max. system voltage
IEC60255-1
250V DC/AC
Current carrying capacity
IEC60255-1
5 A continuous,
42A1s ON, 9s OFF
Making capacity
IEC60255-1
1100 W(DC) at inductive load

with L/R>40 ms
1000 VA(AC)
Breaking capacity
IEC60255-1
1000 cycles
DC220V, 0.15A t=L/R40 ms
DC110V, 0.30A t=L/R40 ms
Unloaded mechanical endurance
IEC60255-1
50,000,000 cycles (3 Hz
switching frequency)
249
Chapter 20 Hardware
Item
Specification state verification
Standard
IEC60255-1
Data
UL/CSATV
IEC60255-23
IEC61810-1
Contact circuit resistance
IEC60255-1
measurement
IEC60255-23
30m
IEC61810-1
Open Contact insulation test
IEC60255-1
(AC Dielectric strength)
IEC60255-27
Maximum temperature of parts
IEC60255-1
AC1000V 1min
55
and materials
9.2
Type tests
9.2.1
Product safety-related Tests

Item
Standard
Data
Over voltage category
IEC60255-27
Category III
Pollution degree
IEC60255-27
Degree 2
Insulation
IEC60255-27
Basic insulation
Degree of protection (IP)
IEC60255-27
Front plate: IP40
IEC 60529
Rear, side, top and bottom: IP

30
Power frequency high voltage
IEC 60255-5
2KV, 50Hz
withstand test
ANSI C37.90
2.8kV DC
GB/T 15145-2001
between the following circuits:
DL/T 478-2001
auxiliary power supply

CT / VT inputs
binary inputs
binary outputs
case earth
500V, 50Hz
between the following circuits:
Communication ports to
case earth
time synchronization terminals to case earth
250
Chapter 20 Hardware
Item
Impulse voltage test
Standard
Data
5kV (1.2/50s, 0.5J)
IEC60255-5
if U i 63V
IEC 60255-27
ANSI C37.90
1kV if U i <63V
GB/T 15145-2001
Tested between the following
DL/T 478-2001
circuits:
CT / VT inputs
binary inputs
binary outputs
case earth
Note: U i : Rated voltage
Insulation resistance
100 M at 500 VDC
IEC60255-5
IEC 60255-27
ANSI C37.90
GB/T 15145-2001
DL/T 478-2001
Protective bonding resistance
IEC60255-27
0.1
Fire withstand/flammability
IEC60255-27
Class V2
9.2.2
Electromagnetic immunity tests

Item
1 MHz burst immunity test
Standard
Data
IEC60255-22-1
class III
IEC60255-26
2.5 kV CM ; 1 kV DM
IEC61000-4-18
Tested on the following circuits:
ANSI/IEEE C37.90.1

CT / VT inputs
binary inputs
binary outputs
1 kV CM ; 0 kV DM
communication ports
Electrostatic discharge
IEC 60255-22-2
Level 4
IEC 61000-4-2
8 kV contact discharge;
15 kV air gap discharge;
both polarities; 150 pF; R i = 330
R
251
Chapter 20 Hardware
Item
Radiated electromagnetic field
Standard
IEC 60255-22-3
disturbance test
Data
frequency sweep:
80 MHz 1 GHz; 1.4 GHz 2.7 G
spot frequencies:
80 MHz; 160 MHz; 380 MHz;
450 MHz; 900 MHz; 1850 MHz;
2150 MHz
10 V/m
AM, 80%, 1 kHz
Radiated electromagnetic field
IEC 60255-22-3
disturbance test
pulse-modulated
10 V/m, 900 MHz; repetition rate
200 Hz, on duration 50 %
Electric fast transient/burst im-
IEC 60255-22-4,
class A, 4KV
munity test
IEC 61000-4-4
ANSI/IEEE C37.90.1

CT / VT inputs
binary inputs
binary outputs
class A, 2KV
communication ports
Surge immunity test
IEC 60255-22-5
4.0kV L-E
IEC 61000-4-5
2.0kV L-L
CT / VT inputs
binary inputs
binary outputs
2.0kV L-E
communication ports
Conduct immunity test
IEC 60255-22-6
frequency sweep: 150 kHz 80
IEC 61000-4-6
MHz
spot frequencies: 27 MHz and
68 MHz
10 V
AM, 80%, 1 kHz
Power frequency immunity test
IEC60255-22-7
Class A
300 V CM
150 V DM
252
Chapter 20 Hardware
Item
Power frequency magnetic field
Standard
IEC 61000-4-8
test
Data
level 4
30 A/m cont. / 300 A/m 1 s to 3 s
100 kHz burst immunity test
IEC61000-4-18
2.5 kV CM ; 1 kV DM
CT / VT inputs
binary inputs
binary outputs
1 kV CM ; 0 kV DM
communication ports
DC voltage interruption test
9.2.3
231B
Item
DC voltage dips
Standard
IEC 60255-11
Data
100% reduction 80 ms
DC voltage interruptions
IEC 60255-11
100% reduction 5 s
DC voltage ripple
IEC 60255-11
15%, twice rated frequency
DC voltage gradual shutdown
IEC 60255-11
60 s shut down ramp
/start-up
5 min power off

60 s start-up ramp
DC voltage reverse polarity
9.2.4
IEC 60255-11
1 min
Electromagnetic emission test

23B
Item
Radiated emission
Conducted emission
Standard
Data
IEC60255-25
30MHz to 1GHz ( IT device may
CISPR22
up to 5 GHz)
IEC60255-25
0.15MHz to 30MHz
CISPR22
253
Chapter 20 Hardware
9.2.5
Mechanical tests
Item
Sinusoidal Vibration response
Standard
IEC60255-21-1
test
Data
class 1
10 Hz to 60 Hz: 0.075 mm
60 Hz to 150 Hz: 1 g
1 sweep cycle in each axis
Relay energized
Sinusoidal Vibration endur-
IEC60255-21-1
ance test
class 1
10 Hz to 150 Hz: 1 g
20 sweep cycle in each axis
Relay non-energized
Shock response test
IEC60255-21-2
class 1
5 g, 11 ms duration
3 shocks in both directions of 3
axes
Relay energized
Shock withstand test
IEC60255-21-2
class 1
15 g, 11 ms duration
3 shocks in both directions of 3
axes
Relay non-energized
Bump test
IEC60255-21-2
class 1
10 g, 16 ms duration
1000 shocks in both directions of
3 axes
Relay non-energized
Seismic test
IEC60255-21-3
class 1
X-axis 1 Hz to 8/9 Hz: 7.5 mm
X-axis 8/9 Hz to 35 Hz :2 g
Y-axis 1 Hz to 8/9 Hz: 3.75 mm
Y-axis 8/9 Hz to 35 Hz :1 g
1 sweep cycle in each axis,
Relay energized
254
Chapter 20 Hardware
9.2.6
Climatic tests
Item
Standard
Cold test - Operation
IEC60255-27
Data
-10C, 16 hours, rated load
IEC60068-2-1
Cold test Storage
IEC60255-27
-25C, 16 hours
IEC60068-2-1
Dry heat test Operation
[IEC60255-27
+55C, 16 hours, rated load
IEC60068-2-2
Dry heat test Storage
IEC60255-27
+70C, 16 hours
IEC60068-2-2
Change of temperature
Damp heat static test
Damp heat cyclic test
9.2.7
IEC60255-27
Test Nb, figure 2, 5 cycles
IEC60068-2-14
-10C / +55C
IEC60255-27
+40C, 93% r.h. 10 days, rated
IEC60068-2-78
load
IEC60255-27
+55C, 93% r.h. 6 cycles, rated
IEC60068-2-30
load
CE Certificate
Item
EN 61000-6-2 and EN61000-6-4 (EMC
EMC Directive
Council Directive 2004/108/EC)
Low voltage directive
9.3
Data
EN 60255-27 (Low-voltage directive 2006/95

EC).
IED design
Item
Data
Case size
4U19inch
Weight
8kg
255
Chapter 21 Appendix
Chapter 21 Appendix
256
Chapter 21 Appendix
General setting list
1.1
Function setting list
Setting
Unit
HV Wind Conn/Y
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
Default
setting
Description
(Ir:5A/1A)
0
Connection for HV
winding, 0:wye
connection, 1:delta
connection
MV Wind Conn/Y
Connection for MV
winding, 0:wye
connection, 1:delta
connection
LV Wind Conn/Y
Connection for LV
winding, 0:wye
connection, 1:delta
connection
Vet Grp Angle
MVA
1.000
3000.
120.0
Vector Group Angle( VET

GRP ANGLE)
SN
kV
1.000
1000.
220.0
Capacity of the transformer
HV VT Ratio
MVA
1.000
9999.
2200.0
Ratio in HV side
50.00
9999.
1200.0
HV CT Pri
in HV side
A
1.000
5.000
1.0
HV CT Sec
CT Secondary(SEC) current in HV side
HV Voltage Chan
Sel
HV voltage channel location
MV Voltage Chan
Sel
MV voltage channel location
A
HV NCT Pri(REF)
50.00
9999.
1200.0
Neutral CT (NCT) Primary(PRI) current in HV side

for REF
257
Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
1.000
5.000
Default
setting
Description
(Ir:5A/1A)
1.0
HV NCT Sec(REF)
Neutral CT (NCT) Secondary(SEC) current in

HV side for REF
50.00
9999.
1200.0
HV NCT Pri(BU)
Neutral CT (NCT) Primary(PRI) current in HV side

for backup protection
1.000
5.000
1.0
HV NCT Sec(BU)
Neutral CT (NCT) Secondary(PRI) current in HV

side for backup protection
kV
1.000
1000.
110.0
MV UN

Middle voltage (MV)side
1.000
9999.
1100.0
MV VT Ratio
Ratio in MV side
50.00
9999.
1200.0
MV CT Pri
in MV side
1.000
5.000
1.0
MV CT Sec
CT Secondary(SEC) current in MV side
50.00
9999.
1200.0
MV NCT Pri(REF)
Neutral CT (NCT) Primary(PRI) current in MV side

for REF
1.000
5.000
1.0
MV NCT Sec(REF)
Neutral CT (NCT) Secondary(SEC) current in

MV side for REF
50.00
9999.
1200.0
MV NCT Pri(BU)
Neutral CT (NCT) Primary(PRI) current in MV side

for backup protection
1.000
5.000
1.0
MV NCT Sec(BU)
Neutral CT (NCT) Secondary(PRI) current in MV

side for backup protection
kV
1.000
1000.
10.50
LV UN
Low voltage (LV)side

1.000
9999.
105.0
LV VT Ratio
A
50.00
9999.
3000.0
in LV side
258
Ratio in LV side
LV CT Pri
LV CT Sec
1.000
5.000
1.0
CT Secondary(SEC) current in LV side
Chapter 21 Appendix
Setting
LV Sec Inside
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
1.000
5.000
Delta
Default
setting
Description
(Ir:5A/1A)
1.0
CT Secondary(SEC)
current in LV inside delta
9999
HV Rated Cur Pri
Rated primary current for

HV side (calculated value, read only)
9999
HV Rated Cur Sec

for HV side (calculated
value, read only)
9999
Ratio Factor KTAH
HV ratio factor for differential protection (calculated value, read only)
9999
Ratio Factor KTAM
MV ratio factor for differential protection (calculated value, read only)
9999
LV ratio factor for differential protection (calcu-
Ratio Factor KTAL
lated value, read only)

0
9999
HV ratio factor, with zero-sequence current

calculated, for REF pro-
Ratio REF KTAH
tection (calculated value, read only)

0
9999
HV ratio factor with zero-sequence current di-
Ratio REF KNH

value, read only)
0
9999
MV ratio factor, with zero-sequence current
Ratio REF KTAM

0
9999
MV ratio factor with zero-sequence current di-
Ratio REF KNM

value, read only)
259
Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.5Ir
20Ir
Default
setting
Description
(Ir:5A/1A)
20
I_Inst Diff
Instantaneous Differential
(ID>>) current setting
0.08Ir
4Ir
2.1
I_Percent Diff
Percentage Differential
(ID>) current setting
0.1Ir
Ir
I_ResPoint1 Diff
The 1st breakpoint restraint current (IR1)
0.1Ir
10Ir
I_ResPoint2 Diff
The 2nd breakpoint restraint current (IR2)
Slope1_Diff
0.2
0.2
the 1st slope
Slope2_Diff
0.2
0.7
0.5
the 2nd slope
Slope3_Diff
0.25
0.95
0.7
the 3rd slope
Ratio_2nd Harm
0.05
0.80
0.15
2nd harmonic(HAR) ratio
0.05
0.80
0.35
3rd / 5th harmonic(HAR)
Ratio_3/5th Harm
ratio
s
20
20
Within the delay 2nd

T_2nd Harm Block

is blocked.
s
20
20
Within the delay 5th

T_3/5th Harm
Block

is blocked.
A
0.08Ir
2Ir
HV 3I0_REF
Current setting for HV

Restricted Earth Fault
protection
0.2
0.95
0.5
Slope setting for HV Restricted Earth Fault pro-
HV Slope_REF
tection
s
60
0.03
HV T_REF Trip
trip time setting

A
0.08Ir
2Ir
HV 3I0_REF Alarm
260

s
HV T_REF Alarm
60
0.03

alarm time setting
Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.08Ir
2Ir
Default
setting
Description
(Ir:5A/1A)
2
MV 3I0_REF
Current setting for MV

protection
0.2
0.95
0.5
MV Slope_REF
Slope setting for MV Restricted Earth Fault protection
60
0.03
MV T_REF Trip
MV Restricted Earth
Fault trip time setting
0.08Ir
2Ir
MV 3I0_REF
MV Restricted Earth
Fault alarm current set-
Alarm
ting
s
60
0.03
MV T_REF Alarm
MV Restricted Earth
Fault alarm time setting
0.08Ir
2Ir
LV 3I0_REF
Current setting for LV

protection
0.2
0.95
0.5
Slope setting for LV Restricted Earth Fault pro-
LV Slope_REF
tection
s
60
0.03
LV T_REF Trip
trip time setting

A
0.08Ir
2Ir
LV 3I0_REF Alarm
s
60
0.03

alarm time setting
40
130
57.3
Reference Voltage
Nominal phase voltage in

HV side
1.5
1.1
V/F_Definite Alarm
Alarming setting of
volt/hertz
0.1
9999
10
T_Definite Alarm
Timer setting for

volt/hertz alarming stage
1.5
1.2
V/F_Definite Trip
Tripping setting of definite volt/hertz stage
0.1
9999
T_Definite Trip
V/F=1.05

LV T_REF Alarm
T1_Inverse
Timer setting for definite

volt/hertz stage
0.1
9999
10
Timer setting for

volt/hertz=1.05
261
Chapter 21 Appendix
Setting
T2_Inverse
Unit
s
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.1
9999
Default
setting
90
V/F=1.10
T3_Inverse
0.1
9999
80
0.1
9999
70
0.1
9999
60
0.1
9999
50
0.1
9999
45
0.1
9999
40
Timer setting for

volt/hertz=1.40
0.1
9999
35
V/F=1.45
T10_Inverse
Timer setting for

volt/hertz=1.35
V/F=1.40
T9_Inverse
Timer setting for

volt/hertz=1.30
V/F=1.35
T8_Inverse
Timer setting for

volt/hertz=1.25
V/F=1.30
T7_Inverse
Timer setting for

volt/hertz=1.20
V/F=1.25
T6_Inverse
Timer setting for

volt/hertz=1.15
V/F=1.20
T5_Inverse
Timer setting for

volt/hertz=1.10
V/F=1.15
T4_Inverse
Description
(Ir:5A/1A)
Timer setting for

volt/hertz=1.45
0.1
9999
30
V/F=1.50
Timer setting for

volt/hertz=1.50
0.1
9999
25
T_Cool Down

overexcitation protection
0.05Ir
20Ir
HV I_OC1
HV overcurrent (O/C)
current setting for Stage
1
60
60
HV T_OC1

Stage 1
0.05Ir
20Ir
HV overcurrent (O/C)
HV I_OC2
2
s
60
60
HV T_OC2

Stage 2
HV Curve_OC Inv
12
Ref to appendix 3 page

307
0.05Ir
20Ir
HV I_OC Inv
307
0.05
HV K_OC Inv
262
999

307
Chapter 21 Appendix
Setting
Unit
s
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
200
Default
setting
Description
(Ir:5A/1A)
0.14
HV A_OC Inv

307
60
HV B_OC Inv

307
10
0.02
HV P_OC Inv

307
90
45
HV Angle_OC
The angle setting for

voltage ahead of current.
0.25Ir
20Ir
The maximum 1st

-harmonic current setting
HV
to remove the inrush
Imax_2H_UnBlk
block, in HV O/C protection

0.07
0.5
0.2
HV Ratio_I2/I1
Inrush 2nd harmonic ratio

setting for blocking HV
O/C protection
60
20
Inrush 2nd harmonic

cross-block time for HV
HV T2h_Cross_Blk
O/C protection
A
0.05Ir
20Ir
MV I_OC1
MV overcurrent (O/C)
1
60
60
MV T_OC1

Stage 1
0.05Ir
20Ir
MV I_OC2
MV overcurrent (O/C)
2
60
60
MV T_OC2

Stage 2
MV Curve_OC Inv
12

307
0.05Ir
20Ir
MV I_OC Inv
307
0.05
999
MV K_OC Inv

307
s
MV A_OC Inv
200
0.14

307
263
Chapter 21 Appendix
Setting
Unit
s
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
60
Default
setting
Description
(Ir:5A/1A)
0
MV B_OC Inv

307
10
0.02
MV P_OC Inv

307
90
45
MV Angle_OC

0.25Ir
20Ir
The maximum 1st

MV
Imax_2H_UnBlk
block, in MV O/C protection

0.07
0.5
0.2
MV Ratio_I2/I1

setting for blocking MV
O/C protection
60
20
MV
Inrush 2nd harmonic

cross-block time for MV
T2h_Cross_Blk
O/C protection
A
0.05Ir
20Ir
LV I_OC1
LV overcurrent (O/C)
1
60
60
LV T_OC1

Stage 1
0.05Ir
20Ir
LV I_OC2
LV overcurrent (O/C)
2
60
60
LV T_OC2

Stage 2
MV Curve_OC Inv
12

307
0.05Ir
20Ir
LV I_OC Inv
307
0.05
999
LV K_OC Inv
s
200
0.14

307
264

307
LV A_OC Inv
LV B_OC Inv
60

307
Chapter 21 Appendix
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
10
Default
setting
Description
(Ir:5A/1A)
0.02
LV P_OC Inv

307
90
45
LV Angle_OC

0.25Ir
20Ir
The maximum 1st

LV
Imax_2H_UnBlk
block, in LV O/C protection

0.07
0.5
0.2
LV Ratio_I2/I1

setting for blocking LV
O/C protection
60
20
Inrush 2nd harmonic

cross-block time for LV
LV T2h_Cross_Blk
O/C protection
A
0.05Ir
20Ir
HV 3I0_EF1
HV earth fault (E/F) protection current setting for

Stage 1
60
60
HV T_EF1
Stage 1
A
0.05Ir
20Ir
HV 3I0_EF2
HV earth fault (E/F) current setting for Stage 2
60
60
HV T_EF2
Time setting for HV E/F,

Stage 2
12
HV Curve_EF Inv

307
0.05Ir
20Ir
1.2
HV 3I0_EF Inv

307
0.05
999
HV K_EF Inv

307
200
0.14
HV A_EF Inv

307
60
HV B_EF Inv

307
0
HV P_EF Inv
Time setting for HV E/F,
10
0.02

307
265
Chapter 21 Appendix
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
90
Default
setting
Description
(Ir:5A/1A)
45
HV Angle_EF

0.25Ir
20Ir
The maximum 1st

HV
Imax_2H_UnBlk_E
0.07
0.5
0.2
The maximum 1st

HV Ratio_I2/I1_EF

A
0.05Ir
20Ir
MV 3I0_EF1
MV earth fault (E/F) protection current setting for

Stage 1
60
60
MV T_EF1
Stage 1
A
0.05Ir
20Ir
MV 3I0_EF2
s
60
60
Time setting for MV E/F,

Stage 2
12
MV Curve_EF Inv

307
0.05Ir
20Ir
MV 3I0_EF Inv

307
0.05
999
MV K_EF Inv

307
200
0.14
MV A_EF Inv

307
60
MV B_EF Inv

307
10
0.02
MV P_EF Inv

307
266
MV earth fault (E/F) current setting for Stage 2
MV T_EF2
MV Angle_EF
Time setting for MV E/F,
90
45

Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.25Ir
20Ir
Default
setting
Description
(Ir:5A/1A)
5
The maximum 1st

MV
Imax_2H_UnBlk_E
F
block, in MV E/F protection

0.07
0.5
0.2
MV Ratio_I2/I1_EF

E/F protection
0.05Ir
20Ir
LV 3I0_EF1
LV earth fault (E/F) protection current setting for

Stage 1
60
60
LV T_EF1
Stage 1
A
0.05Ir
20Ir
LV 3I0_EF2
s
60
60
12

307
0.05Ir
20Ir
LV 3I0_EF Inv

307
0.05
999
LV K_EF Inv

307
200
0.14
LV A_EF Inv

307
60
LV B_EF Inv

307
10
0.02
LV P_EF Inv

307
90
45
LV Angle_EF

Time setting for LV E/F,

Stage 2
LV Curve_EF Inv
Imax_2H_UnBlk_E
LV earth fault (E/F) current setting for Stage 2
LV T_EF2
LV
Time setting for LV E/F,
0.25Ir
20Ir
The maximum 1st

block, in LV E/F protection
267
Chapter 21 Appendix
Setting
Unit
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.07
0.5
Default
setting
Description
(Ir:5A/1A)
0.2
LV Ratio_I2/I1_EF

E/F protection
0.05Ir
20Ir
HV 3I0_Neutral
HV neutral over-current
(NOC) protection current
OC1
setting for Stage 1

s
60
60
HV T_Neutral OC1
Time setting for HV NOC,

Stage 1
0.05Ir
20Ir
HV 3I0_Neutral
HV neutral over-current
OC2
setting for Stage 2

s
60
60
HV T_Neutral OC2
Time setting for HV NOC,

Stage 1
HV Curve_NOC
12
Inv

307
0.05Ir
20Ir
HV 3I0_NOC Inv

307
0.05
999
HV K_NOC Inv

307
200
0.14
HV A_NOC Inv

307
60
HV B_NOC Inv

307
10
0.02
HV P_NOC Inv

307
90
45
HV Angle_NOC

0.25Ir
20Ir
The maximum 1st

HV
Imax_2H_UnBlk_
NOC
block, in HV NOC protection

0.07
HV Ratio_I2/I1_NOC
0.5
0.2

setting for blocking HV
NOC protection
268
Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.05Ir
20Ir
Default
setting
Description
(Ir:5A/1A)
5
MV 3I0_Neutral
MV neutral over-current
OC1
setting for Stage 1

s
60
60
MV T_Neutral OC1
Time setting for MV NOC,

Stage 1
0.05Ir
20Ir
MV 3I0_Neutral
MV neutral over-current
OC2
setting for Stage 2

s
60
60
MV T_Neutral OC2
Time setting for MV NOC,

Stage 1
MV Curve_NOC
12
Inv

307
0.05Ir
20Ir
MV 3I0_NOC Inv

307
0.05
999
MV K_NOC Inv

307
200
0.14
MV A_NOC Inv

307
60
MV B_NOC Inv

307
10
0.02
MV P_NOC Inv

307
90
45
MV Angle_NOC

0.25Ir
20Ir
The maximum 1st

MV
Imax_2H_UnBlk_
NOC
block, in MV NOC protection

0.07
0.5
0.2
MV Ra-

tio_I2/I1_NOC
NOC protection
A
0.05Ir
20Ir
LV 3I0_Neutral
LV neutral over-current
OC1
setting for Stage 1

s
LV T_Neutral OC1
60
60
Time setting for LV NOC,

Stage 1
269
Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.05Ir
20Ir
Default
setting
Description
(Ir:5A/1A)
5
LV 3I0_Neutral
LV neutral over-current
OC2
setting for Stage 2

s
60
60
LV T_Neutral OC2
Time setting for LV NOC,

Stage 1
12
LV Curve_NOC Inv

307
0.05Ir
20Ir
LV 3I0_NOC Inv

307
0.05
999
LV K_NOC Inv

307
200
0.14
LV A_NOC Inv

307
60
LV B_NOC Inv

307
10
0.02
LV P_NOC Inv

307
90
45
LV Angle_NOC

0.25Ir
20Ir
The maximum 1st

LV
Imax_2H_UnBlk_
NOC
block, in LV NOC protection

0.07
0.5
0.2
LV Ra-

tio_I2/I1_NOC
NOC protection
A
0.1Ir
5Ir
HV I_Therm OL
Setting for HV-side

thermal overload
Trip
trip-stage current
A
0.1Ir
5Ir
HV I_Therm OL
Setting for HV-side

thermal overload
Alarm
alarm-stage current
s
HV T_Const
Therm
9999
10
Time const for HV-side

270
Chapter 21 Appendix
Setting
HV T_Const Cool
Unit
s
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
9999
Default
setting
Description
(Ir:5A/1A)
10
Down

HV-side thermal overload
0.1Ir
5Ir
MV I_Therm OL
Setting for MV-side

thermal overload
Trip
trip-stage current
A
0.1Ir
5Ir
MV I_Therm OL
Setting for MV-side

thermal overload
Alarm
alarm-stage current
s
9999
10
MV T_Const
Time const for MV-side

thermal overload protec-
Therm
tion
MV T_Const Cool
9999
10
Down
MV-side thermal overload

A
0.1Ir
4Ir
HV I_OverLoad
HV T_OverLoad
0.1
3600
10
0.1Ir
4Ir
Overcurrent Setting of
overload
0.1
3600
10
0.1Ir
4Ir
LV I_OverLoad
LV T_OverLoad
overload
MV I_OverLoad
MV T_OverLoad
overload
s
0.1
3600
10
0.1Ir
4Ir
20
Alarm current setting of
LW I_OvLd Alarm
LV delta winding overload

protection
s
0.1
3600
10
LW T_OvLd Alarm
Alarm time setting of LV

delta winding overload
protection
LW I_OvLd Low
0.1Ir
4Ir
20
Trip
LW T_OvLd Low
rent setting
s
0.1
3600
10
Trip
LW I_OvLd High
Trip
Low stage tripping time

setting
0.1Ir
4Ir
20
Trip
LW T_OvLd High
Low stage tripping cur-
High stage tripping current setting
0.1
3600
10
High stage tripping time

setting
271
Chapter 21 Appendix
Setting
Unit
V
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
40
200
Default
setting
Description
(Ir:5A/1A)
200
HV U_OV1
HV voltage setting for

stage 1 of overvoltage
protection
60
60
HV T_OV1
HV time setting for stage

1 of overvoltage protection
40
200
200
HV U_OV2
HV voltage setting for

protection
60
60
HV T_OV2
HV time setting for stage

0.9
0.99
0.95
HV Dropout_OV
HV dropout ratio for

40
200
200
MV voltage setting for

MV U_OV1
protection
s
60
60
MV T_OV1
MV time setting for stage

40
200
200
MV U_OV2
MV voltage setting for

protection
60
60
MV T_OV2
MV time setting for stage

0.9
0.99
0.95
MV Dropout_OV
MV dropout ratio for

0.05Ir
20Ir
Phase current setting

value for HVcircuit
HV I_CBF OC
breaker failure (CBF)

protection
A
HV 3I2_CBF NS
0.05Ir
20Ir
Negative sequence (NS)

current setting 3I 2 value for HV CBF protection
272
Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.05Ir
20Ir
Default
setting
Description
(Ir:5A/1A)
5
Zero sequence (ZS) current setting 3I 0 value
HV 3I0_CBF ZS
for HV1 CBF protection

s
32
10
HV T1_CBF
Time setting value of

Stage 1, for HV CBF
protection
0.1
32
10
HV T2_CBF

Stage 2, for HV CBF
protection
0.05Ir
20Ir
MVI_CBF OC

value for MV CBF protection
0.05Ir
20Ir

current setting 3I 2 val-
MV 3I2_CBF NS
ue for MV CBF protection

A
0.05Ir
20Ir
MV 3I0_CBF ZS

s
32
10
MV T1_CBF

Stage 1, for MV CBF
protection
0.1
32
10
MV T2_CBF

Stage 2, for MV CBF
protection
0.05Ir
20Ir
LV I_CBF OC

value for LV CBF protection
0.05Ir
20Ir

current setting 3I 2 val-
LV 3I2_CBF NS
ue for LV CBF protection

A
LV 3I0_CBF ZS
0.05Ir
20Ir

273
Chapter 21 Appendix
Setting
Unit
s
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
32
Default
setting
Description
(Ir:5A/1A)
10
LV T1_CBF

Stage 1, for LV CBF protection
0.1
32
10
LV T2_CBF

Stage 2, for LV CBF protection
HV T_Dead Zone
32
10
Time delay setting for HV

MV T_Dead Zone
32
10
Time delay setting for MV

LV T_Dead Zone
32
10
Time delay setting for LV

0.05Ir
20Ir
100
HV I_STUB
current threshold of
STUB protection
60
60
HV T_STUB
0.05Ir
20Ir
100
MV I_STUB
STUB protection
60
60
MV T_STUB
0.05Ir
20Ir
100
LV I_STUB
STUB protection
60
60
LV T_STUB
0.05Ir
20Ir
HV 3I0_PD

threshold of pole discordance protection
0.05Ir
20Ir
negative sequence current threshold of pole
HV 3I2_PD
s
60
10
HV T_PD
cordance protection
A
MV 3I0_PD
delay time of pole dis-
0.05Ir
20Ir

threshold of pole discordance protection
274
Chapter 21 Appendix
Setting
Unit
A
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
0.05Ir
20Ir
Default
setting
Description
(Ir:5A/1A)
5
MV 3I2_PD
negative sequence current threshold of pole

60
10
MV T_PD
delay time of pole discordance protection
0.05Ir
0.2Ir
0.05
HV I_VT Fail
Minimum Current of VT
failure for HV side
0.05Ir
0.2Ir
0.5
HV 3I02_ VT Fail
Minimum zero or negative Current of HV VT fail
20
HV Upe_VT Fail
Maximum phase to earth

voltage of HV VT fail
10
30
16
HV Upp_VT Fail
Maximum phase to
phase voltage of HV VT
fail
HV Upe_VT Nor-
40
65
40
mal
Minimum phase to phase

voltage of HV VT normal
0.05Ir
0.2Ir
0.05
MV I_VT Fail
failure for MV side
0.05Ir
0.2Ir
0.5
MV 3I02_VT Fail
Minimum zero or negative Current of MV VT fail
20
MV Upe_VT Fail

voltage of MV VT fail
10
30
16
MV Upp_VT Fail
Maximum phase to
phase voltage of MV VT
fail
MV Upe_VT Nor-
40
65
40
mal
voltage of MV VT normal
A
0.05Ir
0.2Ir
0.05
LV I_VT Fail
failure for LV side
0.05Ir
0.2Ir
0.5
LV 3I02_VT Fail
Minimum zero or negative Current of LV VT fail
20
LV Upe_VT Fail

voltage of LV VT fail
V
LV Upp_VT Fail
10
30
16
Maximum phase to
phase voltage of LV VT
fail
275
Chapter 21 Appendix
Setting
LV Upe_VT Nor-
Unit
V
Min.
Max.
(Ir:5A/1A)
(Ir:5A/1A)
40
65
Default
setting
40
mal

voltage of LV VT normal
0.2
T_Pulse Tripping
1.2
Description
(Ir:5A/1A)
Binary setting list

Setting
Unit
Min.
Max.
Default
setting
Description
Autotransformer not comm
on transformer
Auto Trans
1-autotransformer ;
0- not autotransformer
Two-Wind Trans
Two-winding(TWO WIND )
not three -winding trans0
former (TRANS)
1-two-winding trans;
0-three-winding trans
CT Fail Detect
Setting
Func_Inst Diff
Func_Percent Diff
Unit
Min.
Max.
Default
setting
Block Diff at Inrush
VT Failure Detection On/Off

1-On, 0-Off.
Description
Instantaneous differential
protection ON 1-on; 0-off.
Percentage differential protection ON 1-on; 0-off.
Inrush block differential pro-
tection
2nd Harm Not
2nd harmonic (HAR) inhibit
Wave
not the fuzzy recognition

0
based on the waveform(WAVE)

1-2nd harmonic on; 0waveform on
Block Diff at
Overexcit
Overexcitation block differ0
ential protection
276
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
Overexcit 3rd NOT
5th
judgement
0
3rd or 5th harmonic (HAR)

inhibit on
1-3rd harmonic; 0-5th harmonic.
Func_Diff Alarm
Differential current (DIFF)

0
Alarming on
1-on; 0-off.
Block Diff at
CT_Fail
Block differential protection

0
when there is CT failure

HV D_side Eliminate I0

0
when HV side winding is

MV D_side Eliminate I0

0
when MV side winding is

LV D_side Eliminate I0

0
when LV side winding is

Diff Includes LV
LV current is included in
Cur
calculation of the differential

0
protection.
1- Diff Includes LV Cur;
0-Diff NOT Includes LV Cur
HV Func_REF Trip

0
trip-stage ON
1-on; 0-off.
HV Func_REF
Alarm

0
Alarm-stage ON
1-on; 0-off.
Block HV REF at
HV CT_Fail
Block HV REF when CT

0
failure,
1-Block;0-unblock
MV Func_REF Trip

277
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
MV Func_REF
Alarm
Description
Alarm-stage ON
1-on; 0-off.
Block MV REF at
MV CT_Fail
Block MV REF when CT

0
failure,
1-Block;0-unblock
LV Func_REF Trip
LV Func_REF
Alarm

Alarm-stage ON
1-on; 0-off.
Block LV REF at
LV CT_Fail
Block LV REF when CT fail0
ure,
1-Block;0-unblock
HV
Func_Overexcit
MV
Func_Overexcit
LV Func_Overexcit
Func_Overexcit
Alarm Def
HV Overexcitation (V/F) on
1-on; 0-off.
MV Overexcitation (V/F) on
1-on; 0-off.
LV Overexcitation (V/F) on
1-on; 0-off.
Definite Overexcitation (V/F)
Alarming on
1-on; 0-off.
Func_Overexcit
Trip Def
Definite (DEF)Overexcitation
0
(V/F) on
1-on; 0-off.
Func_Overexcit
Trip Inv
Inverse (IVR)Overexcitation
0
(V/F) on
1-on; 0-off.
V/F Volt-
Overexcitation protection
age(0-VPP,1-VPN)
uses phase-to-phase volt0
age (VPP) or phase-to-earth

voltage (VPN)
0-VPP; 1-VPN.
HV Func_OC1
The 1st stage of HV OC

0
(OC_1) protection is
switched ON
1-on; 0-off.
278
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
HV OC1 Direction
Description
Direction (DIR) detection of
HV OC Stage 1 is switched
ON
1-on; 0-off.
HV OC1 Dir To Sys
Direction unit of HV OC
0
0 - point to the protected

transformer
1- point to system
HV OC1 Inrush
Block
Inrush 2nd harmonic detec0
tion HV OC Stage 1 is
switched ON
1-on; 0-off.
HV Func_OC2
The 2nd stage of HV OC

0
switched ON
1-on; 0-off.
HV OC2 Direction

0
HV OC Stage 2 is switched
ON
1-on; 0-off.
HV OC2 Dir To Sys
Direction unit of HV OC
0

transformer
1- point to system
HV OC2 Inrush
Block
tion HV OC Stage 2 is
switched ON
1-on; 0-off.
HV Func_OC Inv
The IDMTL inverse time

0
stage of HV OC protection is
switched ON
1-on; 0-off.
HV OC Inv Direction

0
HV OC IDMTL inverse time

is switched ON
1-on; 0-off.
279
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
HV OC Inv Dir To
Direction unit of HV OC ID-
Sys
MTL inverse time points to

0
system
transformer
1- point to system
HV OC Inv Inrush
Block
tion HV OC IDMTL inverse

time is switched ON
1-on; 0-off.
Block HV OC at
Select to block HV OC pro-
HV VT_Fail
tection or exit direction unit,

0
when HV VT fails
0- HV Direct OK at HV VT
Fail
1- Blk HV OC at HV VT Fail
HV OC Initiate LV
CBF
HV OC protection initiate LV
0
side CBF
HV OC Initiate MV
CBF
HV OC protection initiate MV
0
side CBF
MV Func_OC1
The 1st stage of MV OC

0
switched ON
1-on; 0-off.
MV OC1 Direction
0
MV OC Stage 1 is switched
ON
1-on; 0-off.
MV OC1 Dir To
Direction unit of MV OC
Sys

0

transformer
1- point to system
MV OC1 Inrush
Block
tion MV OC Stage 1 is
switched ON
1-on; 0-off.
280
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
MV Func_OC2
Description
The 2nd stage of MV OC
switched ON
1-on; 0-off.
MV OC2 Direction

0
MV OC Stage 2 is switched
ON
1-on; 0-off.
MV OC2 Dir To
Sys

0

transformer
1- point to system
MV OC2 Inrush
Block
tion MV OC Stage 2 is
switched ON
1-on; 0-off.
MV Func_OC Inv

0
stage of MV OC protection is
switched ON
1-on; 0-off.
MV OC Inv Direction

0
MV OC IDMTL inverse time

is switched ON
1-on; 0-off.
MV OC Inv Dir To
Sys
IDMTL inverse time points to

0
system
transformer
1- point to system
MV OC Inv Inrush
Block
tion MV OC IDMTL inverse

time is switched ON
1-on; 0-off.
Block MV OC at
Select to block MV OC pro-
MV VT_Fail

0
when MV VT fails
0- MV Direct OK at MV VT
Fail
1- Blk MV OC at MV VT Fail
281
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
MV OC Initiate
HV1 CBF
Description
MV OC protection initiate
HV1 side CBF

LV Func_OC1
The 1st stage of LV OC

0
switched ON
1-on; 0-off.
LV OC1 Direction
0
LV OC Stage 1 is switched
ON
1-on; 0-off.
LV OC1 Dir To Sys
Direction unit of LV OC
0

transformer
1- point to system
LV OC1 Inrush
Block
tion LV OC Stage 1 is
switched ON
1-on; 0-off.
LV Func_OC2
The 2nd stage of LV OC

0
switched ON
1-on; 0-off.
LV OC2 Direction
0
LV OC Stage 2 is switched
ON
1-on; 0-off.
LV OC2 Dir To Sys
Direction unit of LV OC
0

transformer
1- point to system
LV OC2 Inrush
Block
tion LV OC Stage 2 is
switched ON
1-on; 0-off.
LV Func_OC Inv

0
stage of LV OC protection is
switched ON
1-on; 0-off.
282
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
LV OC Inv Direction
Description
LV OC IDMTL inverse time is

switched ON
1-on; 0-off.
LV OC Inv Dir To
Direction unit of LV OC ID-
Sys

0
system
transformer
1- point to system
LV OC Inv Inrush
Block
tion LV OC IDMTL inverse

time is switched ON
1-on; 0-off.
Block LV OC at LV
Select to block LV OC pro-
VT_Fail

0
when LV VT fails
0- LV Direct OK at LV VT Fail
1- Blk LV OC at LV VT Fail
LV OC Initiate HV1
CBF
LV OC protection initiate
0
HV1 side CBF

HV Func_EF1
The 1st stage of HV earth

0
fault (EF_1) protection is

switched ON
1-on; 0-off.
HV EF1 Direction
0
HV EF Stage 1 is switched
ON
1-on; 0-off.
HV EF1 Dir To Sys
Direction unit of HV EF
0

transformer
1- point to system
HV EF1 Inrush
Block
tion HV EF Stage 1 is
switched ON
1-on; 0-off.
283
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
HV Func_EF2
Description
The 2nd stage of HV earth

switched ON
1-on; 0-off.
HV EF2 Direction

0
HV EF Stage 2 is switched
ON
1-on; 0-off.
HV EF2 Dir To Sys
Direction unit of HV EF
0

transformer
1- point to system
HV EF2 Inrush
Block
tion HV EF Stage 2 is
switched ON
1-on; 0-off.
HV Func_EF Inv

0
stage of HV EF protection is
switched ON
1-on; 0-off.
HV EF Inv Direction

0
HV EF IDMTL inverse time is

switched ON
1-on; 0-off.
HV EF Inv Dir To
Direction unit of HV EF ID-
Sys

0
system
transformer
1- point to system
HV EF Inv Inrush
Block
tion HV EF IDMTL inverse

time is switched ON
1-on; 0-off.
Block HV EF at HV
Select to block HV EF pro-
VT_Fail

0
when HV VT fails
0 - HV Direct OK at HV VT
Fail
1 - Blk HV EF at HV VT Fail
284
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Block HV EF at HV
CT_Fail
Description
Block HV EF when there is
HV CT failure
1-Block;
HV EF Initiate LV
CBF
0-NOT block
HV EF protection initiate LV
0
side CBF
HV EF Initiate MV
CBF
HV EF protection initiate MV
0
side CBF
MV Func_EF1
The 1st stage of MV earth

0

switched ON
1-on; 0-off.
MV EF1 Direction

0
MV EF Stage 1 is switched
ON
1-on; 0-off.
MV EF1 Dir To Sys
Direction unit of MV EF
0

transformer
1- point to system
MV EF1 Inrush
Block
tion MV EF Stage 1 is
switched ON
1-on; 0-off.
MV Func_EF2
The 2nd stage of MV earth

0

switched ON
1-on; 0-off.
MV EF2 Direction

0
MV EF Stage 2 is switched
ON
1-on; 0-off.
MV EF2 Dir To Sys
Direction unit of MV EF
0

transformer
1- point to system
285
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
MV EF2 Inrush
Block
Description
Inrush 2nd harmonic detec-
tion MV EF Stage 2 is
switched ON
1-on; 0-off.
MV Func_EF Inv

0
stage of MV EF protection is
switched ON
1-on; 0-off.
MV EF Inv Direction

0
MV EF IDMTL inverse time

is switched ON
1-on; 0-off.
MV EF Inv Dir To
Direction unit of MV EF ID-
Sys

0
system
transformer
1- point to system
MV EF Inv Inrush
Block
tion MV EF IDMTL inverse

time is switched ON
1-on; 0-off.
Block MV EF at
Select to block MV EF pro-
MV VT_Fail

0
when MV VT fails
0 - MV Direct OK at MV VT
Fail
1 - Blk MV EF at MV VT Fail
Block MV EF at
MV CT_Fail
Block MV EF when there is

0
MV CT failure
1-Block;
MV EF Initiate HV
CBF
0-NOT block
MV EF protection initiate
0
HV1 side CBF

LV Func_EF1
The 1st stage of LV earth

0

switched ON
1-on; 0-off.
286
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
LV EF1 Direction
Description
LV EF Stage 1 is switched
ON
1-on; 0-off.
LV EF1 Dir To Sys
Direction unit of LV EF Stage

1 points to system
0

transformer
1- point to system
LV EF1 Inrush
Block
tion LV EF Stage 1 is
switched ON
1-on; 0-off.
LV Func_EF2
The 2nd stage of LV earth

0

switched ON
1-on; 0-off.
LV EF2 Direction

0
LV EF Stage 2 is switched
ON
1-on; 0-off.
LV EF2 Dir To Sys
Direction unit of LV EF Stage

2 points to system
0

transformer
1- point to system
LV EF2 Inrush
Block
tion LV EF Stage 2 is
switched ON
1-on; 0-off.
LV Func_EF Inv

0
stage of LV EF protection is
switched ON
1-on; 0-off.
LV EF Inv Direction

0
LV EF IDMTL inverse time is

switched ON
1-on; 0-off.
287
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
LV EF Inv Dir To
Direction unit of LV EF ID-
Sys

0
system
transformer
1- point to system
LV EF Inv Inrush
Block
tion LV EF IDMTL inverse

time is switched ON
1-on; 0-off.
Block LV EF at LV
Select to block LV EF pro-
VT_Fail

0
when LV VT fails
0 - LV Direct OK at LV VT
Fail
1 - Blk LV EF at LV VT Fail
Block LV EF at LV
CT_Fail
Block LV EF when there is

0
LV CT failure
1-Block;
LV EF Initiate HV
CBF
0-NOT block
LV EF protection initiate HV1

0
side CBF
HV Func_Neu
OC1
The 1st stage of HV neutral

0
OC (OC_1) protection is
switched ON
1-on; 0-off.

0
switched ON
1-on; 0-off.
HV Neu OC1 Dir
Direction unit of HV neutral
To Sys
OC Stage 1 points to system

0

transformer
1- point to system
tion HV neutral OC Stage 1

is switched ON
1-on; 0-off.
288
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
HV Func_Neu
OC2
Description
The 2nd stage of HV neutral
switched ON
1-on; 0-off.

0
switched ON
1-on; 0-off.
HV Neu OC2 Dir
To Sys

0

transformer
1- point to system
tion HV neutral OC Stage 2

is switched ON
1-on; 0-off.
HV Func_Neu OC
Inv

0
stage of HV neutral OC protection is switched ON

1-on; 0-off.
HV Neu OC Inv
Direction
HV neutral OC IDMTL in0
verse time stage is switched

ON
1-on; 0-off.
HV Neu OC Inv Dir
To Sys
OC IDMTL inverse time

0
stage points to system

transformer
1- point to system
HV Neu OC Inv
Inrush Block
tion HV neutral OC IDMTL

0
inverse time stage is

switched ON
1-on; 0-off.
289
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
Block HV NOC at
Select to block HV neutral
HV VT_Fail
OC protection or exit direction unit, when HV VT fails

0
0 - HV Direct OK at HV VT
Fail
1 - Blk HV NOC at HV VT
Fail
HV Neu OC Init
MV CBF
HV neutral OC protection
0
initiate LV side CBF

MV Func_Neu
OC1
The 1st stage of MV neutral

0
switched ON
1-on; 0-off.

0
switched ON
1-on; 0-off.
MV Neu OC1 Dir
Direction unit of MV neutral
To Sys

0

transformer
1- point to system
tion MV neutral OC Stage 1

is switched ON
1-on; 0-off.
MV Func_Neu
OC2
The 2nd stage of MV neutral

0
switched ON
1-on; 0-off.

0
switched ON
1-on; 0-off.
MV Neu OC2 Dir
To Sys

0

transformer
1- point to system
290
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
tion MV neutral OC Stage 2

is switched ON
1-on; 0-off.
MV Func_Neu OC
Inv

0
stage of MV neutral OC
1-on; 0-off.
MV Neu OC Inv
Direction
MV neutral OC IDMTL in0

ON
1-on; 0-off.
MV Neu OC Inv Dir
To Sys

0

transformer
1- point to system
MV Neu OC Inv
Inrush Block
tion MV neutral OC IDMTL

0

switched ON
1-on; 0-off.
Block MV NOC at
Select to block MV neutral
MV VT_Fail
OC protection or exit direction unit, when MV VT fails

0
0 - MV Direct OK at MV VT
Fail
1 - Blk MV NOC at MV VT
Fail
MV Neu OC Init
MV CBF
MV neutral OC protection
0

LV Func_Neu OC1
The 1st stage of LV neutral

0
switched ON
1-on; 0-off.
291
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
LV neutral OC Stage 1 is
switched ON
1-on; 0-off.
LV Neu OC1 Dir To
Direction unit of LV neutral
Sys

0

transformer
1- point to system
LV Neu OC1 Inrush Block
tion LV neutral OC Stage 1 is

switched ON
1-on; 0-off.
LV Func_Neu OC2
The 2nd stage of LV neutral

0
switched ON
1-on; 0-off.

0
LV neutral OC Stage 2 is
switched ON
1-on; 0-off.
LV Neu OC2 Dir To
Sys

0

transformer
1- point to system
LV Neu OC2 Inrush Block
tion LV neutral OC Stage 2 is

switched ON
1-on; 0-off.
LV Func_Neu OC
Inv

0
stage of LV neutral OC protection is switched ON

1-on; 0-off.
LV Neu OC Inv
Direction
LV neutral OC IDMTL in0

ON
1-on; 0-off.
292
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
LV Neu OC Inv Dir
To Sys

0

transformer
1- point to system
LV Neu OC Inv
Inrush Block
tion LV neutral OC IDMTL

0

switched ON
1-on; 0-off.
Block LV NOC at
Select to block LV neutral
LV VT_Fail
OC protection or exit direc0
tion unit, when LV VT fails

0 - LV Direct OK at LV VT
Fail
1 - Blk LV NOC at LV VT Fail
LV Neu OC Init LV
CBF
LV neutral OC protection
0

HV Func_Thermal
OvLd
Thermal overload in HV side

0
is switched on
0 - OFF, 1 - ON
HV Cold Curve
HV side using hot/cold curve

0
type
HV Thermal Init LV
CBF
HV thermal overload protec0
tion initiate LV side CBF

HV Thermal Init
MV CBF
HV thermal overload protec0
tion initiate MV side CBF

MV Func_Thermal
OvLd
Thermal overload in MV side

0
is switched on
0 - OFF, 1 - ON
MV Cold Curve
MV side using hot/cold curve

0
type
MV Thermal Init
HV1 CBF
MV thermal overload protec0
tion initiate HV side CBF

293
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
HV
Func_OverLoad
Description
Overload (LOAD) protection
in HV side is switched ON
1-on; 0-off.
MV
Func_OverLoad
LV
Func_OverLoad
Overload (LOAD)in MV side

on
Overload (LOAD)in LV side
on
LW Func_OvLd
Alarm stage of LV delta
Alarm
winding (LWIND) overload

0
(LOAD) protection is
switched ON.
1-on; 0-off.
LW Func_OvLd
Low Trip

0

1-on; 0-off.
LW Func_OvLd
High Trip

0

1-on; 0-off.
Low Trip Init HV1

CBF

0

High Trip Init HV1

CBF

0

Low Trip Init MV

CBF

0

High Trip Init MV

CBF

0

- initiate, 1 not initiate
HV Func_OV1
HV Func_OV2
294
HV overvoltage stage 1 enabled or disabled

or alarm
Chapter 21 Appendix
Setting
HV Func_OV2
HV OV2 Trip
Unit
Default
Min.
Max.
setting
HV OV Chk PE
Description
HV overvoltage stage 2 enabled or disabled
or alarm
HV phase to phase voltage
or phase to earth measured

for overvoltage protection
MV Func_OV1
MV Func_OV2
MV Func_OV2
MV OV2 Trip
MV OV Chk PE
MV overvoltage stage 1 enabled or disabled

or alarm
MV overvoltage stage 2 enabled or disabled
or alarm
MV phase to phase voltage
or phase to earth measured

for overvoltage protection
HV Func_CBF
HV Circuit breaker failure

0

ON
1-on; 0-off.
HV 3I0/3I2 Check
On

0

current 3I0 or 3I2.
HV CB Status
Check On

0
HV1 CB status
MV Func_CBF
MV Circuit breaker failure

0

ON
1-on; 0-off.
MV 3I0/3I2 Check
On

0

current 3I0 or 3I2.
MV CB Status
Check On

0
MV CB status
295
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
LV Func_CBF
Description
LV Circuit breaker failure

ON
1-on; 0-off.
LV 3I0/3I2 Check
On
LV CBF protection detect

0

current 3I0 or 3I2.
LV CB Status
Check On
LV CBF protection detect LV

0
CB status
HV Func_Dead
Zone
Dead zone protection is

0
switched ON
1-on; 0-off.
MV Func_Dead
Zone

0
switched ON
1-on; 0-off.
LV Func_Dead
Zone

0
switched ON
1-on; 0-off.
HV Func_STUB
HV STUB Init LV
CBF

protection
STUB protection initiate LV
side CBF
HV STUB Init MV
CBF
STUB protection initiate HV

0
side CBF
MV Func_STUB
MV STUB Init LV
CBF

protection
side CBF
MV STUB Init MV
CBF
STUB protection initiate MV

0
side CBF
LV Func_STUB
LV STUB Init LV
CBF

protection
side CBF
296
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
LV STUB Init MV
CBF
Description
side CBF
MV Func_PD
MV PD Chk 3I0/3I2
MV Func_PD
MV PD Chk 3I0/3I2

criteria
criteria
HV VT Failure Detection
HV VT FAIL Detect
0
On/Off
1-On, 0-Off.
HV Earthing mode:
HV Solid Earth
0

MV VT Failure Detection
MV VT FAIL Detect
0
On/Off
1-On, 0-Off.
MV Solid Earth
MV Earthing mode:
0

LV VT FAIL Detect
LV VT Failure Detection
0
On/Off
1-On, 0-Off.
LV Earthing mode:
LV Solid Earth
0

st
To select whether the 1
st
BI1 Enable BO1
binary input (BI1) trip the 1
binary output (BO1) or not.

1-enable, 0-disable
297
Chapter 21 Appendix
Setting
Unit
Min.
Max.
Default
setting
Description
To select BO1 tripping in
pulse mode or in direct mode
BO1 Pulse Tripping
0- BO1 Direct Tripping,

without delay
1- BO1 Pulse Tripping, with
preset delay time
To select whether the 2nd
nd
BI2 Enable BO2
binary input (BI2) trip the 2
binary output (BO2) or not.

1-enable, 0-disable
To select BO2 tripping in
pulse mode or in direct mode
BO2 Pulse Tripping
0- BO2 Direct Tripping,

without delay
1- BO2 Pulse Tripping, with
preset delay time
whether BI1 initiate HV side
BI1 Init HV CBF
CBF or not
whether BI1 initiate MV side
BI1 Init MV CBF
CBF or not
whether BI1 initiate LV side
BI1 Init LV CBF
CBF or not
whether BI2 initiate HV side
BI2 Init HV CBF
CBF or not
whether BI2 initiate MV side
BI2 Init MV CBF
CBF or not
whether BI2 initiate LV side
BI2 Init LV CBF
CBF or not
298
Chapter 21 Appendix
2 General report list

Table 182 event report list
Information
Relay startup
Description
The relay is initiated by startup elements
Per Diff Trip A

Per Diff Trip B
Treble slope percent Differential protection (ID>) trip for phase A/B/C
Per Diff Trip C

Inst Diff Trip A
Inst Diff Trip B
Instantaneous Differential protection (ID>>) trip for phase A/B/C
Inst Diff Trip C

HV REF Trip
MV REF Trip
LV REF Trip
Def V/F Trip
Overexcitation protection(V/F) tripping (Trip) with definite (DEF) and
Inv V/F Trip
inverse(IVR) time characteristic
HV OC Inv Trip
Inverse time stage of HV overcurrent protection trip
HV OC1 Trip
HV OC2 Trip
MV OC Inv Trip
Inverse time stage of MV overcurrent protection trip
MV OC1 Trip
MV OC2 Trip
LV OC Inv Trip
Inverse time stage of LV overcurrent protection trip
LV OC1 Trip
LV OC2 Trip
HV EF Inv Trip
Inverse time stage of HV earth fault protection trip
HV EF1 Trip
HV EF2 Trip
MV EF Inv Trip
Inverse time stage of MV earth fault protection trip
MV EF1 Trip
MV EF2 Trip
299
Chapter 21 Appendix
Information
Description
LV EF Inv Trip
Inverse time stage of LV earth fault protection trip
LV EF1 Trip
LV EF2 Trip
HV NOC Inv Trip
Inverse time stage of neutral OC protection trip
HV NOC1 Trip
HV NOC2 Trip
MV EF Inv Trip
Inverse time stage of MV neutral OC protection trip
MV EF1 Trip
MV EF2 Trip
LV EF Inv Trip
Inverse time stage of LV neutral OC protection trip
LV EF1 Trip
LV EF2 Trip
HV Therm OL Trip
HV Thermal (TEM) Overload(OVLD) tripping (Trip)
MV Therm OL Trip
MV Thermal (TEM) Overload(OVLD) tripping (Trip)
HV OV1 Trip
HV OV2 Trip
MV OV1 Trip
MV OV2 Trip
HV CBF1 Trip
HV CBF2 Trip
HV CBF Init
Internal or external initiate HV circuit breaker failure protection
MV CBF1 Trip
MV CBF2 Trip
MV CBF Init
Internal or external initiate MV circuit breaker failure protection
LV CBF1 Trip
LV CBF2 Trip
LV CBF Init
Internal or external initiate LV circuit breaker failure protection
HV Dead Zone
HV Dead zone trip
MV Dead Zone
MV Dead zone trip
LV Dead Zone
LV Dead zone trip
HV STUB Trip
HV STUB protection trip
300
Chapter 21 Appendix
Information
Description
MV STUB Trip
MV STUB protection trip
LV STUB Trip
LV STUB protection trip
HV PD Trip
HV poles discordance protection trip
MV PD Trip
MV poles discordance protection trip
HV VT Fail
HV VT Fail alarm
MV VT Fail
MV VT Fail alarm
LV VT Fail
LV VT Fail alarm

No
Abbr. (LCD Display)
Description
Battery Off
Battery off
BI Breakdown
Binary input breakdown
BI Check Err
Binary input checking is error
BI Comm Fail
Binary input communication fail
BI Config Err
Binary input configuration is error
BI EEPROM Err
The EEPROM of binary input is error
BI Input Err
Binary input error
BI_CBF Err
Binary input error of CBF
BO Breakdown
Binary output breakdown
BO Comm Fail
Binary output communication fail
BO EEPROM Err
The EEPROM of binary output is error
BO No Response
No response of binary output
BOConfig Err
Binary output configuration is error
CB Err Blk PD
CB auxiliary contacts indicate that one

pole is open but at the same time current is
flowing through the pole.
CB Open A Err
Binary input error of CB Open A
CB Open B Err
Binary input error of CB Open B
3
4
5
6
10
11
12
13
14
15
16
301
Chapter 21 Appendix
17
CB Open C Err
Binary input error of CB Open C
18
CB Status Err
CB Status Error
19
Def V/F Alarm
Def V/F Alarm
Diff 2har Blk
Inrush detection impose a blocking condition to differential protection
Diff 3/5har Blk
3rd or 5th harmonic detection impose a

blocking condition to differential protection
Diff Cur Alarm
Differential current exceeds the threshold

value
EquipPara Err
Equipment parameter is error
FLASH Check Err
FLASH checking is error
H BI MCB VT Fail
Binary input error of VT fail of MCB
H BI_V3P_MCB Err
Binary input error of three phase MCB
HV 3U0 Alarm
HV 3U0 Alarm
HV BLK VOL REGU
Block tap changer control of transformer
HV Inrush Blk BU
a blocking condition is imposed to backup

protection by inrush condition detection
HV Load Alarm
HV Load Alarm
HV OV1 Alarm
Stage 1 of overvoltage protection alarm
HV OV2 Alarm
HV REF 3I0 Alarm
HV REF 3I0 Alarm
HV Therm OL Alm
HV Thermal Overload Alarm
HV VT Fail
HV VT Fail
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
HV1 I2 Alarm
37
HV2 I2 Alarm
38
39
40
302
Negative-sequence current exceeds a threshold

L BI MCB VT Fail
L BI_V3P_MCB Err
LV 3U0 Alarm
LV 3U0 Alarm
Chapter 21 Appendix
41
LV I2 Alarm
42
LV Inrush Blk BU

43
LV Load Alarm
LV Load Alarm
44
LV REF 3I0 Alarm
LV REF 3I0 Alarm
45
LV Therm OL Alm
LV Thermal Overload Alarm
46
LV VT Fail
LV VT Fail
47
LW Load Alarm
LW Load Alarm
M BI MCB VT Fail
M BI_V3P_MCB Err
MV 3U0 Alarm
MV 3U0 Alarm
MV BLK VOL REGU
Block tap changer control of transformer
48
49
50
51
52
MV I2 Alarm
53
54
55
56
57
58
MV Inrush Blk BU

MV Load Alarm
MV Load Alarm
MV OV1 Alarm
MV OV2 Alarm
MV REF 3I0 Alarm
MV REF 3I0 Alarm
MV Therm OL Alm
MV Thermal Overload Alarm
59
MV VT Fail
MV VT Fail
60
NO/NC Discord
NO/NC discord
61
Ph_A CT Fail
Phase A CT Fail
62
Ph_B CT Fail
Phase B CT Fail
63
Ph_C CT Fail
Phase C CT Fail
64
ROM Verify Err
ROM verifying is error
65
Sampling Err
Sampling is error
66
Set Group Err
Setting group is error
67
Setting Err
Setting value is error
68
Soft Version Err
Soft version is error
69
SRAM Check Err
SRAM checking is error
Sys Config Err
System configuration is error
70
303
Chapter 21 Appendix
71
Test BO Un_reset
Do not reset after testing binary output
72
Voltage or frequency is out of the permissible
V or F Exceed
range
Table 184 operation report list
No
Information
Description
Func_Diff On
Differential protection is switched ON (by CW)
Func_Diff Off
Differential protection is switched OFF (by CW)
HV Func_REF On
HV REF protection is switched ON (by CW)
HV Func_REF Off
HV REF protection is switched OFF (by CW)
MV Func_REF On
MV REF protection is switched ON (by CW)
MV Func_REF Off
MV REF protection is switched OFF (by CW)
LV Func_REF On
LV REF protection is switched ON (by CW)
LV Func_REF Off
LV REF protection is switched OFF (by CW)
Func_Overexc On
Overexcitation protection is switched ON (by CW)
10
Func_Overexc Off
Overexcitation protection is switched OFF (by CW)
11
12
13
14
15
16
17
18
19
20
21
304
HV Func_OC On
HV Func_OC Off
MV Func_OC On
MV Func_OC Off
LV Func_OC On
LV Func_OC Off
HV Func_EF On
HV Func_EF Off
MV Func_EF On
MV Func_EF Off
LV Func_EF On
Overcurrent protection of HV side is switched ON

(by CW)
Overcurrent protection of HV side is switched OFF
(by CW)
Overcurrent protection of MV side is switched ON
(by CW)
Overcurrent protection of MV side is switched OFF
(by CW)
Overcurrent protection of LV side is switched ON (by
CW)
Overcurrent protection of LV side is switched OFF
(by CW)
Earth fault protection of HV side is switched ON (by
CW)
Earth fault protection of HV side is switched OFF (by
CW)
Earth fault protection of MV side is switched ON (by
CW)
Earth fault protection of MV side is switched OFF
(by CW)
Earth fault protection of LV side is switched ON (by
CW)
Chapter 21 Appendix
No
22
Information
LV Func_EF Off
Description
Earth fault protection of LV side is switched OFF (by
CW)
23
HV Func_NOC On
NOC protection of HV side is switched ON (by CW)
24
HV Func_NOC Off
NOC protection of HV side is switched OFF (by CW)
25
MV Func_NOC On
NOC protection of MV side is switched ON (by CW)
26
MV Func_NOC Off
NOC protection of MV side is switched OFF (by CW)
27
LV Func_NOC On
NOC protection of LV side is switched ON (by CW)
28
LV Func_NOC Off
NOC protection of LV side is switched OFF (by CW)
29
30
31
32
HV Func_Therm On
HV Func_Therm Off
MV Func_Therm On
MV Func_Therm Off
HV thermal overload protection is switched ON (by

CW)
HV thermal overload protection is switched OFF (by
CW)
MV thermal overload protection is switched ON (by
CW)
MV thermal overload protection is switched OFF (by
CW)
33
HV Func_OL On
HV overload protection is switched ON (by CW)
34
HV Func_OL Off
HV overload protection is switched OFF (by CW)
35
MV Func_OL On
MV overload protection is switched ON (by CW)
36
MV Func_OL Off
MV overload protection is switched OFF (by CW)
37
LV Func_OL On
LV overload protection is switched ON (by CW)
38
LV Func_OL Off
LV overload protection is switched OFF (by CW)
39
HV Func_OV On
HV overvoltage protection is switched ON (by CW)
40
HV Func_OV Off
HV overvoltage protection is switched OFF (by CW)
41
MV Func_OV On
MV overvoltage protection is switched ON (by CW)
42
MV Func_OV Off
MV overvoltage protection is switched OFF (by CW)
43
HV Func_DZ On
HV DZ function on
44
HV Func_DZ Off
HV DZ function off
45
MV Func_DZ On
MV DZ function on
46
MV Func_DZ Off
MV DZ function off
47
LV Func_DZ On
LV DZ function on
48
LV Func_DZ Off
LV DZ function off
49
HV Func_STUB On
HV STUB function on
50
HV Func_STUB Off
HV STUB function Off
51
MV Func_STUB On
MV STUB function on
52
MV Func_STUB Off
MV STUB function Off
53
LV Func_STUB On
LV STUB function on
54
LV Func_STUB Off
LV STUB function Off

305
Chapter 21 Appendix
No
306
Information
Description
55
HV Func_PD On
HV poles discordance function on
56
HV Func_PD Off
HV poles discordance function off
57
MV Func_PD On
MV poles discordance function on
58
MV Func_PD Off
MV poles discordance function off
59
HV Func_VT On
HV VT failure supervision function on
60
HV Func_VT Off
HV VT failure supervision function off
61
MV Func_VT On
MV VT failure supervision function on
62
MV Func_VT Off
MV VT failure supervision function off
63
LV Func_VT On
LV VT failure supervision function on
64
LV Func_VT Off
LV VT failure supervision function off
Chapter 21 Appendix
3 Time inverse characteristic

3.1
11 kinds of IEC and ANSI inverse time

characteristic curves
In the setting, if the curve number is set for inverse time characteristic, which
is corresponding to the characteristic curve in the following tabel. Both IEC
and ANSI based standard curves are available.
Table 185 11 kinds of IEC and ANSI inverse time characteristic
Curves No.
3.2
IDMTL Curves
Parameter A
Parameter P
Parameter B
IEC INV.
0.14
0.02
IEC VERY INV.
13.5
1.0
IEC EXTERMELY INV.
80.0
2.0
IEC LONG INV.
120.0
1.0
ANSI INV.
8.9341
2.0938
0.17966
ANSI SHORT INV.
0.2663
1.2969
0.03393
ANSI LONG INV.
5.6143
2.18592
ANSI MODERATELY
INV.
0.0103
0.02
0.0228
ANSI VERY INV.
3.922
2.0
0.0982
10
ANSI EXTERMELY INV.
5.64
2.0
0.02434
11
ANSI DEFINITE INV.
0.4797
1.5625
0.21359
User defined characteristic

For the inverse time characteristic, also can be set as user defined
characteristic if the setting is set to 12.
Equation 39
307
Chapter 21 Appendix
where:
A: Time factor for inverse time stage
B: Delay time for inverse time stage
P: index for inverse time stage
K: Set time multiplier for step n
CT Requirement
4.1
Overview
In practice, the conventional magnetic- core current transformer (hereinafter
as referred CT) is not able to transform the current signal accurately in whole
fault period of all possible faults because of manufactured cost and installation space limited. CT Saturation will cause distortion of the current signal
and can result in a failure to operate or cause unwanted operations of some
functions. Although more and more protection IEDs have been designed to
permit CT saturation with maintained correct operation, the performance of
protection IED is still depended on the correct selection of CT.
4.2
Current transformer classification

The conventional CTs are usually manufactured in accordance with the
standard, IEC 60044, ANSI / IEEE C57.13, ANSI / IEEE C37.110 or other
comparable standards, which CTs are specified in different protection class.
Currently, the CT for protection are classified according to functional performance as follows:
Class P CT
Accuracy limit defined by composite error with steady symmetric primary
current. No limit for remanent flux.
Class PR CT
CT with limited remanence factor for which, in some cased, a value of the
secondary loop time constant and/or a limiting value of the winding resistance may also be specified.
Class PX CT
Low leakage reactance for which knowledge of the transformer secondary excitation characteristic, secondary winding resistance, secondary
burden resistance and turns ratio is sufficient to assess its performance
in relation to the protective relay system with which it is to be used.
308
Chapter 21 Appendix
Class TPS CT
Low leakage flux current transient transformer for which performance is
defined by the secondary excitation characteristics and turns ratio error
limits. No limit for remanent flux
Class TPX CT
Accuracy limit defined by peak instantaneous error during specified transient duty cycle. No limit for remanent flux.
Class TPY CT
Accuracy limit defined by peak instantaneous error during specified transient duty cycle. Remanent flux not to exceed 10% of the saturation flux..
Class TPZ CT
Accuracy limit defined by peak instantaneous alternating current component error during single energization with maximum d.c. offset at
specified secondary loop time constant. No requirements for d.c. component error limit. Remanent flux to be practically negligible.
TPE class CT (TPE represents transient protection and electronic type
CT)
4.3
Abbreviations (according to IEC 60044-1, -6, as

defined)
Abbrev.
Description
Esl
Rated secondary limiting e.m.f
Eal
Rated equivalent limiting secondary e.m.f
Ek
Rated knee point e.m.f
Uk
Knee point voltage (r.m.s.)
Kalf
Accuracy limit factor
Kssc
Rated symmetrical short-circuit current factor
Kssc
Effective symmetrical short-circuit current factor
Kssc
based on different Ipcf
Kpcf
Protective checking factor
Ks
Specified transient factor
Kx
Dimensioning factor
Ktd
Transient dimensioning factor
Ipn
Rated primary current
Isn
Ipsc
Rated primary short-circuit current
Ipcf
protective checking current
Isscmax
Maximum symmetrical short-circuit current
309
Chapter 21 Appendix
Rct
Secondary winding d.c. resistance at 75 C /

167 F (or other specified temperature)
Rb
Rated resistive burden
Rb
= Rlead + Rrelay = actual connected resistive

burden
Rs
Total resistance of the secondary circuit, inclusive of the secondary winding resistance corrected to 75, unless otherwise specified, and
inclusive of all external burden connected.
Rlead
Wire loop resistance
Zbn
Rated relay burden
Zb
Actual relay burden
Tp
Specified primary time constant
Ts
Secondary loop time constant
4.4
General current transformer requirements
4.4.1
Protective checking current

The current error of CT should be within the accuracy limit required at specified fault current.
To verify the CT accuracy performance, Ipcf, primary protective checking
current, should be chose properly and carefully.
For different protections, Ipcf is the selected fault current in proper fault position of the corresponding fault, which will flow through the verified CT.
To guarantee the reliability of protection relay, Ipcf should be the maximum
fault current at internal fault. E.g. maximum primary three phase short-circuit
fault current or single phase earth fault current depended on system sequence impedance, in different positions.
Moreover, to guarantee the security of protection relay, Ipcf should be the
maximum fault current at external fault.
Last but not least, Ipcf calculation should be based on the future possible
system power capacity
Kpcf, protective checking factor, is always used to verified the CT performance
To reduce the influence of transient state, Kalf, Accuracy limit factor of CT,
310
Chapter 21 Appendix
should be larger than the following requirement
Ks, Specified transient factor, should be decided based on actual operation

state and operation experiences by user.
4.4.2
CT class
The selected CT should guarantee that the error is within the required accuracy limit at steady symmetric short circuit current. The influence of short
circuit current DC component and remanence should be considered, based
on extent of system transient influence, protection function characteristic,
consequence of transient saturation and actual operating experience. To fulfill the requirement on a specified time to saturation, the rated equivalent
secondary e.m.f of CTs must higher than the required maximum equivalent
secondary e.m.f that is calculated based on actual application.
For the CTs applied to transmission line protection, transformer differential
protection with 330kV voltage level and above, and 300MW and above generator-transformer set differential protection, the power system time constant
is so large that the CT is easy to saturate severely due to system transient
state. To prevent the CT from saturation at actual duty cycle, TP class CT is
preferred.
For TPS class CT, Eal (rated equivalent secondary limiting e.m.f) is generally
determined as follows:
Where
Ks: Specified transient factor
Kssc: Rated symmetrical short-circuit current factor
For TPX, TPY and TPZ class CT, Eal (rated equivalent secondary limiting
e.m.f) is generally determined as follows:
311
Chapter 21 Appendix
Where
Ktd: Rated transient dimensioning factor
Considering at short circuit current with 100% offset
For C-t-O duty cycle,
t: duration of one duty cycle;

For C-t-O-t fr -C-t-O duty cycle,
t: duration of first duty cycle;

t: duration of second duty cycle;
t fr : duration between two duty cycle;
For the CTs applied to 110 - 220kV voltage level transmission line protection,
110 - 220kV voltage level transformer differential protection, 100-200MW
generator-transformer set differential protection, and large capacity motor
differential protection, the influence of system transient state to CT is so less
that the CT selection is based on system steady fault state mainly, and leave
proper margin to tolerate the negative effect of possible transient state.
Therefore, P, PR, PX class CT can be always applied.
For P class and PR class CT, Esl (the rated secondary limited e.m.f) is generally determined as follows:
Kalf: Accuracy limit factor

For PX class CT, Ek (rated knee point e.m.f) is generally determined as follows:
Kx: Demensioning factor

For the CTs applied to protection for110kV voltage level and below system,
the CT should be selected based on system steady fault state condition. P
class CT is always applied.
312
Chapter 21 Appendix
4.4.3
Accuracy class
The CT accuracy class should guarantee that the protection relay applied is
able to operate correctly even at a very sensitive setting, e.g. for a sensitive
residual overcurrent protection. Generally, the current transformer should
have an accuracy class, which have an current error at rated primary current,
that is less than 1% (e.g. class 5P).
If current transformers with less accuracy are used it is advisable to check
the actual unwanted residual current during the commissioning.
4.4.4
Ratio of CT
The current transformer ratio is mainly selected based on power system data
like e.g. maximum load. However, it should be verified that the current to the
protection is higher than the minimum operating value for all faults that are to
be detected with the selected CT ratio. The minimum operating current is
different for different functions and settable normally. So each function
should be checked separately.
4.4.5

There are 2 standard rated secondary currents, 1A or 5A. Generally, 1 A
should be preferred, particularly in HV and EHV stations, to reduce the burden of the CT secondary circuit. Because 5A rated CTs, i.e. I2R is 25x compared to only 1x for a 1A CT. However, in some cases to reduce the CT
secondary circuit open voltage, 5A can be applied.
4.4.6
Secondary burden
Too high flux will result in CT saturation. The secondary e.m.f is directly
proportional to linked flux. To feed rated secondary current, CT need to
generate enough secondary e.m.f to feed the secondary burden. Consequently, Higher secondary burden, need Higher secondary e.m.f, and then
closer to saturation. So the actual secondary burden Rb must be less than
the rated secondary burden Rb of applied CT, presented
Rb > Rb
The CT actual secondary burden Rb consists of wiring loop resistance
Rlead and the actual relay burdens Zb in whole secondary circuit, which is
calculated by following equation
313
Chapter 21 Appendix
Rb = Rlead + Zb
The rated relay burden, Zbn, is calculated as below:
Where
Sr: the burden of IED current input channel per phase, in VA;
For earth faults, the loop includes both phase and neutral wire, normally
twice the resistance of the single secondary wire. For three-phase faults the
neutral current is zero and it is just necessary to consider the resistance up to
the point where the phase wires are connected to the common neutral wire.
The most common practice is to use four wires secondary cables so it normally is sufficient to consider just a single secondary wire for the three-phase
case.
In isolated or high impedance earthed systems the phase-to-earth fault is not
the considered dimensioning case and therefore the resistance of the single
secondary wire always can be used in the calculation, for this case.
4.5
Rated equivalent secondary e.m.f requirements

To guarantee correct operation, the current transformers (CTs) must be able
to correctly reproduce the current for a minimum time before the CT will
begin to saturate.
4.5.1
Transformer differential protection

It is recommended that the CT of each side could be same class and with
same characteristic to guarantee the protection sensitivity.
For the CTs applied to 330kV voltage level and above step-down transformer,
TPY class CT is preferred for each side.
For the CTs of high voltage side and middle voltage side, Eal should be verified at external fault C-O-C-O duty cycle.
For the CT of low voltage side in delta connection, Eal should be verified at
external three phase short circuit fault C-O duty cycle.
Eal must meet the requirement based on following equations:
Where
Ktd: Recommended transient dimensioning factor for verification, 3
314
Chapter 21 Appendix
recommended
For 220kV voltage level and below transformer differential protection, P
Class, PR class and PX class is able to be used. Because the system time
constant is less relatively, and then DC component is less, the probability of
CT saturation due to through fault current at external fault is reduced more
and more.
For P Class, PR class CT, Esl can be verified as below:
Where
Ks: Specified transient factor, 2 recommended
For PX class CT, Ek can be verified as below:
Where
Ks: Specified transient factor, 2 recommended
315

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CSC-326

Transformer Protection IED

Compiled: Jin Rui

is registered trademark of Beijing Sifang Automation Co., Ltd.

Instructions for mounting and commissioning;

Compilation of the technical specifications;

Applicability of this Manual

Strictly follow the company and international safety regulations.

Do not touch any circuitry during operation. Potentially lethal

Never connect or disconnect wire and/or connector to or from IED

Always connect the IED to protective earth regardless of the

Do not disconnect the secondary connection of current transformer

Do not remove the screw from a powered IED or from an IED

Using the certified conductive bags to transport PCBs (modules).

Do not connect live wires to the IED, internal circuitry may be

When replacing modules using a conductive wrist strap connected to

When installing and commissioning, take care to avoid electrical

2 Protection principle .......................................................................................................... 136

6 Report ............................................................................................................................... 180

About this chapter

Used in a wide range of voltage levels, up to 1000kV

For single or multi-breaker arrangement

Up to 7 three-phase sets of CTs input (special ordering)

Communication with station automation system

Protection and monitoring IED with extensive functional library, user

Inter-lock between two CPU modules, avoiding mal-operation due to

Transformer differential protection (87T)

Treble slope percent differential protection

Automatic CT ratio matching

Automatic vector group and zero sequence current compensation

Settable 2nd harmonic restraint function for transformer inrush

Fuzzy waveform recognition restraint function for transformer

3rd or 5th harmonic restraint for overexcitation

Differential current alarm

Restricted earth fault protection (87N)

Two slope percent REF protection

Automatic CT ratio matching

REF differential current supervision

Positive sequence current blocking

A complete protection functions library, include:

Transformer differential protection (87T)

Restricted earth fault protection (87N)

Overcurrent protection (50, 51, 67)

Earth fault protection (50N, 51N, 67N)

Neutral earth fault protection (50G, 51G, 67G)

Thermal overload protection (49)

Overload protection (50OL)

Delta winding overload protection (50OL)

Overexcitation protection (24)

Overvoltage protection (59)

Circuit breaker failure protection (50BF)

Poles discordance protection (50PD)

Dead zone protection (50SH-Z)

Voltage transformer secondary circuit supervision (97FF)

Current transformer secondary circuit supervision

2 sets external trip commands (BIs BOs)

Self-supervision to all modules in the IED

Complete information recording: tripping reports, alarm reports,

Up to three electric /optical Ethernet ports can be selected to

Up to two electric RS-485 ports can be selected to communicate with

Time synchronization via network(SNTP), pulse and IRIG-B mode

Configurable LEDs and output relays satisfied users requirement

Versatile human-machine interface