Power Estimation Tool for Sub-Micron CMOS VLSI Circuits

F. Rouatbi, B. Haroun, A. J. Al-Khalili

Departmentof Electrical Engineering, Concordia University
1455 de Maisonneuve Blvd. W., Montreal, QuebecH3G lM8

Abstract

information on resistanceand capacitanceis presentedin

[3], thesecurrent waveforms are generatedby analyzing
a simple RC circuit that fails to give a good
approximation for the current waveforms for complex
CMOS gates.Recently, a current model for CMOS gates
has been presented in [121. In this work the supply
current is estimated by collapsing a CMOS gate to an
equivalent inverter. Then the supply current is estimated
basedon a pre-characterizedcurrent model. The current
model is basedon 3 time regions. The current estimates
are fitted using exponential functions which are
inherently difficult to use in event driven simulation.
Our work presentsa new approach to overcome the
limitations described above. Our approach is based on
event driven simulation using an accurate delay model,
combined with a detailed piece-wise linear analytical
current model to closely approximate supply current
waveforms during switching of a complex CMOS gate.
Our model is particularly suitable for event driven
simulation, which is widely used for analyzing CMOS
circuits. The organization of this paper is as follows,
Section 2 presents event driven current simulation. In
section 3 we present current estimation in a CMOS gate
using collapsing. Section 4 describes our analytical
current and delay model. Section 5 comparesthe results
of our approach with SPICE level 3 and presents
examples of current simulation. Section 6 summarizes
our work.
2. Event Driven Simulation
Event driven simulation is particularly suitable for
fast current estimation in CMOS circuits, because the
current flows in a CMOS gate only during switching of
the gate.Therefore the current can be viewed as the sum
of all gate supply current waveforms. In an event driven
simulation the circuit is dynamically divided into stages
[l] [lo]. A timing analysis of the circuit is performed.
The results of the timing simulation are combined with
the estimation of supply current waveforms in each
stage to estimate the total supply current as shown in
Fig. 1. The main issue in the event driven simulation is
the accurate delay current alignment in multi-stage

Accurate and fast time-domain current waveform

simulation is important for the design of reliable CMOS
VLSI circuits. Previous approaches for switch level current
simulations used simple current models that did not match
accurately the supply current. In this paper, we present a
detailed current model that resulted in a maximum of 10%
deviation from the current waveforms as obtained by
SPICE LEVEL 3, at peak values and 5% on the average
current. Our current model accounts for short-channel
effects, input rise times, short-circuit and dynamic current
and circuit topology. Moreover, our model produces piecewise linear current waveforms and hence can be easily
incorporated in any switch-level simulator. Using our
models in an event driven simulator we achieved 3-4
orders of magnitude speed-up relative to SPICE LEVEL 3.
Our results for- current waveform accuracy outperform
previously published methods and in particular for
complex CMOS circuits.

1. Introduction
Different work has been done to develop fast current
simulators and keep an acceptableaccuracy.A peak current
estimator is developed in [l][lll. The simulator deal with
the problem at three levels of hierarchy, gate level, macro
level and power/ground distribution level. A gate is
collapsed into an equivalent inverter and simulated using
numerical analysis. A branch an bound algorithm is usedto
estimate the peakcurrent in a macro, which can be 50%
higher than SPICE estimates.Another technique to reduce
the simulation time is to usean event driven simulator such
as that used in [21 143.The current at the gate level is
estimatedfrom a database,but including all the factors that
affects the supply current i.e. input rise/fall time, output
capacitance, transistor sizes, input transitions etc., will
increase the database size and the computational
complexity. Also, the databasemethod does not handle
circuits with pass-gates,becausethe stagedecompositionis
static and corresponds to gates in the library. While in
circuits with pass-gates the stage decomposition is
dependenton the inputs [lo]. A current analysis tool that
interrogates a switch-level mode simulator and extracts

204
O-8186-3010-8/92 $03.00 0 1992 IEEE

3.1 Current estimation using collapsing to multigates

Our model is basedon basic time-domain current waveforms shown in Fig. 3 to estimate the capacitive and
short-circuit current. These waveforms are then combined using EQ. 1 to estimate the supply current. We
havedeterminedthrough careful analysis and simulation
that 4 basic waveforms cover all the capacitive current
possibilities derived with input transitions and node
capacitancesvalues. One waveform cover the short circuit current. The stages of the CMOS system are
simplified by collapsing into 3 different gatesto estimate
the parametersincluded in thesewaveforms. The analytical model is derived from the collapsed circuits. Current
estimation in a stage(High to Low transition) is summarized in the following steps:
l- The pull-up network is replaced with an equivalent
transistor.
2- The trigger transistor is determined.
3- The shortest(least number transistors) on path P in
the pull-down from the output node to the ground is
determined(ex. Fig. 4).
4- All parallel/seriesnetworks of on transistors in parallel with any transistor included in P are collapsed into
an equivalent transistor (Fig. 4). The result of this step is
a network of series-connectedMOS transistors (SCM).
5- SCM is collapsed in 2 gates.a) Gate I, to estimatethe
capacitive current surgedue to switching, b) Gate 2 used
to estimate the capacitive current waveform (Fig. 4).
Two different gates are used for the capacitive current
estimation, because its not possible to accurately
estimatethe waveform from a single equivalent circuit.
6- Stageis collapsed into an equivalent inverter (Gate 3,
Fig. 4) to estimateI~,,, delay and output rise/fall time.
7- Supply current is determinedby combining capacitive
and short-circuit current waveforms using EQ.l.
3.2 Issues when Collapsing a CMOS Gate
To achieve good accuracy in delay and current we
addressedthe following issuesfor the collapsed circuit:
1- We ensureDelay equivalenceof the collapsed gate by
determining the equivalent transconductanceas in [6].
2- Body effects of seriesconnectedtransistors are taken
into account. 3- Charge equivalence with the original
gate by determining all initial voltages. 4- All switched
node capacitances are added when collapsing, their
individual contributions are assumednot dependenton
their position in the topology. S- In caseof multiple input
transitions occur, a time window from the time the first
path to ground is createduntil the time the output node is
completely switched. If there are input transitions in that
time window, the network is collapsed again eachtime a
new path is set by thesedelayed transitions.

circuits. As a consequencewe need accurate current

models at the stage level, specifically the peak current
and its timing and the averagecurrent. Furthermore the
current waveforms should be quick to compute in an
event driven simulation, hence the need for piece-wise
linear analytical models.

Fig. 1 Event Driven simulation

3. Current Estimation at the Stage Level
The supply current flows in a CMOS gate only
during the transition of the output node, Fig. 2 showsthe
currents during the switching of a CMOS gate from high
to low (low to high is symmetrical). The trigger input is
defined as the transistor that triggers the charging or
discharging of the output node. The supply current
during switching of a CMOS stagehastwo components,
the capacitive current lcap and the short-circuit current
I sbrr. The short-circuit current is in general less than
20% of the total current and is dependenton the load
[7][8]. In the case of a High to low transition C, is
chargedand C,, is dischargedso the supply current is the
sum of the short-circuit current and the fraction of the
capacitive current neededto charge Cp.
Supply current
Vdd &

Trigget

Trigger

+I Cl8
Supply current
High to low transition (similarly for L to H)

I
SUPPYHL(LH))

5 (4
=I shorf + ( cn + cp) Lp

CEQ.l)

Fig. 2 Currents in a CMOS Gate During Switching

205

Level :I
I&

fhirnFbe
s

Waveform l-a

WIfveform l-b

Collapsed

Gate 1 to estimate

capacitive

current

surg

-b.

time
Irm 2-b
Capacitive current
Waveform selection table

time

Fig. 3 Basic capacitive and short-circuit current

waveforms used in our model
4. Analytical Current Model
Analytical current expressionsare determined from
the collapsed gates of Fig. 4. Also the delay and output
rise/fall time are determined. We only present here our
analytical model for short-channel transistors based on
the device model in [9]. First we develop a current model
for an ideal step input where the short-circuit current is
zero, then we build on that model to include ramp input
effectsand the short-circuit current.
Step input
The capacitive current is modelled based on 3 time
segments(Fig. 6). These time segmentscorrespond to
the behavior of SCM circuits.
Segment1 (t,), When the trigger transistor is switched
on a current surgeIhit occurs due to the switching. The
value of the current surgedependson the trigger position
(waveform a or b of Fig. 3). Tl starts in the saturation
and all transistors from T2 to Tn are in the linear region.
The voltages V2 to 6-1 (t$ to V,), in Fig. 5 and 6, will fall
(rise) until they reach a plateau value. Segment 1 ends
when the node voltages V2 to V,, are within 1% of their
plateau values (Fig. 6). At that moment (ts) the currents
through the node capacitancesare almost zero and the
node voltages are almost constant.

time
Collapsed

Gate 3 to estimate

short-circuit

current

Fig. 4 Collapsing

time

Fig. 5 Capacitive current

206

Segment 2 (to), the capacitive current is almost constant.

segment 2 ends when Tl gets out of saturation and is

omitted for small loads (waveform 2, Fig. 3).
Segment 3 (tr), Tl to Tn are in the linear mode and Icap
drops to 0.
We have resolved analytically all cases but in this paper
wepresent waveform 1 (Fig. 3). The other waveforms are
derived similarly [I4]. Our analytical current model is,

more comprehensivethan the model presentedin [5][6]

for delay only. In this section we proposeto determine a
piece-wiselinear analytical current model approximation
of the capacitive current in SCMs. The capacitive current
(IMP) is equal to the sum of all the currents in the node
capacitances. The initial current surge Iha after
switching is determined from collapsed gate I of Fig. 4.
The current from the transistors above the trigger is
neglected in the estimation of the current surge (lini,).
This approximation is valid for fast inputs and gives an
acceptableestimatefor practical input rise and fall times.
The rest of the capacitive current waveform is
determined from collapsed gate 2 (Fig. 4).
Analytical derivation of time-current points
The current-time points of the capacitive current are
determined from collapsed gate 2 (Fig.4, Fig.7). To
estimate ICoP we resolve the node equations. These
equations, when Tl is still in saturation (segment l&2),
lead to an analytical solution. Given the complexity of
these equations (Fig. 7). we used a symbolic software
package (Maple [25]) to solve for the model parameters
as given in Table 1. When Tl gets out of saturation, a
direct solution of the current waveform is not possible.
To resolve this problem, we determine the chargelost by
the circuit during segment1 & 2. Since we know the total
charge before the switching, we subtract the charge lost
during segment 1 & 2 to obtain the charge during
segment 3. Then the current during segment 3 is
determined from the charge as a linear decay while
preserving current continuity. This solution ensures
charge preservation and results in accurate average
currents.
1

c/p node

time

Spice

Waveform

c cl
Fig. 6 Capacitive current model
Input ramp effects
We based our model strategy for a ramp input on the
model derived for a step input (Fig. 8). The capacitive
current waveform current-time points are affected by the
input rise time as shown in Fig. 8. The initial current
surgelinir and its timing t- are recalculated to include
the input rise time using the short channel model with an
approachsimilar to that in [7] for a long-channel inverter
with a ramp input. The output voltage of collapsed gate 3
(fig. 4) is derived analytically in the sameway and used
to estimate the short-circuit current, output rise/fall time
and delay. These complex equations are derived using
Maple and are numerical evaluated to estimate the shortcircuit current and the delay. Few time steps (3-30) are
usually required for practical rise and fall times. This
allows accurate short-circuit estimation especially for
circuits with large loads like I/O pad drivers.

_ _
node 1
c

Current equations during Segment I&2 :

4,
e9udl

>

Id1 - Id2

Idl = ~v,,,C,,W,

(DO - T -

pef,co*w2

node 2

I&=

2(t)

effr
c

&

dr

(I)

[DD

(t)

-"4~2(N*2(d

1+-

-IdI

E&efn

Fig. 7 Equivalent gate to estimate the capacitive current

Short-channel model paramters [9]; vmr : Carrier drift velocity saturation,
P Lff : effedive mobility; C,, : Gate capacitance per unit aTea,
Ler:

l-a

Effective channel length; Le Electrical channel length.

207

EC,

f = 1+
V

Saturation
voltage

_ y2 (,)

_ vT

DD

v d3a, =

(1 - 4

(,,

- 4

Tigger
input

-1
I
litit
r
I

Table 1: Waveform 1 parameters

Expression

IPar.

(00

init

Iinif
I
n

I*

Sameasstepinput

f (0.99~2~)

t,

I I

AQ1 AQl=Cl(h[v2(o)l

-rh[o.yJ)

-0.99~~~

da = kl (Ve- y2ss)

4ivs

-klVe+k,k3+k2k3Vcf

zss =

= Cl (VDD-

wtime

-cequ[v2(o)

&I

(-2k,+k2k3)

Vdr;r-Avl)lldss

AQ2 = Idssta
I

I I

Fig.ti Modelling strategy for an input ramp

5. Model Verification
Our models were tested on different complex
CMOS circuits. Good agreement with SPICE level 3
was achieved and some of the results are shown in Fig.
9, 10,ll. Fig. 9 shows the % difference in average and
peak current with SPICE for a 5 input NAND gate. For a
PAD driver Fig. 10, handling large capacitanceby our
model is shown. To demonstratemulti level logic, a 4
bit look-ahead adder with I/O pads is shown in Fig. 11.
Our model showed a maximum 5% deviation from
SPICE on the average current, and a maximum 10%
deviation on the maximum current for several circuits.
Table 2 shows a comparison between our approach and
SPICE execution time, the speed-up is expected to
increasewith larger circuits.
6. Conclusion
In this paper we presented a novel approach to
model the supply current waveforms in CMOS VLSI
circuits. Based on piece-wise linear current waveforms
our model takes into account different factors that affect
the current waveforms. Our analytical model can be
appended to any switch-level simulator to obtain
accurate supply current waveforms. A new collapsing
strategy is presented to model the supply current more
accurately. Our approach showed a good agreement
with SPICE for different circuits and achieved a speedup of 3 to 4 orders of magnitude over SPICE.

, =

"cl3 = einiriaf-

2AQ3/ldrs

(AC+ +aQ2)
I

Functions

vl=h(v2)=-Av2/kg-E1fn(-v2+v2ssl)/k3Av2ss
+B21n (- v2 + vzss2) Ik3AvzFs + Cte
== iSd-hdfrom

llv2=

m (v2) =In(2klVek3+

vDD-avN

2k1Vev2-

DD

2klv2k3 - 2ktv;
-2k2k3v2Vc + k2k&)

C= (kfV; + 2eVek3 - 2k1Vck2k3Ve + kf4

+ 2k1k;k2Vc + $k;V;
a=kfV;

+ 2<V,k3

- 2k1Vek2k3Vc

+ kf$
+ 2k, k;k2Vc

g ( v2) = atanh ( (-kl

- 2kl Vegk2 ) In

+ k@,

- 2kl V&k2

+ k2k3) v2 + kt V, - k1 kg - k2k3Vc)

Constants
b is determined from v2 1t = o= VDD Ll

Ksa,Coxl

vc

vDD-

qn

VT,

C WIL
cJJ ox 2
DD

e//z

in EQ. 2

k3

= EcLeffl

-yT.

threshold linear reg. ; aVTnthreshold saturation ; a factor 0.5 to 1

I
C

(I= --

k2=p

aTN

kl

-P

; B1=-Vek3

V Y
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k3v2.wl

+ Ll

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208

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c 2.~2 + 32~~2

+ irs2

References

10.00
SM
6.00
8 4.00

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6 2.00
$ 0.00
2::
* -6.cQ
-s.oo
Eizl
Load capacitance(fP)

Load capacitance(fF)
a- Average current

b- Peak curmt

Fig. 9 Corn araison with SPICE for

a s-input nand gate
o.su kchmlogy

ENABIE

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PAD
,OAD

E\ *:
k
:

.. ... ...........

Lmd=lpF
,

Load=SpF

10.00
5.00
Time (ns)

0.00

15.00

Fig. 10 A 4m-A I/O pad driver

Y x 10-3
3.50
3.00

Ii

,
#,

3s 2so
2.00-

1 spice
:

Model
,.......

,,

@
5 1.50$l.oo3 0.50 -

20.M)
Tie (ns)

Fig. 11 A cl-bit carry look-ahead adder with

I/O pad drivers

209