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Clock Domain Crossing Synchronization

Faiq Khalid Lodhi

11/28/2015

Faiq Khalid Lodhi

Outline
Introduction

Clock Domain Crossing


Synchronization Problems

Basic Synchronizers
Level Synchronizers
Edge Detection Synchronizers
Pulse Generating Synchronizers

Advanced Synchronizers
Low Latency Synchronizer
Digital Phase Detector

Comparison
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Clock Domain Crossing

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Why Synchronization ?
Clock Skew
Original Clock

Un Skewed Clock

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Positive
NegativeSkewed
SkewedClock
Clock

Faiq Khalid Lodhi

Why Synchronization ?
Clock Jitter
Original Clock

Clock Jitter

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State of the Art Synchronizers


Basic Synchronizers
Level Synchronizers
Edge Detection Synchronizers
Pulse Generating Synchronizers
Advanced Synchronizers
Low Latency Synchronizers
Digital Phase Detector

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Faiq Khalid Lodhi

Basic Synchronizers
Level Synchronizers
Heart of all synchronizers
Consists of two flip-flops connected back to back

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Basic Synchronizers
Edge Detection Synchronizers
Consists of a level synchronizer with an additional flip-flop at its output
Detects rising or falling edge of the clock and generates a clock wide pulse
at the output

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Faiq Khalid Lodhi

Basic Synchronizers
Pulse Generating Synchronizers
Consists of a toggle circuit whose output passes through the level
synchronizer and is XORed with a one clock cycle delayed version of
the output of level synchronizer

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Faiq Khalid Lodhi

Basic Synchronizers
Problems
Extra latency introduced by a synchronizer present at receivers end
Adaptive synchronizer
It calculates phase difference between the local clock and the ready signal
and it places the data at the center of the clock cycle
Extra Delay

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Advanced Synchronizers

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Low Latency Synchronizer


Local
Clock

Delay Block
Generates delayed Local Clocks

Selection
Block

Delayed
Signals

Remote
Clock

Bank of DFF

Synchronized
Clock

Selects the Most


Synchronized phase of
the Local Clock to avoid
the Metastable output

Samples the remote Clock

Sampled
Signals

Selection
signals

Decision Maker
It is Combinational Logic which
gives the selection signals to the
Selection Block

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Low Latency Synchronizer


Sampling

SR

D1

D2

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D1 D2

D1 D2
Faiq Khalid Lodhi

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Low Latency Synchronizer


Sampling Criteria

T/2
For Process Variation

thold + tsetup

tfz

tfz/2

Forbidden Zone
tfz
D1

SR

tfz
D2

D3

tfz
D4

tfz = tsetup + thold = 25ps

D5

D1

To incorporate the process and temperature variations we take

of DFF
25ps
tfz = 2*tsetup
(=:tsetup
setuptime
+ thold
) = =50ps
thold: hold time of DFF = 0ps

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Low Latency Synchronizer


Sampling Criteria
333ps
T/2

D1

SR

D2

fz
tfz = t50ps

D3

D4

D5

D1

+118
< <
156

< <
we took the
valueand
+average

that is 136ps
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Low Latency Synchronizer


Decision Block
TABLE:1 DECISION MAKERS TRUTH TABLE (RISING EDGE)
Case #
A1
A2
A3
A4
A5
Decision
1
X
1
1
0
0
S2
2
0
X
1
1
0
S3
3
0
0
X
1
1
S4
4
1
0
0
X
1
S5
5
1
1
0
0
X
S1
TABLE:1 DECISION MAKERS TRUTH TABLE (FALLING EDGE)
Case#
A1
A2
A3
A4
A5
Decision
X=1
X=0
6
X
0
0
1
1
S5
S4
7
1
X
0
0
1
S1
S5
8
1
1
X
0
0
S2
S1
9
0
1
1
X
0
S3
S2
10
0
0
1
1
X
S4
S3

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Low Latency Synchronizer


Problems
Extra Latency
Extra power
It can detect only 5 phases of the clock

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Digital Phase Detector


Local
Clock

Delay Block
Generates delayed Local Clocks

Selection
Block

Delayed
Signals

Remote
Clock

Bank of DFF

Synchronized
Clock

Selects the Most


Synchronized phase of
the Local Clock to avoid
the Metastable output

Samples the remote Clock

Sampled
Signals

Selection
signals

Decision Maker
It is Combinational Logic which
gives the selection signals to the
Selection Block

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Digital Phase Detector


Sampling Criteria
T/2
For Process Variation

thold + tsetup

tfz/2

Forbidden Zone
tfz
D1

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tfz
D2

D3

D4

tfz = tsetup + thold = 25ps

tsetup: setup time of DFF = 25ps


thold: hold time of DFF = 0ps
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Digital Phase Detector


Sampling Criteria

333ps
T/2

tfz
tfz = 25ps

D1

D2

D3

D4

<60
>
we take
2(N 70ps
1)
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Digital Phase Detector


Selection Criteria
Local Clock

Remote Clock

tfz

D1
1

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D2
1

D3
1

D4
X

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Digital Phase Detector


Selection Criteria
Local Clock

Remote Clock

tfz
D1
0

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D2
0

D3
0

D4
X

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D2
1

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Digital Phase Detector


Selection Criteria
CASE#

A1

A2

A3

A4

Output

Minterm

Selection

Y1

D3

Y2

D2

Y3

D1

Y4

D4

Y5

D3

Y1

Y2

Y3

Y4

Y5

Y6

Y6

D2

Y7

Y7

D1

Y8

Y8

D4

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Digital Phase Detector


Selection Criteria

CASE#

MINTERM

Selection

Mutually Exclusive
minterms

Mutually Exclusive
minterms

Y1,Y2

D3

Y1,Y8

D3

Y1 = A2.A3.A4

Y2 = A1.A2.A3

Y3,Y2

D1

Y3,Y4

D4

Y5,Y4

D3

Y3 = A1.A2.A4

Y4 = A1.A3.A4

Y5 = A2.A3.A4

Y6 = A1.A2.A3

Y5,Y6

D3

Y7 = A1.A2.A4

Y8 = A1.A3.A4

Y7,Y6

D1

Y7,Y8

D4

CASE#

A1

A2

A3

A4

Output

Selection

Y1

D3

Y2

D2

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Sample Vector [ 1 1 1 1]
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Comparison
Operating Frequency = 1GHz
Synchronizers

Maximum operating
Frequency (GHz)

Latency
(ps)

Energy
(mJ)

Energy Delay
Product (pJs)

Level synchronizer

1.1

890

3.41

3.035

Edge detecting synchronizer

1.0

960

3.50

3.360

Pulse synchronizer

1.0

990

3.62

3.584

Low Latency Synchronizer

1.1

877

3.27

2.867

Digital Phase Detector

1.7

560

3.26

1.825

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Questions

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Basic Synchronizers
CDC Module 1

CDC Module 2

Partial Handshake Protocol II

Two Clocks

Two Clocks

One Clock

Two Clocks

One Clock

4
Minimum clock cycles
required for burst mode
data
communication
e.g. 1000 Clock Cycles

One Clock

Two Clocks

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Partial Handshake Protocol I

Full Handshake Protocol

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