International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882

Volume 4, Issue 8, August 2015

CHARACTERIZATION OF HAFNIUM OXIDE FILM DEPOSITED USING

ATOMIC LAYER DEPOSITION SYSTEM
Dr. R.K KHOLA
Professor (ELECTRONICS DEPARTMENT)
Suresh Gyan Vihar University, Jaipur
Rajasthan (India)

PRAVEEN CHAUDHARY
M. Tech Student ( ELECTRONICS DEPARTMENT)
Suresh Gyan Vihar University, Jaipur
Rajasthan (India)

Abstract

II.

EXPERIMENTAL

The responsibility of increasing the efficiency of

crystalline silicon solar cells depended on the
understanding and optimization of each single
processing step, as well as coactions between the
processing conditions and the material properties. This
work considers rear surface passivation of crystal silicon
solar cells using hafnium oxide. In this work firstly we
do deposition of hafnium oxide on the wafer surface
using Atomic layer deposition technique (Hafnium oxide
has high K value due to which less leakage current flow
through passivating layer). After deposition of
passivation layer of HfO2 we characterized it using
different techniques; itself includes, XRD, CV,
Impedance and Life time measurements.

In this experiment first of all we polish wafers, polished

wafer undergo RCA cleaning and 1 minute dip in diluted
hydro fluoric acid solution to remove native oxide, after
cleaning wafer undergoes rinse for minute to clean wafer
surface [1] . The ALD deposition parameters and the
thickness of the oxide are collected in table 1.1 below.
Thickness of the oxide is determined from Ellipsometry
measurements. The film is found to be uniform with
thickness variation of 2 over a wafer of 4 dia.
TABLE 1.1DEPOSITION CONDITIONS

KeywordsAtomic layer deposition;nano layer

deposition; ; X ray diffraction;Annealing; Capacitance
voltage; impedance.

0.96
300

Thickness of oxide

30nm

ALD process

Thermal

In order to decrease the interface trap sand the fixed

charges, the as-deposited films are annealed [7] in
nitrogen atmosphere at different temperature.

III.

RESULTS AND DISCUSSION

Comparison of physical properties

1. XRD Results:
XRD plot of as deposited hafnium oxide
.
B
1000000

100000

10000

1000

130

To meet future power demand constraints, Hafnium

based (high dielectric constant) crystalline silicon cell in
addition with metal oxide gate electrode are implanted
for fulfillment of passivating layer of silicon solar cell
Passivation of the surface enhances the overall cell
efficiency by prolonging the charge-carrier effective
lifetime. Surface passivation by ALD is beneficial on
both the front and rear surface of an n-type wafer.
Hafnium oxide is an potential alternative of alluminium
oxide(allumina) and silicon dioxide. H2O and tetrakis
(ethylmethylamino) hafnium (TEMAHf) are used as the
oxidant and the hafnium precursor [2] .In this experiment
we use ALD process to deposit uniform nano layer of
hafnium oxide over silicon substrate, we use different
type of wafer at different deposition temperature.The
HfO2films are annealed with rapid thermal process in
nitrogen atmosphere. The impurities and composition of
the films are analyzed using xrd, cv characterization
techniques.

Deposition rate
No. of cycles

200

INTRODUCTION

TableColumnHead

amplitude

I.

TableHead

100

20

40

60

angle(2theta)

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100

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 8, August 2015

c
b
a
20

40

60

80

100

angle(2 theta)

Figure 1.1: a) XRD plot of as deposited hafnium oxide

b)XRD plots of HfO2 at different annealing temperatures;
a) 600C, b) 700C c) 1200C
The structural evolution of the oxide with temperature
was analyzed by x-ray diffraction. From the comparison
of two figures 1.1 (a) and 1.1(b) it is clear that as
deposited oxide is amorphous. Only the silicon
diffraction lines are observed in the figure 1.1(a).
Hafnium oxide film changes from amorphous to
crystalline structure with monoclinic phases after
annealing at different temperatures. The annealed
samples exhibit reflections at different angles. The peaks
are indexed by comparing with standard diffraction data
of INTERNATIONAL CENTRE OF DIFFRACTION
DATA file no 006-0318. The peaks are found to be
corresponding to monoclinic hafnium oxide. After
annealing at 750C the amorphous structure changes to
monoclinic structure and large number of peaks show
that it is polycrystalline. Large number of small
reflections is observed for the sample annealed at 700C
for 10min. Nucleation of other growth directions have
appeared at this annealing temperature.
2. Lifetime Measurement:
Figure 1.2 shows injection level dependent effective
carrier lifetime of n-type c-Si passivated at both faces by
70nm HfO2 thin film in both as deposited and sintered
states plotted with excess carrier concentration measured
in both transient and quasi steady state modes depending
on the lifetime value range. The effective lifetime eff is
taken to be the value at injection level of 1015/cm3. The
decrease or increase in the value below or above this
concentration is due to trapping or recombination. The
value increased from 26s to 270s due to post
deposition annealing. There is a clear indication of
increase of one order in the lifetime value after annealing.
Using the effective lifetime value, we calculate the

The value decreased from 625cm/s to 58cm/s with

annealing. Table shows the lifetime and maximum SRV
values of both as deposited and annealed symmetrically
passivated n-Si sample. The values show that HfO2
provides very good surface passivation after a post
deposition passivation anneal at 400C in N2 ambient.
The values also agree with those reported in the
literature.
From the figure, the decrease in the lifetime values for
injection levels above 1016/cm3 is due to auger
recombination and that below is due to SRH
recombination at the bulk or at the surface. The samples
do not show a very strong dependence on injection level.
It has been reported that HfO2 films on c-Si contain
positive fixed charges with a density of 1012/cm2
elementary charge. This origin of built in charges can be
attributed to the oxygen vacancies which are the
dominant intrinsic defects. The positive fixed charges are
particularly beneficial for passivating n-Si because they
repel the bulk minority charge carriers from the surface
and consequently reduce the recombination rate.
1E-3

1E-4

tau(sec)

-213

131

-321

220
221 130

102

-111
111
200
-121

relative intensity

maximum surface recombination velocity using the

formula[6] which is given by

1E-5

n hfo2 rca sint back side

n hfo2 70 cycle back
1E14

1E15

1E16

excess carrier concentration

Figure1.2: Injection level dependence life time of n-Si

with both the faces passivated with HfO2; a) as deposited
b) Sintered at 400C in N2 ambient.
SRV= w/2tau
w=wafer thickness which is equal to 325 m.
Tau= effective carrier lifetime, 279s for annealed, 26s
for as deposited sample

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 8, August 2015

Table 1.2 SRV of n type hafnium oxide

sintering.
Sample type
Effective lifetime
(s)
As deposited
26
Sintered
279

before and after

SRV (cm/sec)
58
625

Electrical properties
3. Capacitance-Voltage Characteristics:

-8

1.0x10

As Deposited
Sintered

-9

Capacitance(F)

8.0x10

Table 1.3: C V parameters of hafnium oxide layer

Parameter
Value(as
Value(sintered)
deposited)
8E11
Interface states
density (Dit)
3.8E12
Fixed
oxide 8.02x1011 -3.8x1011 C
charge (Qf)
C
.67V
Flat band voltage
(VFB)
-0.74V
4.8nF
Oxide
capacitance(Cox) 7.9nF
.1V
Hysteresis loop
width (VH)
1V
-8

1.0x10
-9

6.0x10

a
-9

8.0x10
-9

Capacitance (F)

4.0x10

-9

2.0x10

0.0
-6

-4

-2

Voltage(volt)

-9

6.0x10

-9

4.0x10

-9

2.0x10

Figure 1.3: CV plot of hafnium oxide

b
0.0

To relate the passivation quality of all the oxides with

lifetime, MIS structures were measured using high
frequency C-V technique. Figure 1.3 shows the high
frequency C-V plots of the as deposited as well as
annealed sample. Oxide capacitance (Cox), flatband
voltage (VFB), fixed oxide charge (QF) interface states
density (Dit) and Hysteresis loop width (VH) are
collected below in table 1.3. Oxide capacitance is taken
to be the maximum capacitance in the far accumulation
region. For some of the capacitors, the breakdown
strength was too low to apply sufficient bias to reach far
accumulation. For sintered films, there is deterioration in
the CV curves, possibly because of some interdiffusion
between the oxide and the substrate. The measured lower
value of oxide capacitance as compared to expected value
must be due to formation of a low dielectric constant
interface layer may be SiOx.

-5

Gate Voltage (V)

Figure 1.4: Figure describing calculation of flatband

voltage; a) Capacitance of as deposited HfO2/n-Si, b)
1/C2 vs V, c) double derivative of 1/C2 vs V curve, the
maxima in the depletion region indicates the flatband
voltage.
Visualisation of C-V curves gives a glimpse of VFB, type
of QF and hysteresis VH. Flat band voltage was
calculated using method described in the literature [3,4].
The method is based on plotting (COX/CMOS)2 vs VG
and finding the maxima in its second derivative. The
method is described in the figure for as deposited
HfO2/n-Si. Hysteresis causes a shift of VFB in C-V
characteristics which can be explained on the basis of
their direction. Negative shift in VFB was observed for
all the samples. Hysteresis is due to slow movement of
mobile charges in the oxide at or near the
oxide/semiconductor interface. Hysteresis is generally
undesirable in CMOS devices and must be minimized as
it causes instability in threshold voltage. It was found that

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 8, August 2015

post deposition annealing reduces hysteresis. Substantial

hysteresis width suggests that HfO2 film might have
larger interfacial layer. Positive and negative fixed oxide
charges can be predicted from the flatband voltage shift
VFB. It is to be noted that VFB is different from that
of hysteresis. The former decides the amount and sign of
fixed charge whereas the later denotes to the motion of
mobile ions present in the oxide. VFB refers to the
difference in the measured flatband voltage for a single
sweep from that expected for an ideal capacitor.
Hysteresis refers to the flatband shift arising from C-V
voltage sweeps in opposite polarities. Using the flat band
voltage shift, the fixed oxide charge is calculated using
the following formula (neglecting the influence of
interface trapped charge) [3,4]:

Where ms is the metal semiconductor work function

difference and Cox is the oxide capacitance in the far
accumulation region.ms is taken as -0.22V for n-Si with
Al as gate electrode and impurity concentration of
1015/cm3. The values of fixed charge for as deposited
HfO2 was determined to be 8.02x1011 and -3.8x1011
coulomb in the as deposited and sintered state
respectively. This can be correlated to the increase in
lifetime values after sintering. The source of fixed charge
is believed to originate from the bonding of the atoms
associated with the dielectric near the interface.
Conductance measurements
A number of methods exist for the determination of
interface traps density (Dit). One very common method is
based on the measurement of equivalent parallel
conductance as a function of bias with frequency as
parameter or conductance in a wide range of frequency
with bias as parameter. Because conductance arises
solely from the steady state loss due to the capture and
emission of carriers by interface states and is thus a more
direct measure of this [3,4]. The trap levels capture or
emit majority carriers when their occupancy in the band
gap changes which can be achieved by small variations in
gate bias voltage. This method is particularly suitable for
a wide range of frequency except for very low or very
high frequency at which the interface trap levels respond
immediately or they do not respond at all respectively.
The conductance method gives Dit in the depletion and
weak inversion region. Dit and conductance are related
by the expression [3,4];

Where Gp is the equivalent parallel conductance, Dit is

the density of interface states, q is the elementary charge
of electron, is the angular frequency, and it is the time
constant of the traps. This equation assumes that interface
states are distributed in a small region across the band
gap of Si. Measurement of parallel conductance as well
as function of frequency for certain DC biases voltage in
depletion or as function of bias with frequency as
parameter can determine the density of interface traps.
Conductance measurements were performed in a range of
frequencies at different voltages ranging from inversion
to accumulation region and in a range of voltage at a
fixed frequency. The equivalent parallel conductance Gp
can be extracted from the measured conductance and
capacitance using the formula [3,4];

And
are the measured parallel conductance and
capacitance and Cox is the oxide capacitance. This
equation
does not take into account any series resistance effect.
Fig 1.5 shows the conductance-frequency curves of all
the capacitors biased in the depletion and weak inversion
region. As can be seen, for each gate bias voltage the
Gp/ vs curve shows a peak and the peak position
shifts towards higher frequencies with increasing applied
bias voltage. This implies that the traps are distributed in
energy in the silicon band gap. The peak exists because at
this point, charges at the interface of silicon/oxide layer
contribute to total charging current.
Further the conductance-frequency curves at different
biases in the depletion region help in determining the
density the trap levels. The data furnishes densities at a
particular energy. Further, at this peak;
.and
this condition gives
and hence an approximate
equation for interface states density is [3,4].

Where A is the area of the gate contact .The value of Dit

averaged over the midgap region for as deposited and
sintered samples are found to be 3.8E12 and 8E11
respectively. Thisclearly indicates a decrease of one order
of magnitude in its value after sintering. Dit is known to
change by an order of magnitude or more in the region
between flatband and mid gap. On the accumulation side
of the flatband majority carrier effects dominate and
therefore give an indication of an increasingly high value
of for Dit.

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 8, August 2015

indicate positive fixed charge in the as deposited state

whereas it is negative in the sintered state. Hysteresis
loop width is less in the sintered state. Interface trap
level
density
determined
from
conductance
measurements showed decrease in its value after
annealing. The value of lifetime, fixed charge density
and interface trap level density are in good agreement
with each other to show an optimal passivation by some
atomic layers of HfO2.

n_hfO2_as dep
(a)

-6

10

-7

10

-2
-0.8V
-0.6V
-0.4V
-0.2V
0
0.2
0.4
0.6
0.8
1.2
2.2
2.2V

-8

10

-9

Gp/(F)

10

-10

10

-11

10

-12

10

-13

10

Future scope:
It is desirable to have quantitative fitting of data which
may be done in future .Only after this it will be
integrated with silicon solar cell processing and will
come out with the final device.

-14

10

10

10

10

10

10

10

10

10

10

(Hz)

Fig: 1.5 Conductance plots of a) as deposited HfO2/n-Si

n_hfo2_sint
(b)

-9

10

-10

Gp/(F)

10

-2V
-1V
0V
0.5V
1V
2V

-11

10

-12

10

10

10

10

10

10

10

(Hz)

Fig: 1.6 Conductance plots of a) as deposited and b)

sintered HfO2/n-Si .

IV. CONCLUSION AND FUTURE SCOPE

Conclusion:
In conclusion we have demonstrated the passivation of
c-Si by thin layer of HfO2 deposited by thermal ALD
technique. The films are found to be uniform over a
larger area. The oxide is characterized by X-ray
diffraction measurement, lifetime measurement,
Capacitance-Voltage, conductance measurement and
impedance measurement. XRD results indicate evolution
of crystalline phase after sintering at higher
temperatures. Large number of reflections in the
spectrum after sintering at 700oC indicates that the oxide
is polycrystalline. Lifetime measurement showed
increased in an order of magnitude in the effective value
after sintering at 400oC in N2 ambient with a value of
270s corresponding to SRV of 58cm/s which is a good
indication of surface passivation. C-V measurements

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10.1063/1.2191434.
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device characterization / by Dieter K. Schroder.p. cm
ISBN-13: 978-0-471-73906-7
[5] Nian Zhan, K. L. Ng, Hei Wong, C. W. Kok,Effects
of Rapid Thermal Annealing on the Interface and Oxide
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Microelectronics
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science
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(1992).
[8] Dennis M. Hanusmann, Roy G. Gord Surface
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