Beruflich Dokumente
Kultur Dokumente
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
2 Applications
3 Description
The AFE4490 is a fully-integrated analog front-end
(AFE) that is ideally suited for pulse-oximeter
applications. The device consists of a low-noise
receiver channel with a 22-bit analog-to-digital
converter (ADC), an LED transmit section, and
diagnostics for sensor and LED fault detection. The
device is a very configurable timing controller. This
flexibility enables the user to have complete control of
the device timing characteristics. To ease clocking
requirements and provide a low-jitter clock to the
device, an oscillator is also integrated that functions
from an external crystal. The device communicates to
an external microcontroller or host processor using an
SPI interface.
The device is a complete AFE solution packaged in a
single, compact VQFN-40 package (6 mm 6 mm)
and is specified over the operating temperature range
of 40C to 85C.
Device Information(1)
PART NUMBER
PACKAGE
AFE4490
VQFN (40)
6.00 mm 6.00 mm
Simplified Schematic
Rx Supply
(2.0 V to 3.6 V)
Rx
LED2 Data
LED2
+
CPD
+
Stage 2
Gain
TIA
AMBLED2
+
Buffer
ADC
LED1
AFE
SPI
SPI Interface
AMBLED1
Photodiode
Diagnostic
PD Open or Short
Timing
Controller
Cable Off
LED Open or Short
LED
Driver
LED
Diagnostic Signals
Digital Filter
Filter
LED Current
Control
DAC
OSC
AFE
Tx Supply
(3.0 V or 5.25 V)
8 MHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
6
6
8
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.2
8.3
8.4
8.5
8.6
27
28
43
52
56
93
93
93
93
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (June 2014) to Revision H
Page
Changed V(ESD) parameter specification values in Absolute Maximum Ratings table ........................................................... 8
Updated AFE Register Description section to current standards: added legend and bit settings to each bit register ........ 59
Page
Added Applications and Implementation, Power Supply Recommendations, and Layout sections....................................... 1
Changed VCM row in Pin Functions table: changed INM to INN in VCM description ........................................................... 7
Changed Absolute Maximum Ratings table: changed first five rows and added TXP, TXN pins row ................................... 8
Changed I-V Transimpedance Amplifier, VO(shield) parameter: changed test conditions and added minimum and
maximum specifications ...................................................................................................................................................... 11
Changed Example value for rows t, t2, t4, t5, t7, t11, t13, t15, t17, t19, t22, t24, t26, and t28 in Table 2 ......................................... 36
Added last two sentences to NUMAV[7:0] description in CONTROL1: Control Register 1 ................................................. 72
AFE4490
www.ti.com
Page
Changed VLED footnote and added VHR footnote to Recommended Operating Conditions table .......................................... 9
Changed Figure 77 (changed TXP and TXN pin names, deleted LED 1 and LED 2 pin names) ....................................... 50
Page
Changed 2.3 mA to 2.3 mW in 4th sub-bullet and changed 250 s to 4 ms in 5th sub-bullet of Receive Channel with
High Dynamic Range Features bullet..................................................................................................................................... 1
Changed Rx, Tx supplies and deleted 5-V supply from front-page graphic........................................................................... 1
Changed Tx Power Supply column in Family and Ordering Information table ...................................................................... 6
Changed Performance, PRF parameter minimum specification in Electrical Characteristics table ..................................... 10
Changed PRF = 1300 Hz to PRF = 1200 Hz in test conditions for the Performance, Total integrated noise current
and NFB parameters in Electrical Characteristics table......................................................................................................... 10
Changed Ambient Cancellation Stage, Gain parameter in Electrical Characteristics table ................................................. 11
Added last two Low-Pass Filter parameters to Electrical Characteristics table ................................................................... 11
Changed CF to C and added TX_REF capacitor to Functional Block Diagram graphic ...................................................... 27
Added last paragraph and Table 1 to Ambient Cancellation Scheme section ..................................................................... 31
Changed corresponding register column description in rows t13, t15, t17, and t19 and example column values for rows
t22, t24, t26, and t28 in Table 2................................................................................................................................................. 36
Deleted supply voltage range from RX_ANA_SUP and RX_DIG_SUP in Figure 65........................................................... 39
Added first paragraph of AFE Output Mode (ADC Bypass Mode) section .......................................................................... 47
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Added last sentence to the AFE SPI Interface Design Considerations section ................................................................... 55
Changed note within CLKALMPIN[2:0] (bits D[11:9]) description of CONTROL1 register .................................................. 72
Changed 001 and 011 bit settings for the STG2GAIN[2:0] bits (bits D[10:8]) in the TIA_AMB_GAIN register ................... 75
Changed description and name of bits D16 and D10 in CONTROL2 register..................................................................... 77
Page
Changed descriptions of RX_ANA_SUP, RX_DIG_SUP, and TX_CTRL_SUP pins in Pin Descriptions table ..................... 7
Added External Clock, External clock input voltage and External clock input current parameters to Electrical
Characteristics table ............................................................................................................................................................. 12
Added Supply Current, ADC bypass mode parameter to Electrical Characteristics table ................................................... 13
Page
Changed first two sub-bullets of Receive Channel with High Dynamic Range Features bullet ............................................. 1
Changed Performance, Total integrated noise current and NFB parameters in Electrical Characteristics table .................. 10
Changed first row of Receiver Functional Block Level Specification, Total integrated noise current parameter in
Electrical Characteristics table ............................................................................................................................................. 10
Changed Ambient Cancellation Stage, Gain parameter specifications in Electrical Characteristics table........................... 11
Changed Transmitter, Transmitter noise dynamic range parameter in Electrical Characteristics table............................... 11
Added External Clock, External clock input frequency parameter to Electrical Characteristics table.................................. 12
Added Timing, Wake-up time from Rx power-down and Wake-up time from Tx power-down parameters to Electrical
Characteristics table ............................................................................................................................................................. 12
Changed typical specification in first row and unit in second row of Power Dissipation, PD(q) parameter in Electrical
Characteristics table ............................................................................................................................................................. 14
AFE4490
www.ti.com
Changed Power Dissipation, After reset LED_DRV_SUP typical specification in Electrical Characteristics table .............. 14
Changed Power Dissipation, With stage 2 mode enabled LED_DRV_SUP, TX_CTRL_SUP, and RX_DIG_SUP
typical specifications in Electrical Characteristics table........................................................................................................ 14
Deleted Figure 11, Input-Referred Noise Current vs PLETH Current (BW = 5 Hz, PRF = 5000 Hz) .................................. 18
Deleted Figure 17, Input-Referred Noise Current vs PLETH Current (BW = 20 Hz, PRF = 5000 Hz) ................................ 19
Deleted Figure 23, Noise-Free Bits vs PLETH Current (BW = 5 Hz, PRF = 5000 Hz)........................................................ 20
Deleted Figure 29, Noise-Free Bits vs PLETH Current (BW = 20 Hz, PRF = 5000 Hz)...................................................... 21
Changed corresponding register column description in rows t24, t26, and t28 in Table 2 ...................................................... 36
Changed description of LED Power Reduction During Periods of Inactivity section ........................................................... 42
Changed last paragraph of AFE Analog Output Mode (ADC Bypass Mode) section .......................................................... 49
Changed description of bits D[15:0] in ALED2STC, ALED2ENDC, and LED1STC registers .............................................. 61
Changed description of bits D[15:0] in ALED1STC, ALED1ENDC, and LED2CONVST registers ...................................... 64
Changed description of bits D[15:0] in LED1CONVST, LED1CONVEND, and ALED1CONVST registers ......................... 67
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Tx POWER
SUPPLY (V)
OPERATING
TEMPERATURE
RANGE
3 to 5.25
40C to 85C
PRODUCT
PACKAGE-LEAD
LED DRIVE
CONFIGURATION
AFE4490
VQFN-40
Bridge, push-pull
AFE4400
VQFN-40
Bridge, push-pull
50
3 to 5.25
0C to 70C
AFE4403
WCSP-36
Bridge, push-pull
100
3 to 5.25
20C to 70C
RX_ANA_GND
RX_ANA_SUP
XIN
XOUT
RX_ANA_GND
RXOUTP
RXOUTN
RX_ANA_SUP
RX_DIG_GND
RX_DIG_SUP
RHA Package
VQFN-40
(Top View)
40
39
38
37
36
35
34
33
32
31
28
ADC_RDY
VCM
27
SPISTE
(1)
26
SPISIMO
DNC
25
SPISOMI
BG
24
SCLK
VSS
23
PD_ALM/ADC Reset
TX_REF
22
LED_ALM
DNC
10
21
DIAG_END
DNC
11
12
13
14
15
16
17
18
19
20
AFE_PDN
RX_DIG_GND
RX_ANA_GND
LED_DRV_SUP
RESET
LED_DRV_SUP
29
LED_DRV_GND
TXP
INP
TXN
CLKOUT
LED_DRV_GND
30
LED_DRV_GND
TX_CTRL_SUP
INN
AFE4490
www.ti.com
Pin Functions
PIN
NAME
(1)
NO.
FUNCTION
DESCRIPTION
ADC_RDY
28
Digital
AFE_PDN
20
Digital
BG
Reference
CLKOUT
30
Digital
DIAG_END
21
Digital
DNC (1)
5, 6, 10
INN
Analog
INP
Analog
LED_DRV_GND
12, 13, 16
Supply
LED_DRV_SUP
17, 18
Supply
LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the
large LED current, which is drawn by this supply pin.
LED_ALM
22
Digital
PD_ALM/ADC Reset
23
Digital
RESET
29
Digital
RX_ANA_GND
3, 36, 40
Supply
RX_ANA_SUP
33, 39
Supply
RX_DIG_GND
19, 32
Supply
RX_DIG_SUP
31
Supply
RXOUTN
34
Analog
RXOUTP
35
Analog
SCLK
24
SPI
SPISIMO
26
SPI
SPISOMI
25
SPI
SPISTE
27
SPI
TX_CTRL_SUP
11
Supply
TX_REF
Reference
TXN
14
Analog
TXP
15
Analog
VCM
Reference
VSS
Supply
XOUT
37
Digital
XIN
38
Digital
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
0.3
0.3
0.3
0.3
Analog inputs
RX_ANA_GND 0.3
RX_ANA_SUP + 0.3
Digital inputs
RX_DIG_GND 0.3
RX_DIG_SUP + 0.3
0.3
Minimum [6,
(LED_DRV_SUP + 0.3)]
mA
Momentary
50
mA
Continuous
mA
85
125
40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited to
10 mA or less.
MAX
UNIT
60
150
1000
1000
250
250
Tstg
V(ESD)
Electrostatic discharge
(1)
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
AFE4490
www.ti.com
MAX
UNIT
SUPPLIES
RX_ANA_SUP
2.0
3.6
RX_DIG_SUP
2.0
3.6
TX_CTRL_SUP
3.0
5.25
LED_DRV_SUP
5.25
0.3
0.3
40
85
TEMPERATURE
(1)
(2)
(3)
VHR refers to the required voltage headroom necessary to drive the LEDs. See Table 6 for the appropriate VHR value.
VLED refers to the maximum voltage drop across the external LED (at maximum LED current) connected between the TXP and TXN pins
(in H-bridge mode) and from the TXP and TXN pins to LED_DRV_SUP (in the common anode configuration).
VCABLE refers to voltage drop across any cable, connector, or any other component in series with the LED.
(1)
RHA (VQFN)
UNIT
40 PINS
RJA
35
RJC(top)
31
RJB
26
JT
0.1
JB
N/A
RJC(bot)
N/A
(1)
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIN_FS
RF = 10 k
50
RF = 25 k
20
RF = 50 k
10
RF = 100 k
RF = 250 k
RF = 500 k
RF = 1 M
PRF
DCPRF
CMRR
0.5
62.5
A
5000
SPS
25%
75
dB
95
dB
100
dB
106
dB
PSRR
PSRRLED
75
dB
PSRRTx
60
dB
PSRR, receiver
60
dB
36
pARMS
13
pARMS
14.3
Bits
13.5
Bits
1.4
pARMS
pARMS
PSRRRx
NFB
(1)
NFB = log 2
IPD
6.6 INOISE
where: IPD is the photodiode current, and INOISE is the input-referred RMS noise current.
10
AFE4490
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain
RF = 10 k to RF = 1 M
Gain accuracy
VOD(fs)
VO(shield)
V/A
7%
Feedback resistance
RF
RF
Feedback capacitance
CF
CF
7%
5, 10, 25, 50, 100, and 250
pF
20%
Set internally
10
0.8
0.9
0.9
1000
pF
1.0
Gain
dB
10
LOW-PASS FILTER
Low-pass corner frequency
Pass-band attenuation, 2 Hz to 10 Hz
3-dB attenuation
0.5 and 1
kHz
0.004
dB
0.041
dB
28
ms
16
ms
ANALOG-TO-DIGITAL CONVERTER
Resolution
Sample rate
22
See the ADC Operation and Averaging Module
section
4 PRF
SPS
1.2
See the ADC Operation and Averaging Module
section
50
Bits
V
PRF / 4
s
tCLK
TRANSMITTER
0, 50, 75, 100, 150, and 200
(see the LEDCNTRL: LED Control
Register for details)
5%
Bits
110
dB
110
dB
50
LED_ON = 0
LED_ON = 1
50
mA
0.5%
11
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIAGNOSTICS
EN_SLOW_DIAG = 0
Start of diagnostics after the DIAG_EN register
bit is set.
End of diagnostic indicated by DIAG_END going
high.
ms
EN_SLOW_DIAG = 1
Start of diagnostics after the DIAG_EN register
bit is set.
End of diagnostic indicated by DIAG_END going
high.
16
ms
> 100
< 10
< 100
Diagnostics current
INTERNAL OSCILLATOR
fCLKOUT
CLKOUT frequency
DCCLKOUT
MHz
50%
With an 8-MHz crystal connected to the XIN and
XOUT pins
200
EXTERNAL CLOCK
Maximum allowable external clock jitter
External clock input frequency
External clock input voltage
50
10%
ps
MHz
0.75 RX_DIG_SUP
0.25 RX_DIG_SUP
1000
ms
TIMING
Wake-up time from complete power-down
Wake-up time from Rx power-down
100
1000
ms
tRESET
ms
tDIAGEND
CLKOUT
cycles
tADCRDY
CLKOUT
cycles
VIL
IIN
VOH
VOL
0.75 RX_DIG_SUP
0.25 RX_DIG_SUP
0.1
V
A
RX_DIG_SUP 0.1
V
0.1
12
nA
AFE4490
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
0.6
mA
0.7
mA
RX_DIG_SUP = 3.0 V
0.27
mA
RX_ANA_SUP + RX_DIG_SUP
(Excluding external ADC current)
1.8
mA
LED_DRV
_SUP
55
TX_CTRL
_SUP
15
220
220
Complete power-down
(using AFE_PDN pin)
Power-down Rx alone
Power-down Tx alone
13
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER DISSIPATION
PD(q)
2.84
mW
0.1
mW
TX_CTRL_SUP
RX_ANA_SUP
RX_DIG_SUP
0.1
TX_CTRL_SUP
RX_ANA_SUP
15
RX_DIG_SUP
20
50
TX_CTRL_SUP
15
RX_ANA_SUP
220
RX_DIG_SUP
220
LED_DRV_SUP
Power-down with the
PDNAFE register bit
LED_DRV_SUP
Power-down Rx
LED_DRV_SUP
Power-down Tx
TX_CTRL_SUP
600
230
55
TX_CTRL_SUP
15
RX_ANA_SUP
600
RX_DIG_SUP
230
55
TX_CTRL_SUP
15
RX_ANA_SUP
700
RX_DIG_SUP
270
RX_ANA_SUP
RX_DIG_SUP
LED_DRV_SUP
After reset, with 8-MHz
clock running
LED_DRV_SUP
With stage 2 mode
enabled and 8-MHz
clock running
14
AFE4490
www.ti.com
tSCLK
tSTECLK
TYP
MAX
UNIT
MHz
62.5
ns
10
ns
tCLKSTEH,L
10
ns
tSIMOSU
10
ns
tSIMOHD
10
ns
tSOMIPD
17
ns
tSOMIHD
0.5
tSCLK
tCLK
XIN
tSTECLK
SPISTE
tSPICLK
tCLKSTEH
31
SCLK
23
tCLKSTEL
tSIMOHD
tSIMOSU
SPISIMO
A7
A6
A1
A0
tSOMIHD
tSOMIPD
tSOMIPD
D23
SPISOMI
D22
D17
D16
D7
D6
D1
D0
(1) The SPI_READ register bit must be enabled before attempting a register read.
(2) Specify the register address whose contents must be read back on A[7:0].
(3) The AFE outputs the contents of the specified register on the SOMI pin.
(1)(2)(3)
15
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
tSTECLK
SPISTE
31
SCLK
23
tSIMOHD
tSIMOSU
A7
SPISIMO
A6
A1
A0
D23
D22
D1
D0
16
AFE4490
www.ti.com
t2
> 100 ms
t3
> 0.5 ms
t4
> 1 s
t5
Time between SPI commands and the ADC_RESET which corresponds to valid
data
t6
Time between RESET pulse and high-accuracy data coming out of the signal
chain
> 1 s (3)
t7
> 100 ms
t8
Time from AFE_PDN high-going edge (or PDN_AFE bit reset) to high-accuracy
data coming out of the signal chain
> 1 s (3)
(1)
(2)
(3)
(4)
This time is required for each of the four switched RC filters to fully settle to the new settings. The same time is applicable whenever
there is a change to any of the signal chain controls (for example, LED current setting, TIA gain, and so forth)
If the SPI commands involve a change in the value of TX_REF from its default, then there is additional wait time that is approximately 1
s (for a 2.2-F decoupling capacitor on the TX_REF pin).
Dependent on the value of the capacitors on the BG and TX_REF pins. The 1-s wait time is necessary when the capacitors are 2.2 F
and scale down proportionate to the capacitor value. A very low capacitor (for example, 0.1 F) on these pins causes the transmitter
dynamic range to reduce to approximately 100 dB.
After an active power-down from AFE_PDN, reset the device by using a low-going pulse on RESET.
RX Supplies
(RX_ANA_SUP, RX_DIG_SUP)
t1
TX Supplies
(TX_CTRL_SUP, LED_DRV_SUP)
t2
t6
RESET
t3
t4
t4
t5
t5
SPI Interface
t7
t3
~
~
~
~
ADC_RDY
t6
t8
AFE_PDN
PDN_AFE
Bit Set
RESET
t3
t4
t5
t8
t6
~
~
ADC_RDY
~
~
~
~
SPI Interface
PDN_AFE Bit
Reset
AFE_PDN
17
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
800
800
700
700
600
600
RX Current (A)
RX Current (A)
At TA = 25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
500
RX_ANA_SUP_CURR (A)
400
RX_DIG_SUP_CURR (A)
RX_ANA_CURR_STG2EN (A)
300
200
500
RX_ANA_SUP_CURR (A)
400
RX_DIG_SUP_CURR (A)
RX_ANA_CURR_STG2EN (A)
300
200
100
100
300
500
700
900
1100
1300
PRF (Hz)
100
900
1100
1300
C002
PRF = 600Hz
49.5
LED_DRV_SUP Current (A)
700
50.0
50
49
49
48
48
47
47
46
49.0
48.5
48.0
47.5
47.0
46.5
46.0
46
45.5
45
45.0
2.5
3.0
3.5
4.0
4.5
5.0
3.0
600
700
Input Referred Noise Current,
pA rms in 5Hz Bandwidth
400
300
200
100
0
0
10
20
30
40
4.5
5.0
C004
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
600
500
400
300
200
100
0
50
10
20
30
40
C005
4.0
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
500
3.5
C003
500
PRF (Hz)
50
18
300
C001
50
C006
AFE4490
www.ti.com
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
600
500
400
300
200
100
0
0
10
20
30
40
700
600
500
400
300
200
100
0
50
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
700
1200
1000
800
1400
600
400
200
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
1200
1000
40
50
C008
800
600
400
200
0
10
20
30
40
50
800
800
500
600
400
300
200
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 20Hz B/W.
100
0
0
10
20
30
40
30
40
50
C010
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
700
600
500
400
300
200
100
0
50
10
20
30
40
C011
20
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
700
10
C009
30
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
20
10
C007
50
C012
19
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
800
700
600
500
400
300
200
100
0
0
10
20
30
40
900
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty cycle 25%
1000
800
600
400
200
50
1400
1200
1000
1400
800
600
400
200
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
1200
1000
800
10
20
30
40
C014
400
200
50
16
Noise-Free Bits in 5Hz Bandwidth
15
14
13
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
11
10
0
10
20
30
40
20
30
40
50
C016
12
10
C015
50
0
0
15
14
13
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
12
11
10
50
C017
20
40
600
16
30
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
1600
20
10
C013
10
20
30
40
50
C018
AFE4490
www.ti.com
16
15
14
13
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
12
11
10
0
10
20
30
40
15
14
13
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
12
11
10
50
40
50
C020
16
Noise-Free Bits in 5Hz Bandwidth
30
15
14
13
12
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
11
10
0
10
20
30
40
15
14
13
11
10
50
16
Noise-Free Bits in 20Hz Bandwidth
14
13
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
10
0
10
20
30
40
30
40
50
C022
15
14
13
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
12
11
10
50
10
20
30
40
C023
20
15
11
10
C021
12
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
12
20
16
10
C019
50
C024
21
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
16
15
14
13
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
12
11
10
0
10
20
30
40
15
14
13
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
12
11
10
0
50
40
50
C026
16
Noise-Free Bits in 20Hz Bandwidth
30
15
14
13
12
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
11
10
0
10
20
30
40
15
14
13
11
10
0
110
110
100
90
80
70
75mA & 150mA Range
50mA & 100mA Range
40
60
80
40
50
C028
100
90
80
70
75mA & 150mA Range
60
200mA Range
20
30
20
120
50
10
C027
60
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
12
50
200mA Range
50mA & 100mA Range
50
100
C029
22
20
10
C025
20
40
60
80
100
C030
AFE4490
www.ti.com
500
500
400
400
300
300
DAC Step Error (A)
At TA = 25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
200
100
0
100
200
300
200
100
0
100
200
300
400
400
TX_REF = 0.5V
500
0
50
100
150
200
250
100
150
200
250
C032
400
400
300
300
DAC Step Error (A)
500
200
100
0
100
200
300
200
100
0
100
200
300
400
400
TX_REF = 0.5V
500
TX_REF = 0.5V
500
50
100
150
200
250
50
100
150
200
250
C033
C034
500
100
Expected + 1%
400
300
80
200
TX Current (mA)
50
C031
TX_REF = 0.5V
500
100
0
100
200
300
Expected - 1%
60
40
20
400
TX_REF = 0.5V
0
50
100
150
200
250
500
C035
50
100
150
200
C036
250
23
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
100
Expected + 1%
Expected + 1%
Actual DAC Current
80
Expected - 1%
TX Current (mA)
TX Current (mA)
80
60
40
20
Expected - 1%
60
40
20
TX Reference Voltage = 0.5V
0
0
50
100
150
200
250
0
50
150
200
250
C038
Expected + 1%
Expected + 1%
180
140
120
Expected - 1%
160
TX Current (mA)
TX Current (mA)
160
100
C037
100
80
60
40
Expected - 1%
140
120
100
80
60
40
20
20
0
0
50
100
150
200
250
0
0
50
100
150
200
250
C039
C040
800
TX_RANGE = 150mA,
Data from 2326 devices
2000
TX_RANGE = 150mA,
Data from 7737 devices
Number of Occurences
Number of Occurences
1800
600
400
200
1600
1400
1200
1000
800
600
400
0
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
37.0
37.5
38.0
38.5
39.0
39.5
40.0
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
9.8
10.0
10.2
10.4
10.6
10.8
11.0
11.2
11.4
11.6
11.8
12.0
200
0
C044
C043
24
AFE4490
www.ti.com
1200
Number of Occurences
1000
165
163
161
159
157
155
151
149
147
145
200
143
200
141
400
139
400
600
137
600
800
135
800
63.0
63.5
64.0
64.5
65.0
65.5
66.0
66.5
67.0
67.5
68.0
68.5
69.0
69.5
70.0
70.5
71.0
71.5
72.0
72.5
73.0
73.5
74.0
74.5
75.0
75.5
76.0
76.5
77.0
Number of Occurences
1000
TX_RANGE = 150mA,
Data from 7737 devices
153
TX_RANGE = 150mA,
Data from 7737 devices
C046
800
100.00
TX_CTRL_SUP = LED_DRV_SUP = 3V TO 3.6V
TX Supply Current, uA
RX Supply Current, uA
700
600
500
RX_ANA_SUP = 2V (STG2=DIS)
RX_ANA_SUP = 2V (STG2=EN)
RX_DIG_SUP=2V
RX_ANA_SUP = 3.3V (STG2=DIS)
RX_ANA_SUP = 3.3V (STG2=EN)
RX_DIG_SUP=3.3V
400
300
80.00
60.00
40.00
TX_CTRL_SUP
LED_DRV_SUP
20.00
200
100
100
300
500
700
900
0.00
0.50
1100
PRF, Hz
1.00
C048
Supply Current, uA
0.75
TX_VREF, V
C047
RX_ANA_SUP (STG2DIS)
RX_ANA_SUP (STG2EN)
RX_DIG_SUP
TX_CTRL_SUP
LED_DRV_SUP
80
60
40
PRF = 1200 Hz, Duty cycle = 10%
1) RF = 100K, Stage 2 & ambient cancellation disabled
2) RF = 500K, Stage 2 & ambient cancellation enabled with stage 2 gain = 4
20
0
0
10
20
30
40
50
60
Temperature, C
70
40 30 20 10
10
20
30
40
50
60
70
80
Temperature, C
C049
C050
25
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
15
Attenuation, dB
10
20
30
40
5% Duty cycle
10
0
10
20
30
40
50
60
Temperature, C
50
70
C051
26
10
100
C052
AFE4490
www.ti.com
8 Detailed Description
8.1 Overview
The AFE4490 is a complete analog front-end (AFE) solution targeted for pulse-oximeter applications. The device
consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault
detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also
integrated that functions from an external crystal. The device communicates to an external microcontroller or host
processor using an SPI interface. The Functional Block Diagram section provides a detailed block diagram for
the device. The blocks are described in more detail in the following sections.
BG
DNC
DNC
RX_DIG_SUP
RX_ANA_SUP
RX_ANA_SUP
TX_CTRL_SUP
LED_DRV_SUP
LED_DRV_SUP
Device
Reference
CF
r1.2 V
SPI Interface
SPISTE
RF
SPISIMO
SPI
+
CPD
INP
Stage 2
Gain
TIA
Buffer
Filter
4GADC
SPISOMI
SCLK
Digital
Filter
INN
RF
Photodiode
CF
Control
VCM
Timing
Controller
AFE_PDN
ADC_RDY
RESET
LED
TXN
LED
Driver
LED Current
Control DAC
TXP
DIAG_END
DNC(1)
DNC(1)
DNC(1)
Diagnostic
Signals
Diagnostics
LED_ALM
PD_ALM
VSS
XOUT
XIN
CLKOUT
RX_DIG_GND
RX_DIG_GND
RX_ANA_GND
RX_ANA_GND
RX_ANA_GND
LED_DRV_GND
LED_DRV_GND
LED_DRV_GND
TX_REF
OSC
8 MHz
27
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Rx
SLED2
CONVLED2
LED2
CF
RF
RG
ADC
+
CPD
+Stage 2
TIA
Amb
SLED2_amb
CONVLED2_amb
Gain
Buffer
SLED1
+
ADC
CONVLED1
LED1
RG
RF
CF
ADC Convert
Ambient
DAC
I-V Amplifier
Amb
SLED1_amb
ADC Clock
CONVLED1_amb
Filter
Buffer
ADC
AFE4490
www.ti.com
Device
Host Processor
LED2 Data
Ambient (LED2)
Data
Front End
(LED2 Ambient)
Data
SPI
Interface
ADC
Rx
Digital
SPI
Block
LED1 Data
Ambient (LED1)
Data
(LED1 Ambient)
Data
29
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
ICANCEL
Cf
Rg
Rf
IPLETH + IAMB
Ri
Rx
VDIFF
Ri
Rf
Rg
ICANCEL
Cf
30
RI = 100 k,
IPLETH = photodiode current pleth component,
IAMB = photodiode current ambient component, and
ICANCEL = the cancellation current DAC value (as estimated by the host processor).
(2)
AFE4490
www.ti.com
GAIN (k)
0 (x1)
100
3.5 (x1.5)
150
6 (x2)
200
9.5 (x3)
300
12 (x4)
400
31
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
RED LED
On Signal
IR LED
On Signal
N+1
Plethysmograph Signal
N+2
N
Photodiode Current
Or
I-V Output Pulses
N+1
Ambient Level
(Dark Level)
Rx Sample Time =
tLED Settle Time
SR ,
Sample RED
SR_amb,
Sample Ambient
(RED Phase)
SIR,
Sample IR
SIR_amb,
Sample Ambient
(IR Phase)
CONVIR_amb,
Convert Ambient Sample
(IR Phase)
CONVR,
Convert RED Sample
CONVR_amb,
Convert Ambient Sample
(RED Phase)
CONVIR,
Convert IR Sample
Convert Ambient
Sample N+1
Convert IR
Sample N+1
Convert Ambient
Sample N+1
Convert Red
Sample N+1
1.0 T
Convert Ambient
Sample N
0.75 T
Convert IR
Sample N
0.50 T
Convert Ambient
Sample N
Convert Red
Sample N
Convert Ambient
Sample N-1
0.25 T
0T
ADC Conversion
TCONV
Convert Red
Sample N-1
AFE4490
www.ti.com
Timer
Module
Divideby-2
ADC
Diagnostics
Module
Oscillator
XIN
XOUT
CLKOUT
4 MHz
8-MHz Crystal
33
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
LED2(Red LED)
ON signal
LED1(IR LED)
ON signal
Rx Sample Time = tLED Settling Time
SLED2_amb,
Sample Ambient
(LED2(Red) phase)
SLED1,
Sample LED1(IR)
SLED1_amb,
Sample Ambient
(LED1(IR) phase)
SLED2,
Sample LED2(Red)
CONVLED2,
Convert LED2(Red) sample
CONVLED2_amb,
Convert ambient sample
(LED2(Red) phase)
CONVLED1,
Convert LED1(IR) sample
CONVLED1_amb,
Convert ambient sample
(LED1(IR) phase)
ADC Conversion
ADC Reset
1.0 T
0.75 T
0.50 T
0.25 T
0T
ADC_RDY Pin
AFE4490
www.ti.com
For the 11 signals in Figure 58, the start and stop edge positions are programmable with respect to the PRF
period. Each signal uses a separate timer compare module that compares the counter value with
preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI
interface.
When the counter value equals the start reference value, the output signal is set. When the counter value equals
the stop reference value, the output signal is reset. Figure 61 shows a diagram of the timer compare register.
With a 4-MHz clock, the edge placement resolution is 0.25 s. The ADC conversion signal requires four pulses in
each PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control the
ADC conversion signal.
Set
Output
Signal
Reset
START
STOP
Enable
Enable
Reset
The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four
sets of start and stop registers to control the ADC conversion signal, as shown in Figure 62.
Reset
CLKIN
16-Bit Counter
Reset
Counter
Enable
RED LED
IR LED
SR
Sample RED
SIR
Sample IR
SR_amb,
Sample Ambient
(red phase)
SIR_amb,
Sample Ambient
(IR phase)
Start
Stop
Start
Stop
Start
Stop
Start
Stop
Start
Stop
Start
Stop
Timer Compare
16-Bit Register 1
Timer Compare
16-Bit Register 2
Timer Compare
16-Bit Register 3
Timer Compare
16-Bit Register 4
Timer Compare
16-Bit Register 5
Timer Compare
16-Bit Register 6
En
En
En
En
En
En
En
En
En
PRF
Pulse
Timer Compare
16-Bit PRF Register
En
Timer Compare
16-Bit Register 7
Start
Stop
Timer Compare
16-Bit Register 8
Start
Stop
Timer Compare
16-Bit Register 9
Start
Stop
Timer Compare
16-Bit Register 10
Start
Stop
CONVR,
Convert RED Sample
CONVIR,
Convert IR Sample
CONVIR_amb,
Convert Ambient Sample
(IR Phase)
CONVR_amb,
Convert Ambient Sample
(RED Phase)
START-A
STOP-A
En
START-B
STOP-B
Timer Compare
16-Bit Register 11 START-C
STOP-D
En
ADC
Conversion
START-D
STOP-D
Timer Module
35
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
(1)
(2)
36
DESCRIPTION
EXAMPLE (1)
(Decimal)
t0
No register control
t1
6050
t2
7998
t3
6000
t4
7999
t5
50
t6
1998
t7
2050
t8
3998
t9
2000
t10
3999
t11
4050
t12
5998
t13
t14
1999
t15
2004
t16
3999
t17
4004
t18
5999
t19
6004
t20
7999
t21
(2)
t22
t23
2000
t24
2003
t25
4000
t26
4003
t27
6000
t28
6003
t29
7999
Values are based off of a pulse repetition frequency (PRF) = 500 Hz and duty cycle = 25%.
See Figure 64, note 2 for the affect of the ADC reset time crosstalk.
Submit Documentation Feedback
AFE4490
www.ti.com
t3
SLED2_amb,
Sample Ambient
LED2 (RED) Phase
t9
t10
t6
t5
SLED1,
Sample LED1 (IR)
t7
t8
SLED1_amb,
Sample Ambient
LED1 (IR) Phase
t11
t12
SLED2,
Sample LED2 (RED)
CONVLED2,
Convert LED2 (RED) Sample
t4
t1
t2
t14
t13
CONVLED2_amb,
Convert Ambient Sample
LED2 (RED) Phase
t15
t16
CONVLED1,
Convert LED1 (IR) Sample
t17
t18
CONVLED1_amb,
Convert Ambient Sample
LED1 (IR) Phase
t19
t20
ADC Conversion
ADC Reset
t23
t21
t22
t0
t27
t25
t24
t26
t28
t29
37
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
CONVLED2,
Convert LED2 (RED) Sample
t14
t13
CONVLED2_amb,
Convert Ambient Sample
LED2 (RED) Phase
t16
t15
CONVLED1,
Convert LED1 (IR) Sample
t18
t17
CONVLED1_amb,
Convert Ambient Sample
LED1 (IR) Phase
t20
t19
ADC Conversion
t23
t22
ADC Reset
t0
t25
t24
t27
t28
t26
t29
Figure 64. Relationship Between the ADC Reset and ADC Conversion Signals(1)(2)
38
AFE4490
www.ti.com
1.8 V
RX_ANA_SUP
RX_ANA_SUP to
1.8-V Regulator
Rx Analog Modules
RX_DIG_SUP
RX_DIG_SUP to
1.8-V Regulator
1.8 V
Rx I/O
Block
Rx Digital
I/O
Pins
Device
(3)
To lower the minimum LED_DRV_SUP voltage even further, the transmitter reference voltage can be
programmed to 0.5 V. By doing so, the minimum LED_DRV_SUP voltage can be reduced to 3.0 V, provided that
Equation 4 is met. Refer to the Recommended Operating Conditions table.
3.0 V (VLED + VCABLE) > 1.4 V
(4)
Note that with the 0.5-V transmitter reference voltage, the maximum LED current supported is 100 mA.
39
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
TX_CTRL_SUP
External
Supply
Tx
CBULK
H-Bridge
LED2_ON
H-Bridge
Driver
LED1_ON
LED2_ON
or
LED1_ON
LED2 Current
Reference
ILED
LED
Current
Control
8-Bit Resolution
LED1 Current
Reference
Register
Register
40
AFE4490
www.ti.com
TX_CTRL_SUP
External
Supply
LED_DRV_SUP
CBULK
Tx
LED2_ON
H-Bridge
Driver
LED1_ON
LED2_ON
or
LED1_ON
LED2 Current
Reference
ILED
LED
Current
Control
8-Bit Resolution
LED1 Current
Reference
Register
Register
IR Current Reference
Figure 67. Transmit: Push-Pull LED Drive for Common Anode LED Configuration
41
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
TX_CTRL_SUP
Tx Reference
and Control
LED
Current
Control
DAC
Tx LED
Bridge
LED_DRV_SUP
Device
1 PA
50uA
0 mA to 200 mA
(See the LEDRANGE bits
in the LEDCNTRL register.)
LED_ON
42
AFE4490
www.ti.com
ADC Reset
ADC
22-Bits
ADC
Register
42
LED2 Data
Register
43
LED2_Ambient Data
Register
44
LED1 Data
Register
45
LED1_Ambient Data
LED2 Data
Ambient
(LED2) Data
Averager
LED1 Data
ADC Reset
ADC Convert
Ambient
(LED1) Data
ADC Clock
43
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
44
AFE4490
www.ti.com
ADC Conversion
ADC Data
10
11
12
13
14
15
16
17
18
19
20
ADC Reset
25%
0%
0%
75%
50%
ADC_RDY Pin
0T
1.0 T
45
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
ADC Conversion
ADC Data
10
11
12
13
14
15
16
17
18
19
20
ADC Reset
25%
0%
Average of
ADC data 1 to 3 are
written into
register 42.
Average of
ADC data 5 to 7
are written into
register 43.
0%
75%
50%
Average of
ADC data 9 to 11 are
written into
register 44.
Average of
ADC data 13 to 15 are written
into register 45.
Register 42 register 43
are written into register 46.
Register 44 register 45
are written into register 47.
ADC_RDY Pin
0T
1.0 T
NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2.
46
AFE4490
www.ti.com
INP
RXOUTN
+
Stage 2
Gain
TIA
ADC
INN
Device
External
ADC
In ADC bypass mode, one of the internal clocks (ADC_Reset) can be brought out on the PD_ALM pin, as shown
in Figure 74. This signal can be used to convert each of the four phases (within every pulse repetition period).
Additionally, the ADC_RDY signal can be used to synchronize the external ADC with the AFE. See Figure 75 for
the timing of this mode.
Use ADC_RDY to
sync the external
ADC with the AFE.
RXOUTP
RXOUTN
ADC_RDY
PD_ALM
Clocking
INP
+
TIA
Stage 2
Gain
Internal
ADC
INN
Device
Figure 74. Device in ADC Bypass Mode with ADC_Reset to PD_ALM Pin
Submit Documentation Feedback
47
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
t3
SLED2_amb,
Sample Ambient
LED2 (RED) Phase
t9
t4
t10
t6
t5
SLED1,
Sample LED1 (IR)
t7
t8
SLED1_amb,
Sample Ambient
LED1 (IR) Phase
t11
t12
SLED2,
Sample LED2 (RED)
t1
ADC Reset
(Pin 23)
t22
t27
t25
t23
t21
t24
t2
t28
t26
ADC_RDY
(Pin 28)
t0
t29
Figure 75. Device Analog Output Mode (ADC Bypass) Timing Diagram
48
AFE4490
www.ti.com
10 k
10 k
1 k
Cable
Rx On/Off
INN
To Rx Front-End
INP
Rx On/Off
PD Wires
LED Wires
100 PA
100 PA
GND Wires
49
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
SW1
Cable
SW3
10 k
10 k
TXP
D
C
SW2
SW4
TXN
LED Wires
100 PA
PD Wires
100 PA
GND Wires
LED DAC
50
AFE4490
www.ti.com
SEQ.
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
No fault
Rx INP cable
shorted to LED cable
Rx INN cable
shorted to LED cable
Rx INP cable
shorted to GND
cable
Rx INN cable
shorted to GND
cable
PD open or shorted
Tx OUTM line
shorted to GND
cable
Tx OUTP line
shorted to GND
cable
PD
LED
(1)
FAULT
Diagnostic State
Machine
Diagnostic Ends
Diagnostic Starts
DIAG_END Pin
tDIAG
51
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
After completion of the diagnostics function, time must be allowed for the device filter to settle. See the Electrical
Characteristics for the filter settling time. The slow diagnostics feature is provided for use in systems where highcapacitance sensors (such as photodiodes, capacitors, cables, and so forth) are connected to the INP, INN, TXP,
or TXN pins.
8.5 Programming
8.5.1 Serial Programming Interface
The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data
output), SPISIMO (serial interface data input), and SPISTE (serial interface enable).
The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts
out data from the device. SCLK features a Schmitt-triggered input and clocks data out on SPISOMI. Data are
clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean
as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK
low.
The SPISOMI (SPI serial out master in) pin is used with SCLK to clock out device data. The SPISIMO (SPI serial
in master out) pin is used with SCLK to clock in data to the device. The SPISTE (SPI serial interface enable) pin
enables the serial interface to clock data on the SPISIMO pin in to the device.
8.5.2 Reading and Writing Data
The device has a set of internal registers that can be accessed by the serial programming interface formed by
the SPISTE, SCLK, SPISIMO, and SPISOMI pins.
8.5.2.1 Writing Data
The SPI_READ register bit must be first set to '0' before writing to a register. When SPISTE is low,
Serially shifting bits into the device is enabled.
Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.
The serial data are loaded into the register at every 32nd SCLK rising edge.
In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in
multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and
the remaining 24 bits form the register data. Figure 79 shows an SPI timing diagram for a single write operation.
For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.
SPISTE
SPISIMO
A7
A6
A1
A0
D23
D22
D17
D16
D15
D14
D9
D8
D7
D6
D1
D0
SCLK
52
AFE4490
www.ti.com
Programming (continued)
8.5.2.2 Reading Data
The SPI_READ register bit must be first set to '1' before reading from a register. The device includes a mode
where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a
diagnostic check to verify the serial interface communication between the external controller and the AFE. To
enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing
Data section. In the next command, specify the SPI register address with the desired content to be read. Within
the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin.
Figure 80 shows an SPI timing diagram for a single read operation. For multiple read and write cycles, refer to
the Multiple Data Reads and Writes section.
SPISTE
SPISIMO
A7
A6
A1
A0
SPISOMI
D23
D22
D17
D16
D15
D14
D9
D8
D7
D6
D1
D0
SCLK
(1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.
(2) Specify the register address of the content that must be readback on bits A[7:0].
(3) The AFE outputs the contents of the specified register on the SPISOMI pin.
53
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
SPISIMO
Second Write(1, 2)
First Write
Operation
A7
A0
D23
D16
D15
D8
D7
D0
A7
A0
D23
D16
D15
Read(3, 4)
D8
D7
D0
A7
A0
D23
D16
D15
D8
D7
D0
SPISOMI
SCLK
(1) The SPI read register bit must be enabled before attempting a serial readout from the AFE.
(2) The second write operation must be configured for register 0 with data 000001h.
(3) Specify the register address whose contents must be read back on A[7:0].
(4) The AFE outputs the contents of the specified register on the SOMI pin.
54
AFE4490
www.ti.com
55
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL0
00
DIAG_EN
TIM_COUNT_RST
SPI_READ
REGISTER DATA
Hex
SW_RST
ADDRESS
REGISTER
CONTROL (1)
NAME
LED2STC
R/W
01
LED2STC[15:0]
LED2ENDC
R/W
02
LED2ENDC[15:0]
LED2LEDSTC
R/W
03
LED2LEDSTC[15:0]
LED2LEDENDC
R/W
04
LED2LEDENDC[15:0]
ALED2STC
R/W
05
ALED2STC[15:0]
ALED2ENDC
R/W
06
ALED2ENDC[15:0]
LED1STC
R/W
07
LED1STC[15:0]
LED1ENDC
R/W
08
LED1ENDC[15:0]
LED1LEDSTC
R/W
09
LED1LEDSTC[15:0]
LED1LEDENDC
R/W
0A
10
LED1LEDENDC[15:0]
ALED1STC
R/W
0B
11
ALED1STC[15:0]
ALED1ENDC
R/W
0C
12
ALED1ENDC[15:0]
LED2CONVST
R/W
0D
13
LED2CONVST[15:0]
LED2CONVEND
R/W
0E
14
LED2CONVEND[15:0]
ALED2CONVST
R/W
0F
15
ALED2CONVST[15:0]
ALED2CONVEND
R/W
10
16
ALED2CONVEND[15:0]
LED1CONVST
R/W
11
17
LED1CONVST[15:0]
LED1CONVEND
R/W
12
18
LED1CONVEND[15:0]
ALED1CONVST
R/W
13
19
ALED1CONVST[15:0]
ALED1CONVEND
R/W
14
20
ALED1CONVEND[15:0]
ADCRSTSTCT0
R/W
15
21
ADCRSTCT0[15:0]
ADCRSTENDCT0
R/W
16
22
ADCRENDCT0[15:0]
ADCRSTSTCT1
R/W
17
23
ADCRSTCT1[15:0]
ADCRSTENDCT1
R/W
18
24
ADCRENDCT1[15:0]
ADCRSTSTCT2
R/W
19
25
ADCRSTCT2[15:0]
ADCRSTENDCT2
R/W
1A
26
ADCRENDCT2[15:0]
ADCRSTSTCT3
R/W
1B
27
ADCRSTCT3[15:0]
ADCRSTENDCT3
R/W
1C
28
ADCRENDCT3[15:0]
(1)
56
R = read only, R/W = read or write, N/A = not available, and W = write only.
Submit Documentation Feedback
AFE4490
www.ti.com
D23
D22
D21
D20
D19
D18
D17
D16
PRPCOUNT
R/W
1D
29
CONTROL1
R/W
1E
30
CLKALMPIN[2:0]
TIMEREN
SPARE1
N/A
1F
31
TIAGAIN
R/W
20
32
ENSEPGAN
STAGE2EN1
STG2GAIN1[2:0]
CF_LED1[4:0]
RF_LED1[2:0]
TIA_AMB_GAIN
R/W
21
33
FLTRCNRSEL
STAGE2EN2
STG2GAIN2[2:0]
CF_LED2[4:0]
RF_LED2[2:0]
LEDCNTRL
R/W
22
34
CONTROL2
R/W
23
35
TX_REF0
REGISTER DATA
Hex
TX_REF1
ADDRESS
REGISTER
CONTROL (1)
SPARE2
N/A
24
36
SPARE3
N/A
25
37
SPARE4
N/A
26
38
RESERVED1
N/A
27
39
RESERVED2
N/A
28
40
ALARM
R/W
29
41
AMBDAC[3:0]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PRPCT[15:0]
LED
RANGE[1:0]
NUMAV[7:0]
PDNAFE
PDNRX
PDNTX
DIGOUT_TRISTATE
ALMPINCLKEN
EN_SLOW_DIAG
XTALDIS
TXBRGMOD
LED2[7:0]
EN_ADC_BYP
LED1[7:0]
RST_CLK_ON_PD_ALM
NAME
57
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
2B
43
ALED2VAL[23:0]
2C
44
LED1VAL[23:0]
ALED1VAL
2D
45
ALED1VAL[23:0]
LED2-ALED2VAL
2E
46
LED2-ALED2VAL[23:0]
LED1-ALED1VAL
2F
47
LED1-ALED1VAL[23:0]
DIAG
30
48
58
D13
D12
D11
D10
LED1OPEN
D14
LED_ALM
D15
PD_ALM
D16
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
INPSCLED
LED1VAL
D17
INNSCLED
ALED2VAL
D18
INPSCGND
LED2VAL[23:0]
D19
INNSCGND
42
D20
PDSC
2A
D21
PDOC
D22
OUTNSHGND
LED2VAL
D23
OUTPSHGN
Dec
LEDSC
REGISTER DATA
Hex
LED2OPEN
ADDRESS
REGISTER
CONTROL (1)
NAME
AFE4490
www.ti.com
D22
0
W-0h
D10
D21
0
W-0h
D9
D20
0
W-0h
D8
D19
0
W-0h
D7
D18
0
W-0h
D6
D17
0
W-0h
D5
D16
0
W-0h
D4
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
D15
0
W-0h
D3
D14
0
W-0h
D2
SW_RST DIAG_EN
W-0h
W-0h
D13
0
W-0h
D1
TIM_
COUNT_
RST
W-0h
D12
0
W-0h
D0
SPI_
READ
W-0h
This register is write-only. CONTROL0 is used for AFE software and count timer reset, diagnostics enable, and
SPI read functions.
Bits D[23:4]
Must be '0'
Bit D3
Bit D2
Bit D1
Bit D0
59
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Figure 83. LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED2STC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED2STC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the LED2 signal sample.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 84. LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED2ENDC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED2ENDC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the LED2 signal sample.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 85. LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED2LEDSTC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED2LEDSTC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for when the LED2 signal turns on.
Bits D[23:16]
Must be '0'
Bits D[15:0]
60
AFE4490
www.ti.com
Figure 86. LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED2LEDENDC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED2LEDENDC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for when the LED2 signal turns off.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 87. ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ALED2STC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ALED2STC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the ambient LED2 signal sample.
Bits D[23:16]
Must be '0'
Bits D[15:0]
61
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ALED2ENDC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ALED2ENDC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the ambient LED2 signal sample.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 89. LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED1STC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED1STC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the LED1 signal sample.
Bits D[23:17]
Must be '0'
Bits D[16:0]
62
AFE4490
www.ti.com
Figure 90. LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED1ENDC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED1ENDC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the LED1 signal sample.
Bits D[23:17]
Must be '0'
Bits D[16:0]
Figure 91. LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED1LEDSTC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED1LEDSTC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for when the LED1 signal turns on.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 92. LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED1LEDENDC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED1LEDENDC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for when the LED1 signal turns off.
Bits D[23:16]
Must be '0'
Bits D[15:0]
63
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Figure 93. ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ALED1STC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ALED1STC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the ambient LED1 signal sample.
Bits D[23:16]
Must be '0'
Bits D[15:0]
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ALED1ENDC[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ALED1ENDC[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the ambient LED1 signal sample.
Bits D[23:16]
Must be '0'
Bits D[15:0]
64
AFE4490
www.ti.com
Figure 95. LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED2CONVST[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED2CONVST[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the LED2 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 96. LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED2CONVEND[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED2CONVEND[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the LED2 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
65
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ALED2CONVST[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ALED2CONVST[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the ambient LED2 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
D16
0
0
0
R/W-0h
R/W-0h
R/W-0h
D6
D5
D4
ALED2CONVEND[15:0]
R/W-0h
D15
D3
D14
D13
ALED2CONVEND[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the ambient LED2 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
66
AFE4490
www.ti.com
Figure 99. LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED1CONVST[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED1CONVST[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the LED1 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 100. LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
LED1CONVEND[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
LED1CONVEND[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the LED1 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
67
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ALED1CONVST[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ALED1CONVST[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start timing value for the ambient LED1 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
D16
0
0
0
R/W-0h
R/W-0h
R/W-0h
D6
D5
D4
ALED1CONVEND[15:0]
R/W-0h
D15
D3
D14
D13
ALED1CONVEND[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end timing value for the ambient LED1 conversion.
Bits D[23:16]
Must be '0'
Bits D[15:0]
68
AFE4490
www.ti.com
Figure 103. ADCRSTSTCT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ADCRSTSTCT0[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ADCRSTSTCT0[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start position of the ADC0 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 104. ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
D16
0
0
0
R/W-0h
R/W-0h
R/W-0h
D6
D5
D4
ADCRSTENDCT0[15:0]
R/W-0h
D15
D3
D14
D13
ADCRSTENDCT0[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end position of the ADC0 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 105. ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ADCRSTSTCT1[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ADCRSTSTCT1[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start position of the ADC1 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
69
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Figure 106. ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
D16
0
0
0
R/W-0h
R/W-0h
R/W-0h
D6
D5
D4
ADCRSTENDCT1[15:0]
R/W-0h
D15
D3
D14
D13
ADCRSTENDCT1[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end position of the ADC1 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 107. ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ADCRSTSTCT2[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ADCRSTSTCT2[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start position of the ADC2 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
70
AFE4490
www.ti.com
Figure 108. ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
D16
0
0
0
R/W-0h
R/W-0h
R/W-0h
D6
D5
D4
ADCRSTENDCT2[15:0]
R/W-0h
D15
D3
D14
D13
ADCRSTENDCT2[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end position of the ADC2 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 109. ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
ADCRSTSTCT3[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
ADCRSTSTCT3[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the start position of the ADC3 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
Figure 110. ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
D16
0
0
0
R/W-0h
R/W-0h
R/W-0h
D6
D5
D4
ADCRSTENDCT3[15:0]
R/W-0h
D15
D3
D14
D13
ADCRSTENDCT3[15:0]
R/W-0h
D2
D1
D12
D0
This register sets the end position of the ADC3 reset conversion signal.
Bits D[23:16]
Must be '0'
Bits D[15:0]
71
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Figure 111. PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
0
R/W-0h
D10
D21
0
R/W-0h
D9
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
D17
0
0
R/W-0h
R/W-0h
D6
D5
PRPCOUNT[15:0]
R/W-0h
D16
0
R/W-0h
D4
D15
D3
D14
D13
PRPCOUNT[15:0]
R/W-0h
D2
D1
D12
D0
Must be '0'
Bits D[15:0]
Figure 112. CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h)
D23
D22
D21
0
0
0
R/W-0h
R/W-0h
R/W-0h
D11
D10
D9
CLKALMPIN[2:0]
R/W-0h
D20
0
R/W-0h
D8
TIMEREN
R/W-0h
D19
0
R/W-0h
D7
D18
0
R/W-0h
D6
D17
0
R/W-0h
D5
D16
D15
0
0
R/W-0h
R/W-0h
D4
D3
NUMAV[7:0]
R/W-0h
D14
0
R/W-0h
D2
D13
0
R/W-0h
D1
D12
0
R/W-0h
D0
This register configures the clock alarm pin, timer, and number of averages.
Bits D[23:12]
Must be '0'
Bits D[11:9]
Bit D8
Bits D[7:0]
72
AFE4490
www.ti.com
000
001
010
011
LED2 convert
LED1 convert
100
101
No output
No output
110
No output
No output
111
No output
No output
Figure 113. SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h)
D23
0
R/W-0h
D11
0
R/W-0h
D22
0
R/W-0h
D10
0
R/W-0h
D21
0
R/W-0h
D9
0
R/W-0h
D20
0
R/W-0h
D8
0
R/W-0h
D19
0
R/W-0h
D7
0
R/W-0h
D18
0
R/W-0h
D6
0
R/W-0h
D17
0
R/W-0h
D5
0
R/W-0h
D16
0
R/W-0h
D4
0
R/W-0h
D15
0
R/W-0h
D3
0
R/W-0h
D14
0
R/W-0h
D2
0
R/W-0h
D13
0
R/W-0h
D1
0
R/W-0h
D12
0
R/W-0h
D0
0
R/W-0h
Must be '0'
73
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
D22
D21
D20
D19
D18
D17
D16
R/W-0h
D7
R/W-0h
D6
R/W-0h
D11
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
D10
D9
D8
STG2GAIN1[2:0]
R/W-0h
R/W-0h
R/W-0h
D5
D4
CF_LED1[4:0]
R/W-0h
D15
ENSEP
GAIN
R/W-0h
D3
D14
STAGE2
EN1
R/W-0h
D2
D13
D12
R/W-0h
R/W-0h
D1
D0
RF_LED1[2:0]
R/W-0h
This register sets the device transimpedance amplifier gain mode and feedback resistor and capacitor values.
Bits D[23:16]
Must be '0'
Bit D15
Bit D14
Bits D[13:11]
Must be '0'
Bits D[10:8]
Bits D[7:3]
100
101
110
111
=
=
=
=
00100 = 25 pF + 5 pF
01000 = 50 pF + 5 pF
10000 = 150 pF + 5 pF
Note that any combination of these CF settings is also supported by setting multiple bits to
'1'. For example, to obtain CF = 100 pF, set D[7:3] = 01111.
Bits D[2:0]
74
=
=
=
=
100
101
110
111
=
=
=
=
25 k
10 k
1 M
None
AFE4490
www.ti.com
Figure 115. TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register
(Address = 21h, Reset Value = 0000h)
D23
D22
D21
D20
R/W-0h
D11
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
D10
D9
D8
STG2GAIN2[2:0]
R/W-0h
D19
D18
D17
D16
D15
FLTR
CNRSEL
R/W-0h
D3
AMBDAC[3:0]
R/W-0h
D7
D6
D5
CF_LED2[4:0]
R/W-0h
D4
D14
STAGE2
EN2
R/W-0h
D2
D13
D12
R/W-0h
R/W-0h
D1
D0
RF_LED2[2:0]
R/W-0h
This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner
frequency.
Bits D[23:20]
Must be '0'
Bits D[19:16]
Bit D15
=
=
=
=
=
=
=
=
1000
1001
1010
1011
1100
1101
1110
1111
=
=
=
=
=
=
=
=
8 A
9 A
10 A
Do not
Do not
Do not
Do not
Do not
use
use
use
use
use
Bit D14
Bits D[13:11]
Must be '0'
Bits D[10:8]
Bits D[7:3]
100
101
110
111
=
=
=
=
00100 = 25 pF + 5 pF
01000 = 50 pF + 5 pF
10000 = 150 pF + 5 pF
Note that any combination of these CF settings is also supported by setting multiple bits to
'1'. For example, to obtain CF = 100 pF, set D[7:3] = 01111.
Bits D[2:0]
=
=
=
=
500 k
250 k
100 k
50 k
100
101
110
111
=
=
=
=
25 k
10 k
1 M
None
Submit Documentation Feedback
75
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Figure 116. LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h)
D23
0
R/W-0h
D11
D22
D21
0
0
R/W-0h
R/W-0h
D10
D9
LED1[7:0]
R/W-0h
D20
0
R/W-0h
D8
D19
0
R/W-0h
D7
D18
0
R/W-0h
D6
D17
D16
D15
LED_RANGE[1:0]
R/W-0h
D5
D4
D3
LED2[7:0]
R/W-0h
D14
D13
LED1[7:0]
R/W-0h
D2
D1
D12
D0
This register sets the LED current range and the LED1 and LED2 drive current.
Bits D[23:18]
Must be '0'
Bits D[17:16]
Bits D[15:8]
Bits D[7:0]
LED_RANGE[1:0]
IMAX
VHR
IMAX
VHR
IMAX
VHR
150 mA
1.4 V
100 mA
1.1 V
200 mA
1.7 V
01
75 mA
1.3 V
50 mA
1.0 V
100 mA
1.6 V
10
150 mA
1.4 V
100 mA
1.1 V
200 mA
1.7 V
11
Tx is off
Tx is off
Tx is off
(1)
For a 3-V to 3.6-V supply, use TX_REF = 0.5 V. For a 4.75-V to 5.25-V supply, use TX_REF = 0.75 V or 1.0 V.
LED1[7:0]
256
LED2[7:0]
256
76
Full-Scale Current
(6)
Full-Scale Current
(7)
AFE4490
www.ti.com
Figure 117. CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h)
D23
D22
D21
D20
D19
R/W-0h
D11
R/W-0h
D10
DIGOUT_
TRI
STATE
R/W-0h
R/W-0h
D9
R/W-0h
D8
EN_
SLOW_
DIAG
R/W-0h
R/W-0h
D7
R/W-0h
D6
R/W-0h
D5
D16
RST_
CLK_ON
_PD_
ALM
R/W-0h
D4
R/W-0h
R/W-0h
R/W-0h
TXBRG
MOD
R/W-0h
XTAL
DIS
R/W-0h
D18
D17
TX_REF1 TX_REF0
D15
D14
D13
D12
EN_ADC
_BYP
R/W-0h
D3
R/W-0h
D2
R/W-0h
D1
R/W-0h
D0
PDNTX
PDNRX
PDNAFE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes.
Bits D[23:19]
Must be '0'
Bits D[18:17]
=
=
=
=
NOTE: For best results, use TX_REF = 0.5 V for 3-V operation. Use TX_REF = 0.75V and
TX_REF = 1.0 V for 5-V operation.
Bit D16
Bit D15
Bits D[14:12]
Must be '0'
Bit D11
Bit D10
Bit D9
Bit D8
77
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Bits D[7:3]
Must be '0'
Bit D2
PDN_TX: Tx power-down
0 = The Tx is powered up (default after reset)
1 = Only the Tx module is powered down
Bit D1
PDN_RX: Rx power-down
0 = The Rx is powered up (default after reset)
1 = Only the Rx module is powered down
Bit D0
Figure 118. SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h)
D23
0
R/W-0h
D11
0
R/W-0h
D22
0
R/W-0h
D10
0
R/W-0h
D21
0
R/W-0h
D9
0
R/W-0h
D20
0
R/W-0h
D8
0
R/W-0h
D19
0
R/W-0h
D7
0
R/W-0h
D18
0
R/W-0h
D6
0
R/W-0h
D17
0
R/W-0h
D5
0
R/W-0h
D16
0
R/W-0h
D4
0
R/W-0h
D15
0
R/W-0h
D3
0
R/W-0h
D14
0
R/W-0h
D2
0
R/W-0h
D13
0
R/W-0h
D1
0
R/W-0h
D12
0
R/W-0h
D0
0
R/W-0h
Must be '0'
Figure 119. SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h)
D23
0
R/W-0h
D11
0
R/W-0h
D22
0
R/W-0h
D10
0
R/W-0h
D21
0
R/W-0h
D9
0
R/W-0h
D20
0
R/W-0h
D8
0
R/W-0h
D19
0
R/W-0h
D7
0
R/W-0h
D18
0
R/W-0h
D6
0
R/W-0h
D17
0
R/W-0h
D5
0
R/W-0h
D16
0
R/W-0h
D4
0
R/W-0h
D15
0
R/W-0h
D3
0
R/W-0h
D14
0
R/W-0h
D2
0
R/W-0h
D13
0
R/W-0h
D1
0
R/W-0h
D12
0
R/W-0h
D0
0
R/W-0h
Must be '0'
Figure 120. SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h)
D23
0
R/W-0h
D11
0
R/W-0h
D22
0
R/W-0h
D10
0
R/W-0h
D21
0
R/W-0h
D9
0
R/W-0h
D20
0
R/W-0h
D8
0
R/W-0h
D19
0
R/W-0h
D7
0
R/W-0h
D18
0
R/W-0h
D6
0
R/W-0h
D17
0
R/W-0h
D5
0
R/W-0h
D16
0
R/W-0h
D4
0
R/W-0h
D15
0
R/W-0h
D3
0
R/W-0h
D14
0
R/W-0h
D2
0
R/W-0h
D13
0
R/W-0h
D1
0
R/W-0h
D12
0
R/W-0h
D0
0
R/W-0h
78
Must be '0'
AFE4490
www.ti.com
D22
X
R-0h
D10
X
R-0h
D21
X
R-0h
D9
X
R-0h
D20
X
R-0h
D8
X
R-0h
D19
X
R-0h
D7
X
R-0h
D18
X
R-0h
D6
X
R-0h
D17
X
R-0h
D5
X
R-0h
D16
X
R-0h
D4
X
R-0h
D15
X
R-0h
D3
X
R-0h
D14
X
R-0h
D2
X
R-0h
D13
X
R-0h
D1
X
R-0h
D12
X
R-0h
D0
X
R-0h
D13
X
R-0h
D1
X
R-0h
D12
X
R-0h
D0
X
R-0h
X = don't care.
This register is reserved for factory use. Readback values vary between devices.
Bits D[23:0]
Must be '0'
Figure 122. RESERVED2: RESERVED2 Register For Factory Use Only
(Address = 28h, Reset Value = XXXXh)
D23
X (1)
R-0h
D11
X
R-0h
D22
X
R-0h
D10
X
R-0h
D21
X
R-0h
D9
X
R-0h
D20
X
R-0h
D8
X
R-0h
D19
X
R-0h
D7
X
R-0h
D18
X
R-0h
D6
X
R-0h
D17
X
R-0h
D5
X
R-0h
D16
X
R-0h
D4
X
R-0h
D15
X
R-0h
D3
X
R-0h
D14
X
R-0h
D2
X
R-0h
X = don't care.
This register is reserved for factory use. Readback values vary between devices.
Bits D[23:0]
Must be '0'
Figure 123. ALARM: Alarm Register (Address = 29h, Reset Value = 0000h)
D23
0
R-0h
D11
D22
0
R-0h
D10
D21
0
R-0h
D9
D20
0
R-0h
D8
R-0h
R-0h
R-0h
R-0h
D19
0
R-0h
D7
ALMPIN
CLKEN
R-0h
D18
0
R-0h
D6
D17
0
R-0h
D5
D16
0
R-0h
D4
D15
0
R-0h
D3
D14
0
R-0h
D2
D13
0
R-0h
D1
D12
0
R-0h
D0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Must be '0'
Bit D7
Bits D[6:0]
Must be '0'
79
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
Figure 124. LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h)
D23
D22
D21
D20
D19
D11
D10
D9
D8
D7
D18
D17
LED2VAL[23:0]
R-0h
D6
D5
LED2VAL[23:0]
R-0h
D16
D15
D14
D13
D12
D4
D3
D2
D1
D0
This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal
goes high each time that the contents of this register are updated. The host processor must readout this register
before the next sample is converted by the AFE.
Bits D[23:0]
D23
D22
D21
D20
D19
D11
D10
D9
D8
D7
D18
D17
ALED2VAL[23:0]
R-0h
D6
D5
ALED2VAL[23:0]
R-0h
D16
D15
D14
D13
D12
D4
D3
D2
D1
D0
This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY
signal goes high each time that the contents of this register are updated. The host processor must readout this
register before the next sample is converted by the AFE.
Bits D[23:0]
80
AFE4490
www.ti.com
Figure 126. LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h)
D23
D22
D21
D20
D19
D11
D10
D9
D8
D7
D18
D17
LED1VAL[23:0]
R-0h
D6
D5
LED1VAL[23:0]
R-0h
D16
D15
D14
D13
D12
D4
D3
D2
D1
D0
This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal
goes high each time that the contents of this register are updated. The host processor must readout this register
before the next sample is converted by the AFE.
Bits D[23:0]
D23
D22
D21
D20
D19
D11
D10
D9
D8
D7
D18
D17
ALED1VAL[23:0]
R-0h
D6
D5
ALED1VAL[23:0]
R-0h
D16
D15
D14
D13
D12
D4
D3
D2
D1
D0
This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY
signal goes high each time that the contents of this register are updated. The host processor must readout this
register before the next sample is converted by the AFE.
Bits D[23:0]
81
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
D22
D21
D20
D19
D11
D10
D9
D8
D7
D18
D17
LED2-ALED2VAL[23:0]
R-0h
D6
D5
LED2-ALED2VAL[23:0]
R-0h
D16
D15
D14
D13
D12
D4
D3
D2
D1
D0
This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host
processor must readout this register before the next sample is converted by the AFE.
Bits D[23:0]
D22
D21
D20
D19
D11
D10
D9
D8
D7
D18
D17
LED1-ALED1VAL[23:0]
R-0h
D6
D5
LED1-ALED1VAL[23:0]
R-0h
D16
D15
D14
D13
D12
D4
D3
D2
D1
D0
This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted. The host
processor must readout this register before the next sample is converted by the AFE.
Bits D[23:0]
82
AFE4490
www.ti.com
Figure 130. DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h)
D23
0
R-0h
D11
LED_
ALM
R-0h
D22
0
R-0h
D10
LED1
OPEN
R-0h
D21
0
R-0h
D9
LED2
OPEN
R-0h
D20
0
R-0h
D8
LEDSC
R-0h
D19
0
R-0h
D7
OUTPSH
GND
R-0h
D18
0
R-0h
D6
OUTNSH
GND
R-0h
D17
0
R-0h
D5
D16
0
R-0h
D4
PDOC
PDSC
R-0h
R-0h
D15
0
R-0h
D3
INNSC
GND
R-0h
D14
0
R-0h
D2
INPSC
GND
R-0h
D13
0
R-0h
D1
INNSC
LED
R-0h
D12
PD_ALM
R-0h
D0
INPSC
LED
R-0h
This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics
sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin.
Bits D[23:13]
Read only
Bit D12
Bit D11
Bit D10
Bit D9
Bit D8
Bit D7
Bit D6
Bit D5
83
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
Bit D4
www.ti.com
Bit D3
Bit D2
Bit D1
Bit D0
84
AFE4490
www.ti.com
Y1
C7
2
8 MHz
18 pF
R17
R16
0
0
18 pF
DNI
RX_DIG_SUP
R20
R22
RX_ANA_SUP
TP11
130
130
R15 0
XIN_MSP
C10
0.1 F
40
39
38
37
36
35
34
33
32
31
C9
0.1 F
RX_ANA_SUP
TP7
0 IN_N
0 IN_P
VCM_AFE
R28
DET_P
R32
R36
R40
130
130
130
1.00 k
R41
TP14
D2
BAV99W-7-F
75 V
DB9-F
J2
10
11
C12
0.01 F
130
INM
INP
RX_ANA_GND
VCM
DNC
DNC
BG
VSS
RSVD
DNC
VBG
C41
2.2 F
C42
2.2 F
11
12
13
14
15
16
17
18
19
20
5
9
4
8
3
7
2
6
1
1
2
3
4
5
6
7
8
9
10
TX_CTRL_SUP
LED_DRV_GND
LED_DRV_GND
TXM
TXP
LED_DRV_GND
LED_DRV_SUP
LED_DRV_SUP
RX_DIG_GND
AFE_PDNZ
R24
R27
R98
10 k
CLK_OUT
RESETZ
ADC_RDY
SPI_STE
SPI_SIMO
SPI_SOMI
SPI_CLK
PD_ALM
LED_ALM
DIAG_END
R23
30
29
28
27
26
25
24
23
22
21
AFE_CLKOUT
AFE_RESETZ
ADC_RDY
STE
SIMO
SOMI
SCLK
PD_ALM
LED_ALM
DIAG_END
TP20
AFE_PDNZ
TX_CTRL_SUP
10
EP
TP12
TP13
D1
BAV99W-7-F
75 V
TP6
41
TP8
1
RX_DIG_SUP
U1
AFE4400
RX_ANA_GND
RX_ANA_SUP
XIN
XOUT
RX_ANA_GND
RX_OUTP
RX_OUTN
RX_ANA_SUP
RX_DIG_GND
RX_DIG_SUP
VCM_SHIELD
DET_N
AFE_PDNZ
LED_DRV_SUP
DB9-F-TP
C16
0.1 F
LED_DRV_SUP
C15
1 F
TP22
R44
0
Jumper
TX_LED_N
TX_N
TP17
TP25
2
D3
BAV99W-7-F
75 V
0
R48
Jumper
TX_LED_P
TP23
2
TP30
TX_P
D4
BAV99W-7-F
75 V
NOTE: The following signals must be considered as two sets of differential pains and routed as adjacent signals within each pair:
TXM, TXP and INM, INP.
INM and INP must be guarded with VCM_SHIELD the signal. Run the VCM_SHIELD signal to the DB9 connector and back to the device.
85
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
RED
IR
TXM
TXP
LED2
Controls
LED1
Controls
LED_DRV_GND
LED2
Controls
LED1
Controls
IR
TXM
TXP
RED
LED2
Controls
LED1
Controls
LED_DRV_GND
86
AFE4490
www.ti.com
INN
87
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
ADC max
(Differential)
+1 V
TIA max
(Differential)
+0.6 V
Ideal Operating
Point
0V
TIA min
(Differential)
-1 V
ADC min
(Differential)
-1.2 V
D22
D21
D20
D10
D9
D8
Ignore
R/W-0h
D11
D19
D18
D17
D16
D15
22-Bit ADC Code, MSB to LSB
R/W-0h
D7
D6
D5
D4
D3
22-Bit ADC Code, MSB to LSB
R/W-0h (TBD register correct?)
D14
D13
D12
D2
D1
D0
Table 7 shows the mapping of the input voltage to the ADC output code.
Table 7. Input Voltage Mapping
88
1.2 V
1000000000000000000000
(1.2 / 221) V
1111111111111111111111
0000000000000000000000
(1.2 / 221) V
0000000000000000000001
1.2 V
0111111111111111111111
AFE4490
www.ti.com
The data format is binary twos complement format, MSB first. TI recommends that the input to the ADC does not
exceed 1 V (which is approximately 80% full-scale) because the TIA has a full-scale range of 1 V.
9.2.3 Application Curve
The dc component of the current from the PPG signal is referred to as Pleth (short for photoplethysmography)
current. The input-referred noise current (referred differentially to the INP, INN inputs) as a function of the Pleth
current is shown in Figure 136 at a PRF of 600 Hz and for various duty cycles of LED pulsing. For example, a
duty cycle of 25% refers to a case where the LED is pulsed for 25% of the pulse repetition period and the
receiver samples the photodiode current for the same period of time. The noise shown in Figure 136 is the
integrated noise over a 20-Hz bandwidth from dc.
900
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
800
700
600
500
400
300
200
100
0
0
10
20
30
40
50
C013
89
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
10 Power-Supply Recommendations
The AFE4490 has two sets of supplies: the receiver supplies (RX_ANA_SUP, RX_DIG_SUP) and the transmitter
supplies (TX_CTRL_SUP, LED_DRV_SUP). The receiver supplies can be between 2.0 V to 3.6 V whereas the
transmitter supplies can be between 3.0 V to 5.25 V. Another consideration that determines the minimum allowed
value of the transmitter supplies is the forward voltage of the LEDs being driven. The current source and
switches inside the AFE require voltage headroom that mandates the transmitter supply to be a few hundred
millivolts higher than the LED forward voltage. TX_REF is the voltage that governs the generation of the LED
current from the internal reference voltage. Choosing the lowest allowed TX_REF setting reduces the additional
headroom required but results in higher transmitter noise. Other than for the highest end clinical SPO2
applications, this extra noise resulting from a lower TX_REF setting might be acceptable.
The LED_DRV_SUP and TX_CTRL_SUP are recommended to be tied together to the same supply (between
3.0 V and 5.25 V). The external supply (connected to the common anode of the two LEDs) must be high enough
to account for the forward drop of the LEDs as well as the voltage headroom required by the current source and
switches inside the AFE. In most cases, this voltage is expected to fall below 5.25 V; thus the external supply
can be the same as the LED_DRV_SUP. However, there might be cases (for instance when two LEDs are
connected in series) where the voltage required on the external supply is higher than 5.25 V. Such a case must
be handled with care to ensure that the voltage on the TXP and TXN pins stays less than 5.25 V and also never
exceeds the supply voltage of LED_DRV_SUP, TX_CTRL_SUP by more than 0.3 V.
Many scenarios of power management are possible.
Case 1: LED forward voltage is such that a voltage of 3.3 V (for example) is acceptable on LED_DRV_SUP. In
that case, a single 3.3-V supply can be used to drive all four pins (RX_ANA_SUP, RX_DIG_SUP,
TX_CTRL_SUP, LED_DRV_SUP). Care must be taken to provide some isolation between the transmit and
receive supplies because the LED_DRV_SUP carries the high switching current from the LEDs.
Case 2: A low-voltage supply (2.2 V for instance) is available in the system. In this case, a boost converter can
be used to derive the voltage for the LED_DRV_SUP, as shown in Figure 137.
2.2-V supply
(Connect to RX_ANA, RX_DIG)
Boost
Converter
3.6 V
(Connect to LED_DRV_SUP, TX_CTRL_SUP)
90
AFE4490
www.ti.com
Case 3: In cases where a high voltage supply is available in the system, a buck converter or an LDO can be
used to derive the voltage levels required to drive RX_ANA and RX_DIG. Such a scenario is shown in
Figure 138.
3.6 V
(Connect to LED_DRV_SUP, TX_CTRL_SUP)
LDO
2.2-V supply
(Connect to RX_ANA, RX_DIG)
91
AFE4490
SBAS602H DECEMBER 2012 REVISED OCTOBER 2014
www.ti.com
11 Layout
11.1 Layout Guidelines
Some key layout guidelines are:
1. TXP, TXN are fast switching lines and must be routed away from sensitive reference lines as well as from
the INP, INN inputs.
2. If required to route long, TI recommends that the VCM be used as a shield for the INP, INN lines.
3. The device can draw high switching currents from the LED_DRV_SUP pin. Therefore, having a decoupling
capacitor electrically close to the pin is recommended.
92
AFE4490
www.ti.com
12.2 Trademarks
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
12.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
93
www.ti.com
24-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
AFE4490RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AFE4490
AFE4490RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AFE4490
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
24-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
10-Oct-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AFE4490RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
AFE4490RHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
10-Oct-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AFE4490RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
AFE4490RHAT
VQFN
RHA
40
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
www.ti.com/automotive
Amplifiers
amplifier.ti.com
www.ti.com/communications
Data Converters
dataconverter.ti.com
www.ti.com/computers
DLP Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
www.ti.com/energy
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
www.ti.com/video
RFID
www.ti-rfid.com
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright 2015, Texas Instruments Incorporated