VENKATESH SARAF

Amarashilpi #EWS-837, 1st main, 1st cross, Navanagar, Hubli - 580025

:

09611622465
vsaraf05@gmail.com

in.linkedin.com/in/venkateshsaraf

CAREER OBJECTIVE
Aspiring to join a Semiconductor Industry where I can apply my skills and knowledge to deliver value added results as
well as further enhance my learning and develop my career.

EDUCATION
Qualification
B.E.
(E & C)
12th Std
10th Std

University / Board
VTU, Belgaum
Dept. of PU
Education
KSEEB

Institution

Year of Passing

Aggregate

2014

60.56%

2010

72.33%

2008

91.36%

K. L. E. Institute of
Technology, Hubli
SMPU Science
College, Dharwad
SDM School,
Dharwad

PROJECTS UNDERTAKEN
I.

Arithmetic Logic Unit (ALU)

Arithmetic logic unit (ALU) is a Digital circuit that

performs arithmetic and bitwise logical operations
on integer binary numbers
This project involves the entire Chip Development
Cycle of Specification, Design, Simulation, Layout,
Verification and Documentation
I took the Lead in designing layout for
ADD_SUB_BIT1 which formed a major block.
Given Constraints:
2 inputs of 3bits each. 1 output of 5bits and a sign
bit. 3 control bits for 8 operations
1.8V supply voltage, Frequency of 10MHz,
Temperature variations of -40 C to 125 C
Implementation in GPDK 180nm technology
Performances Achieved:
A: No. of Transistors = 460 (W*L area = 74.52 sq.um)
B: Average supply current for all 8 operations (WC across
PVT) = 8.89uA
C: Delay b/n Input & Output (WC across PVT) = 1.4ns
D: Total Rectangular Layout Area = 2870.42 sq.um
FOM: (A*B*C*D) = 1.56 E-20 Coulomb.m2

III.

Band Gap Reference

A BGR is a temperature independent circuit that produces

constant reference voltage irrespective of power supply
variations and temperature changes.
Few Highlights that Ive implemented in BGR Layout:
Coaxial shielding technique for output Reference
voltages
Double guard rings for BJT and Placing of dummy
devices around BJTs
Interleaved pattern for Current Mirror, Resistors
and Common-Centroid for Differential pairs
Same routing pattern for Matched devices
BJT and Resistors kept close to each other

IV.

Power Management Module

A Power Management Module is voltage convertor/

regulator that convert input voltage to the output voltage
level that the circuit requires.
Few Highlights that Ive implemented in PM Layout:
Top-down floorplan approach
Reuse of Improvised BGR, Error amplifier and
Buffer blocks
Decaps to boost power supply and act as fillers
Design of Analog and Digital Power transistors
II.
5_Pack_Amplifier
with EM constraints as follows
Analog Layout Design of OPAMP
M1 M5 : 1um 0.5mA
Matching patterns for Current Mirror load and
M6 : 1um 3mA
(Power rails)
Differential pair
Hierarchical DRC and LVS verifications
Guard ring & Dummy FETs to protect transistors
Double contacts & Double guard rings for Power
Parasitic Extraction
MOSFETs

V.

Phase-Locked Loop

H-type clock routings to feed clock signals to

different blocks in order to achieve equal delay
As a lead, I took the responsibility to do top level
routings for Fractional Divider block
Design of 11 track PR Grid of height = 7.7um
Usage of Bindkeys to reduce time-to-market

A phase-locked loop is a feedback system combining a

voltage controlled oscillator (VCO) and a phase comparator
so connected that the oscillator maintains a constant
phase angle relative to a reference signal. Phase-locked
loops can be used, for example, to generate stable output
high frequency signals from a fixed low-frequency signal.
Few Highlights of Customer level PLL Layout design:
Top-down floorplan approach indicating the pin
positions, power rails and critical routings
Isolated Digital and Analog blocks
Performances Achieved:
Area = 1,67,824 sq.um ;
Aspect ratio = 1.25
Height = 459 um
;
Width = 365 um
I took the Lead for Fractional Divider block
which forms 60% of the whole Chip area
Fractional divider consisted of three sub blocks
namely Mash, Decoder and Integer Divider
High density and High performance layout

PROJECTS SUMMARY
Hands-on experience on various tools like
Cadence Virtuoso v6.1, Virtuoso Analog Design
Environment and Assura Physical Verification
Knowledge of Cadence SKILL and Perl
programming needed for Design Automation
In-depth knowledge of Fabrication steps, Analog,
Digital and Mixed signal Chips development
Architecture, Design, Layout and Verification
Knowledge on Reliability issues like Antenna
effects, Electromigration (EM), Electrostatic
discharge (ESD) and Latch-up
Good understanding of Circuit theory

CO - CURRICULAR ACTIVITIES
1. Elected as a President of Students Association (2014 batch) PHOENIX in ECE Dept, KLEIT Hubli.
2. Presented a paper on Built-In Self Test and Concurrent Testing for Digital Circuits at National Level Technical
fest in BVBCET [Pleiades13]
3. Presented a paper on Fuzzy logic and related applications in Accident Control at State Level Technical fest in
SDMCET [Techspin12]

ACHIEVEMENTS
1. Won Gold medals at Asian & International level Karate Tournaments in A.P. and Sri Lanka respectively.
2. Awarded as the Best Boy in High School for the Academic batch 2007-08.
3. Completed B and C certificates in NCC at the grade of Sergeant.

PERSONAL STRENGTHS

Quick learner
Self Motivated
Good analytical skill

Good presentation skill

Hard worker and Flexible
Problem solving skills

PERSONAL DETAILS

Date of Birth
Fathers Name
Passport number
Nationality
Languages known
Hobbies

:
:
:
:
:
:

26th March 1992

Laxman J Saraf
G7310095
Indian
English, Hindi, Kannada
Exploring things, Reading novels, Listening music, Physical fitness

DECLARATION
I hereby declare that the above mentioned particulars are true to the best of my knowledge and belief.
Place: Hubli

(Venkatesh Saraf)