Spartan-IIE™ LC

Development Board
User’s Guide

Version 1.0
March 2003
PN# DS-MANUAL-2SELC
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 Table of Contents

1 OVERVIEW ................................................................................................................... 1
2 THE SPARTAN-IIE LC DEVELOPMENT BOARD............................................................ 1
3 SPARTAN-IIE LC DEVELOPMENT BOARD BLOCK DIAGRAM ...................................... 2
3.1 SPARTAN-IIE DEVICE ................................................................................................ 3
3.2 SDRAM M EMORY .................................................................................................... 4
3.3 CLOCK G ENERATION ................................................................................................. 6
3.4 USER 7-S EGMENT D ISPLAY........................................................................................ 6
3.4.1 7-Segment Display Signal Description ............................................................. 6
3.5 USER LED .............................................................................................................. 7
3.6 USER PUSH B UTTON SWITCHES (SW5 AND SW6)......................................................... 7
3.6.1 User Push Button Switch Signal Assignments .................................................. 7
3.7 USER DIP SWITCH (SW4) ......................................................................................... 7
3.7.1 User DIP Switch Interface ............................................................................... 7
3.7.2 User DIP Switch Signal Assignments............................................................... 8
3.8 RS232 PORT .......................................................................................................... 8
3.8.1 RS232 Interface ............................................................................................. 8
3.8.2 RS232 Signal Descriptions .............................................................................. 9
3.8.3 RS232 Jumper Settings .................................................................................. 9
3.9 VGA PORT.............................................................................................................. 9
3.10 LCD CONNECTOR .................................................................................................. 11
3.11 JTAG CHAIN ......................................................................................................... 11
3.11.1 Using the RJ45 or PC3 Type JTAG Cable ...................................................... 12
3.11.2 JTAG Chain Jumper Settings ........................................................................ 13
3.12 SLAVE PARALLEL /SLAVE SERIAL PORT ...................................................................... 14
3.12.1 Slave Parallel ............................................................................................... 14
3.13 SLAVE SERIAL PORT ............................................................................................... 15
3.14 BANK I/O VOLTAGE................................................................................................. 15
3.14.1 Bank I/O Voltage Jumper Settings ................................................................. 15
3.15 ISP PROM ........................................................................................................... 16
3.16 PROGRAM SWITCH (SW2) ....................................................................................... 16
3.17 SPARTAN-IIE CONFIGURATION MODE S ELECT ............................................................ 16
3.18 P160 EXPANSION SLOT .......................................................................................... 18

March 10, 2003 i

 3.19 GENERAL PURPOSE I/O CONNECTOR ........................................................................ 20
3.20 SAM/GENERAL PURPOSE I/O CONNECTOR ................................................................ 20
3.20.1 SystemACE Controller Clock Input ................................................................ 21
4 DESIGN DOWNLOAD.................................................................................................. 24
4.1 JTAG INTERFACE................................................................................................... 24
4.1.1 Configuring the Spartan-IIE FPGA ................................................................. 24
4.1.2 Programming the XC18V02/04 ISP PROM..................................................... 25
4.2 SLAVE SERIAL INTERFACE........................................................................................ 25
4.3 SLAVE PARALLEL .................................................................................................... 25
REVISION HISTORY............................................................................................................ 26

March 10, 2003 ii

 Figures

FIGURE 1 – S PARTAN-IIE LC DEVELOPMENT BOARD ..................................................................... 2

FIGURE 2 - S PARTAN-IIE LC DEVELOPMENT BOARD BLOCK D IAGRAM.............................................. 3
FIGURE 3 - SDRAM INTERFACE ................................................................................................. 4
FIGURE 4 - 7-S EGMENT LED DISPLAY INTERFACE ......................................................................... 6
FIGURE 5 – USER DIP SWITCH INTERFACE .................................................................................. 8
FIGURE 6 – RS232 INTERFACE .................................................................................................. 9
FIGURE 7 - VGA CONNECTOR.................................................................................................. 10
FIGURE 8 – S PARTAN-IIE DEVELOPMENT BOARD JTAG CHAIN ...................................................... 12
FIGURE 9 - JTAG CONNECTION VIA PC3 TYPE CABLE ................................................................. 13
FIGURE 10 - USING THE RJ45 TYPE JTAG CABLE ...................................................................... 13
FIGURE 11 – SLAVE PARALLEL /SLAVE SERIAL CONNECTOR .......................................................... 14
FIGURE 12 – SLAVE PARALLEL MODE C ONFIGURATION ................................................................ 14
FIGURE 13 – SLAVE SERIAL MODE C ONFIGURATION .................................................................... 15
FIGURE 14 – ISP PROM INTERFACE ........................................................................................ 16
FIGURE 15 - SYSTEMACE MODULE BLOCK D IAGRAM .................................................................. 21
FIGURE 16- SYSTEMACE CONTROLLER CLOCK SOURCE ............................................................. 22
FIGURE 17 – D OWNLOAD SETUP .............................................................................................. 24

March 10, 2003 iii

 Tables

TABLE 1 - SDRAM SIGNAL ASSIGNMENTS ................................................................................... 5

TABLE 2 - S PARTAN-IIE DEVELOPMENT BOARD MASTER CLOCKS ..................................................... 6
TABLE 3 - 7-S EGMENT D ISPLAY SIGNAL D ESCRIPTIONS .................................................................. 7
TABLE 4 – USER LED S IGNAL ASSIGNMENTS ............................................................................... 7
TABLE 5 - USER P USH BUTTON SWITCH S IGNAL ASSIGNMENTS ....................................................... 7
TABLE 6 - USER DIP SWITCH S IGNAL ASSIGNMENTS ..................................................................... 8
TABLE 7 - RS232 S IGNAL D ESCRIPTIONS .................................................................................... 9
TABLE 8 - RS232 JUMPER S ETTINGS .......................................................................................... 9
TABLE 9 - VGA CONNECTOR S IGNAL ASSIGNMENTS.................................................................... 10
TABLE 10 - LCD SIGNAL ASSIGNMENTS ..................................................................................... 11
TABLE 11 - JTAG CHAIN JUMPER S ETTINGS .............................................................................. 13
TABLE 12 - BANK I/O VOLTAGE J UMPER S ETTINGS ...................................................................... 15
TABLE 13 - S PARTAN-IIE CONFIGURATION M ODE S ELECT ............................................................ 17
TABLE 14 – JX1 USER I/O CONNECTOR .................................................................................... 18
TABLE 15 – JX2 USER I/O CONNECTOR .................................................................................... 19
TABLE 16 – J7 USER I/O CONNECTOR ...................................................................................... 20
TABLE 17 - SYSTEMACE™ CONTROLLER CLOCK SOURCE ........................................................... 22
TABLE 18 - SAM/ G ENERAL-P URPOSE I/O (J29 CONNECTOR) ...................................................... 23

March 10, 2003 iv

1 Overview
The Spartan-IIE LC Development Kit provides a complete solution for developing designs and
applications based on the Xilinx Spartan-IIE FPGA family. The kit bundles an expandable
Spartan-IIE based development board with a power supply, user guide and reference designs.
P160 expansion modules available from Memec Design enable further application specific
prototyping and testing. Xilinx ISE software and a JTAG cable are available as kit options.

The Spartan-IIE LC development board utilizes the 300,000/600,000 gate Xilinx Spartan-IIE
device (XC2S300E-6FG456C or XC2S600E -6FG456C) in the 456 fine-pitch ball grid array
package. The high gate density and large number of user I/Os allows complete system solutions
to be implemented in the low cost FPGA. The development board includes 32M bytes of SDRAM,
two clock sources, 82 user I/O header pins via 2 on-board headers, an RS-232 port, a VGA
connector, an LCD connector, LED displays, switches and additional user support circuits. The
board supports the Memec Design P160 expansion module standard, which allows application-
specific expansion modules to be easily added. A SystemACE™ interface on the board gives
software designers the ability to run real-time operating systems (RTOS) from removable
CompactFlash cards when implementing embedded processor solutions.

The Spartan-IIE FPGA family has the advanced features needed to fit the most demanding, high
volume applications. The Spartan-IIE LC Development Kit provides an excellent platform to
explore these features so that you can quickly and effectively meet your time-to-market
requirements.

2 The Spartan-IIE LC Development Board

The Spartan-IIE LC development board provides the FPGA, support circuits and the expansion
slot for realizing advanced FPGA designs. Figure 1 shows a picture of the board and its features.

March 10, 2003 1

 SelectMAP
5V Input JTAG ISP PROM P160 SystemACE
Expansion

2S300E/600E

JTAG
SDRAM

100MHz
Clock
RS-232

User I/O
VGA

LCD

Figure 1 – Spartan-IIE LC Development Board

3 Spartan-IIE LC Development Board Block Diagram

A high-level block diagram of the Spartan-IIE LC development board is shown in Figure 2
followed by a brief description of each board sub-section.

March 10, 2003 2

 32MB

80-Pin Connector

80-Pin Connector
SDRAM

VGA P160 Module

Connector

RS232
Port

LCD
Connector System ACE
Connector

User Push
Switches (2)
JTAG Port
SPIIE FPGA
User DIP XC2S300E
Switches (8) or
JTAG Port
XC2S600E
(FG456)
User
LEDs (4)
ISP PROM
XC18V02/04
7-Segment
Display
SelectMap
Port
Clock Generator

User
OSC
I/O Header
(100MHz)

1.8V 2.5V 3.3V

OSC Socket
Regulator Regulator Regulator
(4/8-Pin)
Voltage Regulators

Figure 2 - Spartan-IIE LC Development Board Block Diagram

3.1 Spartan-IIE Device

The Spartan-IIE development board utilizes either the Xilinx Spartan-IIE XC2S300E -6FG456C or
XC2S600E-6FG456C. The Spartan-IIE 1.8V Field-Programmable Gate Array family gives users
high performance, abundant logic resources, and a rich feature set, all at an exceptionally low
price. The seven-member family offers densities ranging from 50,000 to 600,000 system gates
supporting 200Mhz designs and beyond.

Spartan-IIE devices deliver more gates, I/Os, and features per dollar than other FPGAs by
combining advanced process technology with a streamlined architecture based on the proven
Virtex™-E platform. Features include block RAM (up to 64K bits), distributed RAM (to 98,304
bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable
interconnect means that successive design iterations continue to meet timing requirements.

March 10, 2003 3

The Spartan-IIE family is a superior alternative to mask programmed ASICs. The FPGA avoids
the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA
programmability permits design upgrades in the field with no hardware replacement necessary
(impossible with ASICs).

3.2 SDRAM Memory

The Spartan-IIE LC development board provides 32MB of SDRAM memory (Infineon Mobile
SDRAM, # HYB25L128160AC-8). The high-level block diagram of the SDRAM interface is shown
below followed by a table describing the SDRAM memory interface signals.

OSC Data[15:0]
clk_in
100Mhz
Addr[13:0]

BA[1:0]
Push
Button reset
AUDQM
Switch
ALDQM

CSn 8M x 16
SDRAM
RASn

CASn

WEn

CLKE

CLK

Spartan-IIE
FPGA
Data[31:16]

BUDQM

BLDQM

8M x 16
SDRAM

Figure 3 - SDRAM Interface

March 10, 2003 4

 Table 1 - SDRAM Signal Assignments

Signal Name Description FPGA Pin #

A0 Address 0 Y13
A1 Address 1 Y16
A2 Address 2 Y17
A3 Address 3 W13
A4 Address 4 W10
A5 Address 5 Y9
A6 Address 6 W12
A7 Address 7 Y8
A8 Address 8 W9
A9 Address 9 W11
A10 Address 10 W16
A11 Address 11 Y7
A12 Address 12 W8
A12 Address 13 W6
DQ0 Data 0 AB6
DQ1 Data 1 AB7
DQ2 Data 2 AA7
DQ3 Data 3 AB8
DQ4 Data 4 AA8
DQ5 Data 5 AB9
DQ6 Data 6 AA9
DQ7 Data 7 AA10
DQ8 Data 8 W5
DQ9 Data 9 AA6
DQ10 Data 10 Y5
DQ11 Data 11 AB5
DQ12 Data 12 AA3
DQ13 Data 13 AA5
DQ14 Data 14 AB3
DQ15 Data 15 AB4
DQ16 Data 16 AB17
DQ17 Data 17 AB18
DQ18 Data 18 AA17
DQ19 Data 19 AB19
DQ20 Data 20 AA18
DQ21 Data 21 AB20
DQ22 Data 22 AA19
DQ23 Data 23 AA20
DQ24 Data 24 AB13
DQ25 Data 25 AA16
DQ26 Data 26 AA13
DQ27 Data 27 AB16
DQ28 Data 28 AB14
DQ29 Data 29 AA15
DQ30 Data 30 AA14
DQ31 Data 31 AB15
BA0 Bank Select 0 Y12
BA1 Bank Select 1 Y15
UDQM ALDQM W17
UDQM AUDQM W7
LDQM BLDQM W18

March 10, 2003 5

 LDQM BUDQM Y18
CSn Chip Select W15
RASn Row Address Strobe Y14
CASn Column Address Strobe Y11
WEn Write Enable W14
CLK Clock Y6
CKE Clock Enable Y10

3.3 Clock Generation

The Spartan-IIE LC development board provides two master clock inputs to the Spartan-IIE
FPGA. The following table provides a brief description of these clock signals.

Table 2 - Spartan-IIE development board Master Clocks

Signal Name Spartan-IIE Pin # Direction Description

CLK.CAN1 AA12 Input On-board 100 MHz Oscillator
FPGA.CLK AB12 Input On-board OSC Socket (2.5V OSC)

The Spartan-IIE development board provides two on-board oscillators. A fixed oscillator runs at
100Mhz (CLK.CAN1) and a user configurable 4/8-pin socket (FPGA.CLK) allows the addition of a
user-supplied device.

3.4 User 7-Segment Display

The Spartan-IIE LC development board utilizes a common-anode 7-segment LED displays that
can be used during the test and debugging phase of a design. The user can turn a given segment
ON by driving the associated signal low. The following figure shows the user 7-segment display
interface to the Spartan-IIE FPGA.

DISPLAY.1F A
DISPLAY.1G
DISPLAY.1E F B
DISPLAY.1D G
DISPLAY.1C
DISPLAY.1B E C
DISPLAY.1A
D

Figure 4 - 7-Segment LED Display Interface

3.4.1 7-Segment Display Signal Description

The following table shows the 7-Segment LED display pin descriptions.

March 10, 2003 6

 Table 3 - 7-Segment Display Signal Descriptions

Signal Name Spartan-IIE Description

Pin #
DISPLAY.1A V3 7-Segment LED Display1, Segment A
DISPLAY.1B V4 7-Segment LED Display1, Segment B
DISPLAY.1C W3 7-Segment LED Display1, Segment C
DISPLAY.1D T4 7-Segment LED Display1, Segment D
DISPLAY.1E T3 7-Segment LED Display1, Segment E
DISPLAY.1F U3 7-Segment LED Display1, Segment F
DISPLAY.1G U4 7-Segment LED Display1, Segment G

3.5 User LED

The Spartan-IIE LC development board provides a four user LEDs. The following table shows the
user LED pin assignments.

Table 4 – User LED Signal Assignments

Signal Name Spartan-IIE Description

Pin #
LED1 N1 LED1 is ON when the signal is low
LED2 N2 LED2 is ON when the signal is low
LED3 P1 LED3 is ON when the signal is low
LED4 P2 LED4 is ON when the signal is low

3.6 User Push Button Switches (SW5 and SW6)

The Spartan-IIE LC development board design provides two user push button switch inputs to the
Spartan-IIE FPGA. Each push button switch can be used to generate an active low signal.

3.6.1 User Push Button Switch Signal Assignments

The following table shows the pin assignments for the user push button switches.

Table 5 - User Push Button Switch Signal Assignments

Signal Name Spartan-IIE Description

Pin #
PUSH1 R1 User Push Button Switch Input 1 (SW3)
FPGA.RESETn R2 User Push Button/Reset Switch Input 2 (SW4)

3.7 User DIP Switch (SW4)

The Spartan-IIE LC development board provides 8 user switch inputs. These switches can be
statically set to a low or high logic level.

3.7.1 User DIP Switch Interface

The following figure shows the user DIP switch interface to the Spartan-IIE FPGA.

March 10, 2003 7

 SW4
Switch
DIP8
9 8
DIP7
DIP6
10 7
DIP5
11 6
DIP4 12 5
DIP3 13 4
14 3
DIP2
15 2
DIP1
16 1

Figure 5 – User DIP Switch Interface

3.7.2 User DIP Switch Signal Assignments

The following table shows the user switch pin assignments.

Table 6 - User DIP Switch Signal Assignments

Signal Name Spartan-IIE Pin # Description

DIP8 L1 User Switch Input 8
DIP7 L2 User Switch Input 7
DIP6 K1 User Switch Input 6
DIP5 K2 User Switch Input 5
DIP4 J1 User Switch Input 4
DIP3 J2 User Switch Input 3
DIP2 H1 User Switch Input 2
DIP1 H2 User Switch Input 1

3.8 RS232 Port

The Spartan-IIE LC development board provides an RS232 port that can be driven by the
Spartan-IIE FPGA. A subset of the RS232 signals are used on the Spartan-IIE development
board to implement this interface (RD and TD signals).

3.8.1 RS232 Interface

The Spartan-IIE LC development board provides a DB -9 connection for a simple RS232 port.
This board utilizes the Texas Instruments MAX3221 RS232 driver for driving the RD and TD
signals. The user provides the RS232 UART code, which resides in the Spartan-IIE FPGA.

March 10, 2003 8

 1
RXD
Din RS232 Dout RD
Drivers JP5 2 2
TXD Rout Rin
MAX3221

3
JD1
3 Connector

JP3
2 TD
3

Figure 6 – RS232 Interface

3.8.2 RS232 Signal Descriptions

The following table shows the RS232 signals and their pin assignments to the Spartan-IIE FPGA.

Table 7 - RS232 Signal Descriptions

Signal Name Spartan-IIE Pin # Description

RXD M4 Data Transmitted by FPGA
TXD M3 Data Received by FPGA

3.8.3 RS232 Jumper Settings

The following table shows the RS232 jumper settings.

Table 8 - RS232 Jumper Settings

JP3 JP3 JP5 JP5 Description

(1-2) (2-3) (1-2) (2-3)
Closed Open Closed Open DCE Mode – RD is input to the PC and TD is output from
PC
Open Closed Open Closed DTE Moe – RD is output from the PC and TD is input to
the PC

3.9 VGA Port

The Spartan-IIE LC development board provides a simple interface to a VGA monitor. The FPGA
signals are connected to the VGA connector via a simple “R-2R” resistor-ladder in order to
generate a suitable analog voltage for input to the VGA monitor. The following figure shows the
VGA connector along with the “R-2R” resistor-ladder.

March 10, 2003 9

 VGA.RED0
1
VGA.RED1
2
VGA.RED2
3
VGA.GREEN0
4
VGA.GREEN1
VGA.GREEN2 5

VGA.BLUE0 6

VGA.BLUE1 7

VGA.BLUE2 8

10

11

12
VGA.HSYNC
13
VGA.VSYNC
14

15

JD2

Figure 7 - VGA Connector

The following table shows the VGA pin assignments.

Table 9 - VGA Connector Signal Assignments

FPGA Signal FPGA Pin # VGA Connector (JD2) Pin # VGA Connector Signal
VGA.RED0 N3
VGA.RED1 N4 1 RED OUT
VGA.RED2 P3
VGA.GREEN0 N5
VGA.GREEN1 M6 2 GREEN OUT
VGA.GREEN2 M5
VGA.BLUE0 R4
VGA.BLUE1 R3 3 BLUE OUT
VGA.BLUE2 P4
GND NA 4 MONID2
GND NA 5 GND
NA NA 6 RED IN
NA NA 7 GREEN IN
NA NA 8 BLUE IN
NA NA 9 NC
GND NA 10 SYNC IN
GND NA 11 MONID0
NA NA 12 MONID1
VGA.HSYNC N6 13 HSYNC
VGA.VSYNC P5 14 VSYNC
NA NA 15 MONID3

March 10, 2003 10

3.10 LCD Connector
The Spartan-IIE LC development board provides an 8-bit interface to a 2x16 LCD panel. The
following table shows the LCD interface signals.

Table 10 - LCD Signal Assignments

Signal Spartan-IIE Description LCD Connector (J6)

Name Pin # Pin #
LCD.DB7 Y2 LCD Data Bit 7 14
LCD.DB6 Y1 LCD Data Bit 6 13
LCD.DB5 W2 LCD Data Bit 5 12
LCD.DB4 W1 LCD Data Bit 4 11
LCD.DB3 V2 LCD Data Bit 3 10
LCD.DB2 V1 LCD Data Bit 2 9
LCD.DB1 U2 LCD Data Bit 1 8
LCD.DB0 U1 LCD Data Bit 0 7
LCD.E T2 LCD Enable Signal 6
RW LCD Write Signal (this signal is connected 5
to logic “0” on the Spartan-IIE system
board).
LCD.RS T1 LCD Register Select Signal 4
VL LCD Contrast 3
GND LCD Ground 2
VDD LCD Power (+5V) 1

3.11 JTAG Chain

The following figure shows the JTAG chain on the Spartan-IIE LC development board.

March 10, 2003 11

 TDO

JP11
4
TDI
3

2
System
ACE TDI TDO 1 TDI TDO
Connector

TMS
TMS TMS

TCK
TCK TCK

PROM FPGA
14

13
12

11

JTAG
Port
JTAG Port (J2)
10

(JM1)
9
8

7
6

GND
4

3.3V
2

JTAG connection via JTAG connection via

RJ45 type cable Parallel Cable 3 (PC3) type cable

Figure 8 – Spartan-IIE development board JTAG Chain

3.11.1 Using the RJ45 or PC3 Type JTAG Cable

The following figures show how a PC3 type or RJ45 type JTAG cable can be connected to the
board. When the RJ45 type cable is connected to the JM1 connector, jumpers must be installed
on J2 pins 7-8, 9-10, 11-12, and 13-14. These jumpers connect the on-board JTAG circuitry to
the JTAG chain signals. For this reason, you cannot connect the RJ45 cable and the PC3 or PC4
JTAG cable at the same time. The jumpers on J2 actually prevent this from happening.

March 10, 2003 12

 TMS

14

13
TDI

12

11
JTAG Port (J2)
TDO

10

9
TCK

7
8
6

5
GND
4

3
2

1
3.3V

J2 Connector

JTAG connection via

Parallel Cable 3 (PC3) type cable

Figure 9 - JTAG Connection via PC3 Type Cable

14

13
12

11

JTAG
Port
10

(JM1)
9
8

7
6

5
4

3
2

J2 Connector

Figure 10 - Using The RJ45 Type JTAG Cable

3.11.2 JTAG Chain Jumper Settings

The following table shows the JTAG chain jumper setting on the Spartan-IIE development board.

Table 11 - JTAG Chain Jumper Settings

Jumper Setting Description

JP11 1-2 2-3 3-4
Closed Closed ISP PROM in the chain (normal operation)
Closed ISP PROM bypassed

March 10, 2003 13

3.12 Slave Parallel/Slave Serial Port
In addition to the JTAG mode, the Spartan-IIE FPGA on the Spartan-IIE LC development board
can be configured using the Slave Serial or the Slave Parallel mode of configuration. The
following figure shows the connector pin assignments for the Slave Serial/Slave Parallel port.

JP2
Slave Parallel/Slave Serial
Connector

CSn D0
1 2
DONE D1
3 4
CCLK D2
5 6
INITn D3
7 8
PROGRAMn D4
9 10
D5
11 12
RD/Wn D6
13 14
DOUT/BUSY D7
15 16

Figure 11 – Slave Parallel/Slave Serial Connector

3.12.1 Slave Parallel

In the Slave Parallel configuration mode, a byte of configuration data is loaded into the Spartan-
IIE FPGA during each CCLK clock cycle. In this mode, an external source drives the CCLK clock
and the data bus containing the configuration data. The following figure shows the Slave Parallel
configuration mode interface to the Spartan-IIE FPGA. The JP6 jumper must be installed
(position 2-3) for this mode of configuration.

D[0:7]
D[0:7]
DONE
DONE
CCLK
CCLK
INITn
INIT_B
Spartan-IIE
PROGRAMn
FPGA
PROG_B
RD/Wn
RDWR_B
DOUT/BUSY
BUSY
CSn
CS_B

Figure 12 – Slave Parallel Mode Configuration

March 10, 2003 14

3.13 Slave Serial Port
In the Slave Serial configuration mode, a bit of configuration data is loaded into the FPGA during
each CCLK clock cycle. In this mode, an external source places the most significant bit of each
byte on the DIN pin first and then drives the CCLK clock to store data into the FPGA. The
following figure shows the Slave Serial configuration mode interface to the Spartan-IIE FPGA.
The JP6 jumper must be installed (position 2-3) for this mode of configuration.

D0
DIN
DONE
DONE
CCLK
CCLK
Spartan-IIE
INITn
FPGA
INIT_B
PROGRAMn
PROG_B

Figure 13 – Slave Serial Mode Configuration

3.14 Bank I/O Voltage

The Spartan-IIE LC development board allows the Spartan-IIE I/O pins to be configured for 2.5V
or 3.3V operation. All Spartan-IIE user I/O pins are grouped in 8 different banks. Each bank of
I/O pins on the board can be configured to operate in the 2.5V or the 3.3V mode.

3.14.1 Bank I/O Voltage Jumper Settings

The following table shows the jumper settings for the Spartan-IIE bank I/O voltage (VCCO)
selection. Each bank can be set to 2.5V or 3.3V.

Table 12 - Bank I/O Voltage Jumper Settings

Bank # Spartan-IIE VCCO Pin # Jumper I/O Voltage

F7, F8, G9, G10 JP4
0 1-2 2-3
Closed Open 3.3V
Open Closed 2.5V
F15, F16, G13, G14 JP8
1 1-2 2-3
Closed Open 2.5V
Open Closed 3.3V
G17, H17, J16, K16 JP9
1-2 2-3
Closed Open 3.3V
2 Open Closed 2.5V
3, 6 Fixed 3.3V
4, 5 Fixed 2.5V
H6, G6, K7, J7 JP10
7 1-2 2-3
Closed Open 2.5V
Open Closed 3.3V

March 10, 2003 15

3.15 ISP PROM
The Spartan-IIE LC development board utilizes the Xilinx XC18V02 or XC18V04 ISP PROM,
allowing FPGA designers to quickly download revisions of a design and verify the design changes
in order to meet the final system-level design requirements. The XC18V02/04 ISP PROM uses
two interfaces to accomplish the configuration of the Spartan-IIE FPGA.

The JTAG port on the XC18V02/04 device is used to program the PROM with the design bit file.
Once the XC18V02/04 has been programmed, the user can configure the Spartan-IIE device in
Master Serial or Master SelectMap mode. The configuration of the Spartan-IIE device is initiated
by asserting the PROGn signal. Upon activation of the PROGn signal (by pressing the SW2
switch), the XC18V02/04 device will use its FPGA Configuration Port to configure the Spartan-IIE
FPGA.

XC18V02/04 ISP PROM Spartan-IIE FPGA

TDI
D0 D0
TMS
JTAG CE DONE
Port TCK
CCLK CCLK
TDO
RESET/OE INIT_B

CF PROG_B

Figure 14 – ISP PROM Interface

3.16 Program Switch (SW2)

The Spartan-IIE LC development board provides a push button switch for initiating the
configuration of the Spartan-IIE FPGA. This switch is used when the XC18V02/04 ISP PROM
configures the Spartan-IIE FPGA. After programming of the XC18V02/04 ISP PROM, this switch
can assert the PROGn signal. Upon activation of the PROGn signal, the XC18V02/04 ISP PROM
initiates the configuration of the Spartan-IIE FPGA.

3.17 Spartan-IIE Configuration Mode Select

The following table shows the Spartan-IIE Configuration Mode Select jumper settings.

March 10, 2003 16

 Table 13 - Spartan-IIE Configuration Mode Select

Mode PC Pull-up J1
1-2 (M0) 3-4 (M1) 5-6 (M2)
Master Serial No Closed Closed Closed
Master Serial Yes Closed Closed Open
Slave Serial No Open Open Open
Slave Serial Yes Open Open Closed
Slave Parallel No Closed Open Open
Slave Parallel Yes Closed Open Closed
JTAG No Open Closed Open
JTAG Yes Open Closed Closed

March 10, 2003 17

3.18 P160 Expansion Slot
A versatile expansion slot is implemented on the Spartan-IIE LC board, allowing application
specific cards or modules to be easily interfaced with the Spartan-IIE FPGA. The P160
Expansion Slot is made up of two 80-pin connectors yielding 110 user I/O signals to an add-on
module. The following tables show the Spartan-IIE pin assignments to the P160 Expansion Slot
connectors (JX1 & JX2) located on the Spartan-IIE LC development board.

Table 14 – JX1 User I/O Connector

FPGA I/O Connector I/O FPGA

Pin # Signal Name JX1 Pin # Connector Pin #
Signal
Name
TCK A1 B1 FPGA.BITSTREAM
NA GND A2 B2 SM.DOUT/BUSY
TMS A3 B3 FPGA.CCLK
NA Vin A4 B4 DONE
NA TDI A5 B5 INITn
NA GND A6 B6 PROGRAMn
NA TDO A7 B7 NC
NA 3.3V A8 B8 LIOB8 B7
C7 LIOA9 A9 B9 LIOB9 A6
NA GND A10 B10 LIOB10 B6
D7 LIOA11 A11 B11 LIOB11 A5
NA 2.5V A12 B12 LIOB12 B5
C6 LIOA13 A13 B13 LIOB13 A4
NA GND A14 B14 LIOB14 B4
D6 LIOA15 A15 B15 LIOB15 A3
NA Vin A16 B16 LIOB16 B3
C5 LIOA17 A17 B17 LIOB17 D3
NA GND A18 B18 LIOB18 E3
D5 LIOA19 A19 B19 LIOB19 F4
NA 3.3V A20 B20 LIOB20 F3
C4 LIOA21 A21 B21 LIOB21 G4
NA GND A22 B22 LIOB22 G3
F5 LIOA23 A23 B23 LIOB23 H4
NA 2.5V A24 B24 LIOB24 H3
G5 LIOA25 A25 B25 LIOB25 J4
NA GND A26 B26 LIOB26 J3
H5 LIOA27 A27 B27 LIOB27 K4
NA Vin A28 B28 LIOB28 K3
J6 LIOA29 A29 B29 LIOB29 L4
NA GND A30 B30 LIOB30 L3
J5 LIOA31 A31 B31 LIOB31 C2
NA 3.3V A32 B32 LIOB32 C1
K6 LIOA33 A33 B33 LIOB33 D2
NA GND A34 B34 LIOB34 D1
K5 LIOA35 A35 B35 LIOB35 E2
NA 2.5V A36 B36 LIOB36 E1
L6 LIOA37 A37 B37 LIOB37 F2
NA GND A38 B38 LIOB38 F1
L5 LIOA39 A39 B39 LIOB39 G2
NA Vin A40 B40 LIOB40 G1

March 10, 2003 18

 Table 15 – JX2 User I/O Connector

FPGA I/O I/O FPGA

Pin # Connector JX2 Pin # Connector Signal Pin #
Signal Name
Name
A7 RIOA1 A1 B1 GND NA
B8 RIOA2 A2 B2 RIOB2 E8
A8 RIOA3 A3 B3 Vin NA
B9 RIOA4 A4 B4 RIOB4 E9
A9 RIOA5 A5 B5 GND NA
B10 RIOA6 A6 B6 RIOB6 E10
A10 RIOA7 A7 B7 3.3V NA
B11 RIOA8 A8 B8 RIOB8 F10
D8 RIOA9 A9 B9 GND NA
C8 RIOA10 A10 B10 RIOB10 A12
D9 RIOA11 A11 B11 2.5V NA
C9 RIOA12 A12 B12 RIOB12 B12
D10 RIOA13 A13 B13 GND NA
C10 RIOA14 A14 B14 RIOB14 A13
D11 RIOA15 A15 B15 Vin NA
E11 RIOA16 A16 B16 RIOB16 B13
F11 RIOA17 A17 B17 GND NA
E12 RIOA18 A18 B18 RIOB18 A14
F12 RIOA19 A19 B19 3.3V NA
E13 RIOA20 A20 B20 RIOB20 B14
F13 RIOA21 A21 B21 GND NA
E14 RIOA22 A22 B22 RIOB22 A15
F14 RIOA23 A23 B23 2.5V NA
E15 RIOA24 A24 B24 RIOB24 B15
E16 RIOA25 A25 B25 GND NA
E17 RIOA26 A26 B26 RIOB26 A16
C12 RIOA27 A27 B27 Vin NA
D12 RIOA28 A28 B28 RIOB28 B16
C13 RIOA29 A29 B29 GND NA
D13 RIOA30 A30 B30 RIOB30 A17
C14 RIOA31 A31 B31 3.3V NA
D14 RIOA32 A32 B32 RIOB32 B17
C15 RIOA33 A33 B33 GND NA
D15 RIOA34 A34 B34 RIOB34 A18
C16 RIOA35 A35 B35 2.5V NA
D16 RIOA36 A36 B36 RIOB36 B18
C17 RIOA37 A37 B37 GND NA
D17 RIOA38 A38 B38 RIOB38 A19
C18 RIOA39 A39 B39 Vin NA
D18 RIOA40 A40 B40 RIOB40 B19

March 10, 2003 19

3.19 General Purpose I/O Connector
Two header connectors, J7 and J29 are provided for connection to general purpose I/O signals to
or from the FPGA. J7 is a 2 x 15 header at .1” centers, providing 26 user I/O signals plus voltage
and grounds.

Table 16 – J7 User I/O Connector

FPGA Pin # J7 Pin # FPGA Pin #

5.0V 1 2 3.3V
N20 3 4 N19
P20 5 6 P19
R20 7 8 T20
T19 9 10 U20
U19 11 12 V20
V19 13 14 L22
W22 15 16 M21
N22 17 18 N21
P21 19 20 R22
R21 21 22 T22
T21 23 24 U22
U21 25 26 V22
V21 27 28 W22
2.5V 29 30 GND

3.20 SAM/General Purpose I/O Connector

The Spartan-IIE LC development board provides a SystemACE™ connector that can be used to
configure the Spartan-IIE FPGA by using the Memec Design SystemACE module. The
SystemACE interface on the Spartan-IIE LC development board gives software designers the
ability to run real-time operating systems (RTOS) from removable CompactFlash cards. The
following figure shows a high-level block diagram of the Memec Design SystemACE module. For
more information, please refer to the Memec Design SystemACE module User’s Guide
document.

March 10, 2003 20

 CompactFlah
Connector
Parallel Cable IV

CompactFlah
Connector

Interface

Configuration
Connector

Connector
JTAG

JTAG

JTAG

JTAG
Port

Port
Test

SystemACE™
Controller

OSC
@242MHz

Reset MPU
Switch Interface

50-pin Connector
(connects to a 50-pin 0.1" square post header on the main board)

4 28 10 8

JTAG MPU Power &

Misc
Configuration Port Interface Ground
Signals

Figure 15 - SystemACE Module Block Diagram

3.20.1 SystemACE Controller Clock Input

The following figure shows the clocking scheme for the SystemACE controller. When the MPU
port of the SystemACE controller is used, the Spartan-IIE FPGA and the SystemACE controller
must use the same clock source. Hence, jumpers are provided on the Spartan-IIE development
board and the SystemACE module to provide the clock input to both devices. Two clocking
schemes are provided to ensure full synchronization of the MPU interface and also allow a

March 10, 2003 21

variable clock input to the SystemACE controller. The following table shows these two clocking
options.
Table 17 - SystemACE Controller Clock Source

Clock Source Jumper Settings

JP30 JP5
SystemACE module 24Mhz OSC Place jumper on pins 1-3 Open
Spartan-IIE development board OSC Place jumpers on pins 1-2 Closed
socket and 3-4
When this option is used, the OSC
must not exceed 33Mhz.

OSC
Socket

SystemACE™
Controller
JP30
2 4

OSC
@ 24MHz
1 3 EN

JP5

Pin AB12

SystemACE™ Module
Spartan-IIE FPGA

Spartan-IIE Development Board

Figure 16- SystemACE Controller Clock Source

The following table shows the SystemACE interface signals. A 50-pin 0.1” square post header
(JP29) is used to connect the SystemACE module to the Spartan-IIE LC development board.

March 10, 2003 22

 Table 18 - SAM/ General-Purpose I/O (J29 Connector)

SAM Signal FPGA Pin # JP29 Pin # FPGA Pin # SAM Signal
3.3V NA 1 2 NA 3.3V
TDO TDO 3 4 NA GND
TMS TMS 5 6 AB12 CLK
TDI TDI 7 8 NA GND
PROG PROG 9 10 TCK TCK
GND NA 11 12 NA GND
OEn D22 13 14 INTn INTn
A00 E22 15 16 D21 WEn
A02 F22 17 18 E21 A01
2.5V NA 19 20 F21 A03
D00 G22 21 22 NA 2.5V
D02 H22 23 24 G21 D01
D04 J22 25 26 H21 D03
D06 K22 27 28 J21 D05
D08 L21 29 30 K21 D07
D10 E20 31 32 D20 D09
D12 F20 33 34 E19 D11
D14 G20 35 36 F19 D13
A04 J20 37 38 G19 D15
A06 K20 39 40 J19 A05
IRQ L20 41 42 NA GND
RESETn L19 43 44 L18 CEn
DONE DONE 45 46 L17 BRDY
CCLK CCLK 47 48 C22 SM.D0
GND NA 49 50 NA GND

March 10, 2003 23

4 Design Download
The Spartan-IIE LC development board supports multiple methods of configuring the Spartan-IIE
FPGA. The JTAG port on the Spartan-IIE LC development board can be used to directly
configure the Spartan-IIE FPGA, or to program the on-board XC18V02/04 ISP PROM. Once the
ISP PROM is programmed, it can be used to configure the Spartan-IIE FPGA. The Slave
Parallel/Slave Serial port on this development board can also be used to configure the Spartan-
IIE FPGA. The following figure shows the setup for all Spartan-IIE FPGA configuration modes
that are supported on the Spartan-IIE LC development board.

Slave Serial/SelectMap

JP2
Parallel
Port JTAG

J2
Cable
SPIIE
Development
Board

JM1
PC
Adapter
AC/DC

JP1

Figure 17 – Download Setup

4.1 JTAG Interface

The J2 JTAG connector on the Spartan-IIE LC development board can be used to configure the
Spartan-IIE or to program the on-board XC18V02/04 ISP PROM. The Memec Design JTAG
cable is connected to the Spartan-IIE LC development board via J2 at one end and to the PC
parallel port at the other end.

Note: When using the standard JTAG cable, you will need to connect the JTAG and
VCC/GND signals to the top row of pins on J2. When using the low-cost RJ45 cable, you
will need to place jumpers on J2 as described in section 3.11.1

4.1.1 Configuring the Spartan-IIE FPGA

When the JTAG port is used to configure the Spartan-IIE FPGA, the following steps must be
taken:
• Using Table 13 set the Configuration Mode of the Spartan-IIE FPGA to JTAG Mode.
• Install JP6 jumper in the 1-2 position.
• Use the Xilinx JTAG programmer (iMPACT) utility to load the design bit file into the
Spartan-IIE FPGA. You will need to associate the ISP PROM with either a dummy .mcs

March 10, 2003 24

 file, or a .bsd file to allow the JTAG programming software to pass data through the ISP
PROM.

4.1.2 Programming the XC18V02/04 ISP PROM

When the JTAG port is used to program the ISP PROM, the following steps must be taken:
• Using Table 13 set the Configuration Mode of the Spartan-IIE FPGA to Master Serial
Mode.
• Install JP6 jumper in the 1-2 position.
• Use the Xilinx JTAG programmer utility (iMPACT) to load the design mcs file into the ISP
PROM. You will need to associate the FPGA with either a dummy .bit file or a .bsd file to
allow the JTAG programming software to pass data through the FPGA.
• Upon programming of the 18V02/04 ISP PROM, the on-board PROGn push button
switch (SW2) is used to initiate the Spartan-IIE FPGA configuration.

4.2 Slave Serial Interface

In this mode, an external source provides the configuration bit stream and the configuration clock
(CCLK) to the Spartan-IIE FPGA. Refer to Table 13 for setting up the Configuration Mode pins.
The JP6 jumper must be installed (position 2-3) for this mode of configuration.

4.3 Slave Parallel

In this mode, an external source provides the configuration bit stream and the configuration clock
(CCLK) to the Spartan-IIE FPGA. Refer to Table 13 for setting up the Configuration Mode pins.
The JP6 jumper must be installed (position 2-3) for this mode of configuration.

March 10, 2003 25

Revision History

V1.0 Initial Release 3/10/03

March 10, 2003 26