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HDL LAB

IVth Sem EC

H.D.L LAB
For IV Semester B.E

Electronics and Communication Engineering


(As per VTU Syllabus)

HDL MANUAL

EC Dept, RNSIT

HDL LAB
SL.NO
NAME OF THE EXPERIMENT
1
LOGIC GATES
2
ADDERS AND SUBTRACTORS
3
COMBINATIONAL DESIGNS
a.2 TO 4 DECODER
b.8 TO 3 ENCODER
c.8 TO 1 MULTIPLEXER
d.4 BIT BINARY TO GRAY CONVERTER
e. MULTIPLEXER, DE-MULTIPLEXER,
COMPARATOR
4
5
6
7

IVth Sem EC
PAGE NO
6
10
14

FULL ADDER(3 MODELING STYLES)


32 BIT ALU USING THE SCHEMATIC DIAGRAM
FLIP-FLOPS (SR, D, JK AND T)
4 BIT BINARY,BCD COUNTERS
SYNCHRONOUS & ASYNCHRONOUS COUNTERS

8
9

ADDITIONAL EXPERIMENTS
RING COUNTER
JHONSON COUNTER
INTERFACING

1
2
3
4

DC AND STEPPER MOTOR


EXTERNAL LIGHT CONTROL
WAVEFORM GENERATION USING DAC
SEVEN SEGMENT DISPLAY

32
37
40
45

48
51
52
56

EXPERIMENTS LIST (ACCORDING TO VTU SYLLABUS)


HDL MANUAL

EC Dept, RNSIT

HDL LAB

IVth Sem EC

PROGRAMMING (using VHDL and Verilog)


1.Write HDL code to realize all the gates.
2.Write a HDL program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
3. Write a HDL code to describe the functions of a full adder using three modeling
styles.
4. Write a model for 32 bit ALU using the schematic diagram shown below
A(31:0)

Opcode(3:0)

Enable
.

ALU should use the combinational logic to calculate an output based on the four
bit op-code input.
ALU should pass the result to the out bus when enable line in high, and tri-state
the out bus when the enable line is low.
ALU should decode the 4 bit op-code according to the given in example below.

OPCODE
1.
2.
3.
4.
5.
6.
7.
8.

ALU OPERATION
A+B
A-B
A Complement
A*B
A AND B
A OR B
A NAND B
A XNOR B

5. Develop the HDL code for the following flip-flop, SR, D, JK, T.
6. Design 4 bit binary , BCD counters (Synchronous reset and asynchronous reset) and
any sequence counters
INTERFACING (at least four of the following must be covered using VHDL/Verilog)
HDL MANUAL

EC Dept, RNSIT

HDL LAB

IVth Sem EC

1. Write HDL code display messenger on the given seven segment display and LCD
and accepting Hex key pad input data.
2. Write HDL code to control speed, direction of DC and stepper motor.
3. Write HDL code to accept 8 channel analog signal, Temperature sensors and
display the data on LC panel or seven segment display
4. Write HDL code to generate different waveforms (Sine, Square, Triangle,
Ramp etc.,)using DAC change the frequency and amplitude.
5. Write H DL code to simulate Elevator operation
6. Write HDL code to control external light using relays.
*******************

HDL MANUAL
HDL MANUAL

EC Dept, RNSIT

HDL LAB

IVth Sem EC

It is one of most popular software tool used to synthesize VHDL code. This tool
Includes many steps. To make user feel comfortable with the tool the steps are
given below: Double click on Project navigator. (Assumed icon is present on desktop).
Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name
: sample
Project location : C:\example
Top level module : HDL
In NEW PROJECT dropdown Dialog box, Choose your appropriate device
specification. Example is given below:
Device family
: Spartan2
Device
: xc2s200
Package
: PQ208
TOP Level Module : HDL
Synthesis Tool
: XST
Simulation
: Modelsim / others
Generate sim lang : VHDL
In source window right click on specification, select new source
Enter the following details
Entity: sample
Architecture : Behavioral
Enter the input and output port and modes.
This will create sample.VHDL source file. Click Next and finish the initial Project
preparation.

Double click on synthesis. If error occurs edit and correct VHDL code.
Double click on Lunch modelsim (or any equivalent simulator if you are using) for
functional simulation of your design.
Right click on sample.VHDL in source window, select new source
Select source
: Implementation constraints file.
File name
: sample
This will create sample. UCF constraints file.
Double click on Edit constraint (Text) in process window.
Edit and enter pin constraints with syntax:
NET NETNAME LOC = PIN NAME
Double click on Implement, which will carry out translate, mapping, place and route
of your design. Also generate program file by double clicking on it, intern which will
create .bit file.
Connect JTAG cable between your kit and parallel pot of your computer.
Double click on configure device and select mode in which you want to configure
your device. For ex: select slave serial mode in configuration window and finish
your configuration.
Right click on device and select program. Verify your design giving appropriate
inputs and check for the output.
Also verify the actual working of the circuit using pattern generator & logic
analyzer.

HDL MANUAL

EC Dept, RNSIT

HDL LAB

IVth Sem EC

EXPERIMENT NO. 1
WRITE HDL CODE TO REALIZE ALL LOGIC GATES
AIM: Simulation and realization of all logic gates.
COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.
Truth table with symbols

HDL MANUAL

EC Dept, RNSIT

HDL LAB
Black Box

IVth Sem EC
c

a
b

d
LOGIC
GATES

e
f
g
h
i

Truth table Basic gates:


a
b
c
d
e
VHDL CODE
0
0
0
0
1
library IEEE;
0
1
0
1
1
use IEEE.STD_LOGIC_1164.ALL;
1
0
0
1
0
use IEEE.STD_LOG IC_ARITH.ALL;
1
1
1
1
0
use IEEE.STD_LOGIC_UNSIGNED.ALL;

f
g
h
VERILOG CODE
1
1
0
module allgate ( a, b, y );
1
0
1
input a,b;
1
0
1
output [1:6] y;
0
0
0
assign y[1]= a & b;
assign y[2]= a | b,
assign y[3]= ~a ,
assign y[4]= ~(a & b),
assign y[5]= ~(a | b),
assign y[6]= a ^ b;
endmodule

entity gates is
Port ( a,b : in std_logic;
c,d,e,f,g,h,i : out std_logic);
end gates;

i
1
0
0
1

architecture dataflw of gates is


begin
c<= a and b;
d<= a or b;
e<= not a;
f<= a nand b;
g<= a nor b;
h<= a xor b;
i<= a xnor b;
end dataflw;
Procedure to view output on Model sim
1. After the program is synthesized create a Test bench, load the input.
2. Highlight the tbw file and click onto Modelsim Simulate behavioral model.
3. Now click the waveform and zoom it to view the result.
Modelsim Output

HDL MANUAL

EC Dept, RNSIT

HDL LAB

IVth Sem EC

Output (c to i)
PROCEDURE TO DOWNLOAD ONTO FPGA
1) Create a UCF(User Constraints File).
2) Click on UCF file and choose assign package pins option as shown in the figure
below.

3)Assign the package pins as shown in fig below


HDL MANUAL

EC Dept, RNSIT

HDL LAB

IVth Sem EC

3) save the file.


4) Click on the module and choose configure device option.
5) The following icon will be displayed.

6) Right click on the icon and select program option.


HDL MANUAL
9

EC Dept, RNSIT

HDL LAB
IVth Sem EC
7) Program succeeded message will be displayed.
8) Make connections to main board and daughter boards( before configuring ) , give
necessary inputs from DIP SWITCH and observe the output on LEDs.
NET "a" LOC = "p74" ;
NET "b" LOC = "p75" ;
NET "c" LOC = "p84" ;
NET "d" LOC = "p114" ;
NET "e" LOC = "p113" ;
NET "f" LOC = "p115" ;
NET "g" LOC = "p117" ;
NET "h" LOC = "p118" ;
NET "i" LOC = "p121" ;
Repeat the above Procedure to all the Programs.
RESULT: The logic gates design have been realized and simulated using HDL codes.

EXPERIMENT NO.2
HDL MANUAL

10

EC Dept, RNSIT

HDL LAB

IVth Sem EC

AIM: Write a HDL code to describe the functions of Half adder, Half Subtractor and Full
Subtractor.
COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.
(a) HALF ADDER
TRUTH TABLE
INPUTS

BASIC GATES
OUTPUTS

BOOLEAN

EXPRESSIONS:
S=A B
C=A B
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOG IC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HA is
Port ( a, b : in std_logic;
s, c : out std_logic);
end HA;

VERILOG CODE
module ha ( a, b, s, c)
input a, b;
output s, c;
assign s= a ^ b;
assign c= a & b;
endmodule

architecture dataflow of HA is
begin
s<= a xor b;
c<= a and b;
end dataflow;

(b)HALF SUBTRACTOR
TRUTH TABLE
HDL MANUAL

BOOLEAN EXPRESSIONS:
11

EC Dept, RNSIT

HDL LAB

IVth Sem EC
INPUTS
A
B

D=A B
_
Br = A B

OUTPUTS
D
Br

BASIC GATES

VHDL CODE

VERILOG CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOG IC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hs is
Port ( a, b : in std_logic;
d, br : out std_logic);
end hs;

module hs ( a, b, d, br)
input a, b;
output d, br;
assign d= a ^ b;
assign br= ~a & b;
endmodule

architecture dataflow of hs is
begin
d<= a xor b;
br<= (not a) and b;
end dataflow;

(C)FULL SUBTRACTOR
TRUTH TABLE
HDL MANUAL

BOOLEAN EXPRESSIONS:
12

EC Dept, RNSIT

HDL LAB
INPUTS

OUTPUTS

Cin

Br

1
1

1
1

0
1

0
1

0
1

IVth Sem EC
D= A B C
_

Br= A B + B Cin + A Cin

BASIC GATES

VHDL CODE

VERILOG CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOG IC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fs is
Port ( a, b, c : in std_logic;
d, br : out std_logic);
end fs;

module fs ( a, b, c, d, br)
input a, b, c;
output d, br;
assign d= a ^ b ^ c;
assign br=(( ~a)& (b ^ c)) | (b & c);
endmodule

architecture dataflw of fs is
begin
d<= a xor b xor c;
br<= ((not a) and (b xor c)) or (b and c);
end datafolw;
RESULT: The half adder, half subtractor and full subtractor designs have been realized and
simulated using HDL codes.

EXPERIMENT NO.3
AIM: Write HDL codes for the following combinational circuits.
HDL MANUAL

13

EC Dept, RNSIT

HDL LAB

IVth Sem EC

COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply.


3.a) 2 TO 4 DECODER
BLACK BOX
Sel 0
Sel 1

Y0

2 to 4

Y1
Y2
Y4

Decoder

Truth Table of 2 to 4 decoder


E
1
1
1
1
0

Sel1
0
0
1
1
X

Sel0
0
1
0
1
X

Y3
0
0
0
1
0

Y2
0
0
1
0
0

Y1
0
1
0
0
0

Y0
1
0
0
0
0

DATA FLOW
VHDL CODE

VERILOG CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

module dec2_4 (a,b,en,y0,y1,y2,y3)


input a, b, en;
output y0,y1,y2,y3;
assign y0= (~a) & (~b) & en;
assign y1= (~a) & b & en;
assign y2= a & (~ b) & en;
assign y3= a & b & en;
end module

entity dec2_4 is
port (a, b, en :in std_logic ;
y0, y1, y2, y3:out std_logic);
end dec2_4;
architecture data flow of dec2_4 is
begin
y0<= (not a) and (not b) and en;
y1<= (not a) and b and en;
y2<= a and (not b) and en;
y3<= a and b and en;
end dataflow;
NET "e" LOC = "p74";
NET "sel<0>" LOC = "p75";
NET "sel<1>" LOC = "p76";
HDL MANUAL

14

EC Dept, RNSIT

HDL LAB
NET "y<0>" LOC = "p112";
NET "y<1>" LOC = "p114";
NET "y<2>" LOC = "p113";
NET "y<3>" LOC = "p115";

IVth Sem EC

Simulation is done using Modelsim


Waveform window : Displays output waveform for verification.

Output

3.b) 8 TO 3 ENCODER WITH PRIORITY


Black Box
i7

Z3
8:3
Parity
Encoder

Z1
Z0
enx
V

i0
en

Truth table
En

I7

I6

HDL MANUAL

I5

I4

I3

I2

I1
15

I0

Z2

Z1

Z0

enx

EC Dept, RNSIT

HDL LAB
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0

X
1
1
1
1
1
1
1
0
X

X
1
1
1
1
1
1
0
X
X

X
1
1
1
1
1
0
X
X
X

X
1
1
1
1
0
x
X
X
X

X
1
1
1
0
X
X
X
X
X

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder8_3 is
Port ( i : in std_logic_vector(7 downto 0);
en : in std_logic;
enx,V : out std_logic;
z : out std_logic_vector(2 downto 0));
end enco2;
architecture behavioral of encoder8_3 is
begin

end behavioral ;

X
1
1
0
X
X
X
X
X
X

X
1
0
X
X
X
X
X
X
X

1
1
1
1
1
1
0
0
0
0

1
1
1
1
0
0
1
1
0
0

IVth Sem EC
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0

VERILOG CODE
module enc8_3 (I, en, y, v);
input [7:0]I;
input en;
output v;
output [2:0]y;
sig y; sig v;
always @ (en, I)
begin
if(en= =0)
v=0;
else
v=1;
end
if ( I[7]= =1 & en= =1)
y=3b111;
else if ( I[6]==1 & en==1)
else if ( I[5]==1 & en==1)
else if ( I[4]==1 & en==1)
else if ( I[3]==1 & en==1)
else if ( I[2]==1 & en==1)
else if ( I[1]==1 & en==1)
else if ( I[0]==1 & en==1)
else y=3b000;
end
end module

1
0
1
1
1
1
1
1
1
1

y=3b110;
y=3b101;
y=3b100;
y=3b011;
y=3b010;
y=3b001;
y=3b000;

#PACE: Start of Constraints generated by PACE


#PACE: Start of PACE I/O Pin Assignments
NET "en" LOC = "p84";
HDL MANUAL

16

EC Dept, RNSIT

HDL LAB
NET "i<0>" LOC = "p85";
NET "i<1>" LOC = "p86";
NET "i<2>" LOC = "p87";
NET "i<3>" LOC = "p93";
NET "i<4>" LOC = "p94";
NET "i<5>" LOC = "p95";
NET "i<6>" LOC = "p100";
NET "i<7>" LOC = "p74";
NET "enx" LOC = "p112";
NET "V" LOC = "p114";
NET "z<0>" LOC = "p113";
NET "z<1>" LOC = "p115";
NET "z<2>" LOC = "p117";

IVth Sem EC

Output

3.c) 8 TO 1 MULTIPLEXER
Black Box
a
b
c
d
e
f
g
h
sel (2 to 0)

8:1Mux

Truth table
Sel2
0
HDL MANUAL

Sel1
0

Sel0
0
17

Z
A
EC Dept, RNSIT

HDL LAB
0
0
0
1
1
1
1

0
1
1
0
0
1
1

VHDL CODE
entity mux8_1 is
port(I: in std_logic_vector (7 downto 0);
S: in std_logic_vector (2 downto 0);
en: in std_logic; y: out std_logic);
end mux8_1;
architecture behavioral of mux8_1 is
begin
process (I,s,en) is
begin
if en=1 then
if S=000 then y<=I(0);
elsif S=001 then y<=I(1);
elsif S=001 then y<=I(2);
elsif S=001 then y<=I(3);
elsif S=001 then y<=I(4);
elsif S=001 then y<=I(5);
elsif S=001 then y<=I(6);
else y<=I(7);
end if;
else y<=0;
end if;
end process;
end mux8_1;

HDL MANUAL

IVth Sem EC
B
C
D
E
F
G
H

1
0
1
0
1
0
1

VERILOG CODE
module mux8_1
input [7:0]I;
output [2:0]S;
output y;
input en;
reg y;
always @(en,S,I,y);
begin
if (en= =1)
begin
if (s= =000 y=I[0];
else if (s==001) y=I[1];
else if (s==001) y=I[2];
else if (s==001) y=I[3];
else if (s==001) y=I[4];
else if (s==001) y=I[5];
else if (s==001) y=I[6];
else if (s==001) y=I[7];
end
else y=0;
end
end
endmodule

18

EC Dept, RNSIT

HDL LAB

IVth Sem EC

Output

3.d)4-BIT BINARY TO GRAY COUNTER CONVERTER


Black Box
4 bit
Binary to

clk
en
rst

Truth table
Rst
Clk
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

HDL MANUAL

q(3 downto 0)

gray

En
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

19

G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

G2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

G1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

G0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

EC Dept, RNSIT

HDL LAB
VHDL CODE
entity bintogray is
Port ( rst,clk : in std_logic;
g : inout std_logic_vector(3 downto 0));
end bintogray;
architecture Behavioral of bintogray is
signal b: std_logic_vector( 3 downto 0);
begin
process(clk,rst)
begin
if rst='1' then b<="0000";
elsif rising_edge(clk) then
b<= b+1;
end if;
end process;
g(3)<= b(3);
g(2)<= b(3) xor b(2);
g(1)<= b(2) xor b(1);
g(0)<= b(1) xor b(0);
end Behavioral;

IVth Sem EC
VERILOG CODE
module b2g(b,g);
input [3:0] b;
output [3:0] g;
xor (g[0],b[0],b[1]),
(g[1],b[1],b[2]),
(g[2],b[2],b[3]);
assign g[3]=b[3];
endmodule

Binary to gray Output


PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "b<0>" LOC = "p84";
NET "b<1>" LOC = "p85";
NET "b<2>" LOC = "p86";
NET "b<3>" LOC = "p87";
NET "g<0>" LOC = "p112";
NET "g<1>" LOC = "p114";
NET "g<2>" LOC = "p113";
NET "g<3>" LOC = "p115";

HDL MANUAL

20

EC Dept, RNSIT

HDL LAB
3.e)MULTIPLEXER(4 TO 1)

IVth Sem EC

Black Box
a
4:1
Mux

b
c
d
sel (1 to 0)

Truth Table
Sel1
0
0
1
1

Sel0
0
1
0
1

Z
a
b
c
d

VHDL CODE
entity mux1 is
Port ( en,I : in std_logic;
sel:in std_logic_vector(1downto 0);
y : out std_logic);

VERILOG CODE
module mux4_1(I0,I1,I2,I3,s2,s1,y,en)
input I0,I1,I2,I3,s2,s1,en;
output y;
assigny<=((~s2)&(~s1)&en&I0)|
((~s2)&(s1)&en&I1)|(s2&(~s1)&en&I2)|
(s2&s1&en&I3);
dataflow of mux1 is endmodule

end mux1;
architecture
begin
z<= I0 when sel= "00" else
I1 when sel= "01" else
I2 when sel= "10" else
I3;
end dataflow;

( 4:1)Multiplexer Output

HDL MANUAL

21

EC Dept, RNSIT

HDL LAB
3.f) DE-MULTIPLEXER ( 1 TO 4)

IVth Sem EC

Black Box
a
en

1:4
Demux

Y(3 downto 0)

sel(1 downto 1)

Truth table
a
1
1
1
1
0

en
0
0
0
0
1

Sel1
0
0
1
1
X

Sel0
0
1
0
1
X

Y3
0
0
0
1
0

VHDL CODE
entity demux is
Port ( I,en : in std_logic;
sel: in std_logic_vector(1 downto 0);
y:outstd_logic_vector(3downto0));
end demux;
architecture dataflow of demux is
signal x: std_logic_vector( 1 downto 0);
begin
x<= en & a;
y <="0001" when sel="00" and x="01" else
"0010" when sel="01" and x="01" else
"0100" when sel="10" and x="01" else
"1000" when sel="11" and x="01" else
"0000";
end dataflow;

Y2
0
0
1
0
0

Y1
0
1
0
0
0

Y0
1
0
0
0
0

VERILOG CODE
module demux (s2,s1,I,en,y0,y1,y2,y3)
input s2,s1,I,en;
output y0,y1,y2,y3;
assign y0=(~s2)&(~s1)& I& en;
assign y1=(~s2)& s1& I& en;
assign y2=s2&(~s1)& I & en;
assign y3=s2& s1 & I & en;
endmodule

output

HDL MANUAL

22

EC Dept, RNSIT

HDL LAB
NET "a" LOC = "p84";
NET "en" LOC = "p85";
NET "sel<0>" LOC = "p86";
NET "sel<1>" LOC = "p87";
NET "y<0>" LOC = "p112";
NET "y<1>" LOC = "p114";
NET "y<2>" LOC = "p113"; NET "y<3>" LOC = "p115";

IVth Sem EC

Outp

3.g)1-BIT COMPARATOR (STRUCTURAL)


Black Box

L
1bit
Comparat
or

E
G

Truth table

a
0
0
1
1

HDL MANUAL

b
0
1
0
1

L
0
1
0
0

E
1
0
0
1

23

G
0
0
1
0

EC Dept, RNSIT

HDL LAB
VHDL CODE
entity b_comp1 is
port( a, b: in std_logic;
L,E,G: out std_logic);
end;
architecture structural of b_comp1 is
component not_2 is
port( a: in std_logic;
b: out std_logic);
end component;

IVth Sem EC
VERILOG CODE
module b_comp1 (a, b, L, E,G);
input a, b; output L, E, G;
wire s1, s2;
not X1(s1, a);
not X2 (s2, b);
and X3 (L,s1, b);
and X4 (G,s2, a);
xnor X5 (E, a, b);
end module

component and_2 is
port( a, b: in std_logic;
c: out std_logic);
end component;
component xnor_2 is
port( a, b: in std_logic;
c: out std_logic);
end component;
signal s1,s2: std_logic;
begin
X1: not_2 port map (a, s1);
X2: not_2 port map (a, s2);
X3: and_2 port map (s1, b, L);
X4: and_2 port map (s2, a, G);
X5: xnor_2 port map (a, b, E);
end structural;

output
NET "a" LOC = "p74" ;
NET "b" LOC = "p75" ;
NET "E" LOC = "p86" ;
NET "G" LOC = "p85" ;
NET "L" LOC = "p84" ;

HDL MANUAL

24

EC Dept, RNSIT

HDL LAB
1-BIT COMPARATOR(DATA FLOW)
VHDL CODE
entity bcomp is
port( a, b: in std_logic;
c, d, e: out std_logic);
end bcomp;
architecture dataflow of bcomp is
begin
c<= (not a) and b;
d<= a xnor b;
e<= a and (not b);
end dataflow;

IVth Sem EC
VERILOG CODE
module bcomp (a, b, c, d, e)
input a, b;
output c, d, e;
assign c= (~a) & b;
assign d= ~(a ^ b);
assign e= a & (~b);
end module

3.h)4-BIT COMPARATOR
Black Box
a(3 to 0)

x
4bit
Comparator

b(3 to 0)

VHDL CODE
entity compart4bit is
Port ( a,b : in std_logic_vector(3 downto 0);
aeqb,agtb,altb: out std_logic);

VERILOG CODE
module comp(a,b,aeqb,agtb,altb);
input [3:0] a,b;
output aeqb,agtb,altb;
reg aeqb,agtb,altb;

end compart4bit;
architecture Behavioral of
compart4bit is
begin
process (a,b)
begin
if a > b then aeqb<='1';agtb<=0;altb<=0;
elsif a < b then agtb<='1';aeqb<=0;altb<=0;
else altb<='1'; aeqb<=0; agtb<=0;
end if ;
end process;
end Behavioral;

HDL MANUAL

25

always @(a or b)
begin
aeqb=0; agtb=0;
if(a==b)
aeqb=1;
else if (a>b)

altb=0;

agtb=1;
else
altb=1;
end
endmodule

EC Dept, RNSIT

HDL LAB

IVth Sem EC

output
Greater than

Equal to

Less than

RESULT: Combinational designs have been realized and simulated using HDL codes.

HDL MANUAL

26

EC Dept, RNSIT

HDL LAB

IVth Sem EC

EXPERIMENT NO.4
AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.
COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.
DATA FLOW

Black box
a

Sum

FULL
ADDER

Cout

Truth table
INPUTS

OUTPUTS

a
0

b
0

cin
0

SUM
0

Cout
0

0
0

0
1

1
0

1
1

0
0

VHDL CODE
entity fulladder is
Port ( a,b,c : in std_logic;
s,cout : out std_logic);
end fulladr;
architecture data of fulladr is
begin
sum<=a xor b xor cin;
cout<= ( a and b) or ( b and cin) or ( cin and
a);
end data;

VERILOG CODE
module fulladder ( a, b, c,s,cout)
input a, b,c;
output s, cout;
assign s= a ^ b^c;
assign cout= a & b & c;
endmodule

BEHAVIORAL STYLE
HDL MANUAL

27

EC Dept, RNSIT

HDL LAB

IVth Sem EC

VHDL CODE
entity fulladder beh is
Port ( a,b,c : in std_logic;
sum,carry : out std_logic);
end fulladrbeh;

VERILOG CODE
module fulladd(cin,x,y,s,co);
input cin,x,y;
output s,co;
reg s,co;
always@(cin or x or y)
begin
case ({cin,x,y})

architecture Behavioral of fulladrbeh is


begin
process( a,b,c)
begin
if(a='0' and b='0' and c='0')
carry<='0';
elsif(a='0' and b='0' and c='1')
carry<='0';
elsif(a='0' and b='1' and c='0')
carry<='0';
elsif(a='0' and b='1' and c='1')
carry<='1';
elsif(a='1' and b='0' and c='0')
carry<='0';
elsif(a='1' and b='0' and c='1')
carry<='1';
elsif(a='1' and b='1' and c='0')
carry<='1';
else
sum<='1'; carry<='1';
end if;
end process;
end Behavioral;

STRUCTURAL STYLE
HDL MANUAL

then sum<='0';
then sum<='1';
then sum<='1';
then sum<='0';
then sum<='1';

3'b000:{co,s}='b00;
3'b001:{co,s}='b01;
3'b010:{co,s}='b01;
3'b011:{co,s}='b10;
3'b100:{co,s}='b01;
3'b101:{co,s}='b10;
3'b110:{co,s}='b10;
3'b111:{co,s}='b11;
endcase
end
endmodule

then sum<='0';
then sum<='0';

28

EC Dept, RNSIT

HDL LAB

IVth Sem EC

VHDL CODE
entity fullstru is
Port ( a,b,cin : in std_logic;
sum,carry : out std_logic);
end fullstru;

VERILOG CODE
module fa (x,y,z,cout,sum);
input x,y,z;
output cout,sum;
wire P1,P2,P3;

architecture structural of fullstru is

HA HA1 (sum(P1),cout(P2),a(x), b(y));


HA HA2 (sum(sum),carry(P3),a(P1),b(Z));
OR1 ORG (P2,P3, Cout);

signal c1,c2,c3:std_logic;
component xor_3
port(x,y,z:in std_logic;
u:out std_logic);
end component;

endmodule

component and_2
port(l,m:in std_logic;
n:out std_logic);
end component;
component or_3
port(p,q,r:in std_logic;
s:out std_logic);
end component;
begin
X1: xor_3 port map ( a, b, cin,sum);
A1: and_2 port map (a, b, c1);
A2: and_2 port map (b,cin,c2);
A3: and_2 port map (a,cin,c3);
O1: or_3 port map (c1,c2,c3,carry);
end structural;

HDL MANUAL

29

EC Dept, RNSIT

HDL LAB

IVth Sem EC

Supporting Component Gates for Stuctural Full Adder


//and gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and2 is
Port ( l,m : in std_logic;
n : out std_logic);
end and2;
architecture dataf of and2 is
begin
n<=l and m;
end dataf;
//or gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or3 is
Port ( p,q,r : in std_logic;
s : out std_logic);
end or3;
architecture dat of or3 is
begin
s<= p or q or r;
end dat;
//xor gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor3 is
Port ( x,y,z : in std_logic;
u : out std_logic);
end xor3;
architecture dat of xor3 is
begin
u<=x xor y xor z;
end dat;
Full adder data flow i/o pins

HDL MANUAL

30

EC Dept, RNSIT

HDL LAB
NET "a" LOC = "P74";
NET "b" LOC = "P75";
NET "cin" LOC = "P76";
NET "cout" LOC = "P84";
NET "sum" LOC = "P85";

IVth Sem EC

Sum output carryoutput


RESULT: Three modeling styles of full adder have been realized and simulated using HDL.
codes.

HDL MANUAL

31

EC Dept, RNSIT

HDL LAB

IVth Sem EC

EXPERIMENT NO. 5
AIM: Write a model for 32 bit ALU using the schematic diagram shown below.
COMPONENTS REQUIRED:FPGA/CPLD board, FRCs, jumper and power supply.
OPCODE
1
2
3
4
5
6
7
8
9
10
11

ALU OPERATION
A+B
A-B
A Complement
A*B
A and B
A or B
A nand B
A xor B
Right shift
Left Shift
Parallel load

Black box
A1(3 to 0)
B1(3 to 0)
ALU

Zout (7 downto 0)

opcode (2 to 0)

Truth table
Operation
A+B
A-B
A or B
A and B
Not A
A1*B1
A nand B
A xor B

HDL MANUAL

Opcode
000
001
010
011
100
101
110
111

A
1111
1110
1111
1001
1111
1111
1111
0000

B
0000
0010
1000
1000
0000
1111
0010
0100

32

Zout
00001111
00001100
00001111
00001000
11110000
11100001
11111101
00000100

EC Dept, RNSIT

HDL LAB

IVth Sem EC

VHDL CODE
entity alunew is
Port( a1,b1:in std_logic_vector(3 downto 0);
opcode : in std_logic_vector(2 downto 0);
zout : out std_logic_vector(7 downto 0));
end alunew;
architecture Behavioral of alunew is
signal a: std_logic_vector( 7 downto 0);
signal b: std_logic_vector( 7 downto 0);
begin
a<= "0000" & a1;
b<= "0000" & b1;
zout<= a+b
when opcode ="000" else
a-b
when opcode ="001" else
a or b when opcode ="010" else
a and b when opcode ="011" else
not a when opcode ="100" else
a1 * b1 when opcode ="101" else
a nand b when opcode ="110" else
a xor b;
end Behavioral;

VERILOG CODE
module ALU ( a, b, s, en, y );
input signal [3:0]a, b;
input [3:0]s;
input en;
output signal [7:0]y;
reg y;
always@( a, b, s, en, y );
begin
if(en==1)
begin
case
4d0: y=a+b;
4d1: y=a-b;
4d2: y=a*b;
4d3: y={4 bww, ~a};
4d4: y={4 d0, (a & b)};
4d5: y={4 d0, (a | b)};
4d6: y={4 d0, (a ^ b)};
4d7: y={4 d0, ~(a & b)};
4d8: y={4 d0, ~(a | b)};
4d9: y={4 d0, ~(a ^ b)};
default: begin end
end case
end
else
y=8d0;
end
endmodule

RESULT: 32 bit ALU operations have been realized and simulated using HDL codes.

HDL MANUAL

33

EC Dept, RNSIT

HDL LAB

IVth Sem EC

EXPERIMENT NO.6
AIM: Develop the HDL code for the following flipflop: T, D, SR, JK.
COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply.
T FLIPFLOP
Black Box
t
clk
rst

q
T ff

qb

VHDL CODE
entity tff is
Port ( t,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end tff;
architecture Behavioral of tff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process (clk)
variable temp:std_logic:='0';
begin
if rising_edge(clk) then
if (t='1') then
temp:=not temp;
else
temp:=temp;
end if;
end if;
q<=temp;qb<=not temp;
end process;
end Behavioral;

HDL MANUAL

VERILOG CODE
module tff(t,clk,rst, q,qb);
input t,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0) begin
if(t==1) begin
temp=~ temp;
end
else
temp=temp;
end
q=temp;qb=~temp;
end
endmodule

34

EC Dept, RNSIT

HDL LAB

IVth Sem EC

Truth table
Rst
1
1
1
0

T
0
1
X
X

Clk
1
1
No +ve edge
X

q
q
qb
Previous state
0

Rising edge
Output
D FLIPFLOP
Black Box
d
D FF
clk

q
qb

VHDL CODE
entity dff is
Port ( d,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process (clk)
variable temp: std_logic;
begin
if rising_edge(clk) then
temp:=d;
end if;
q<=temp;qb<=not temp;
end process;
end Behavioral;

HDL MANUAL

VERILOG CODE
module dff(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0)
temp=d;
else
temp=temp;
q=temp;
qb=~ temp ;
end
endmodule

35

EC Dept, RNSIT

HDL LAB

IVth Sem EC

Truth table
clk
X
1
1

d
1
1
0

q
1
1
0

qb
0
0
1

Output at rising edge


NET "clk" LOC = "P18";
NET "d" LOC = "P74";
NET "q" LOC = "P84";
NET "qb" LOC = "P85";
SR FLIPFLOP
Black Box
clk
s
r
rst
pr

SR FF

qb

Truth table
rst
1
0
0
0
0
0

pr
X
1
0
0
0
0

HDL MANUAL

Clk
X
X
1
1
1
1

s
X
X
0
0
1
1

r
X
X
0
1
0
1

36

q
0
1
Qb
0
1
1

qb
1
0
Qbprevious
1
0
1

EC Dept, RNSIT

HDL LAB
VHDL CODE
entity srff is
Port ( s,r,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end srff;
architecture Behavioral of srff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clk,rst)
variable sr:std_logic_vector(1 downto 0);
variable temp1,temp2:std_logic:='0';
begin
sr:=s&r;
if (rst ='0')then
if rising_edge(clk) then
case sr is
when "01"=> temp1:='0'; temp2:='1';
when "10"=> temp1:='1'; temp2:='0';
when "11"=> temp1:='1'; temp2:='1';
when others=> null;
end case;
end if;
else temp1:='0'; temp2:='1';
end if;
q<=temp1;qb<=temp2;
end process;
end Behavioral;

IVth Sem EC
VERILOG CODE
module srff(s,r,clk,rst, q,qb);
input s,r,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]sr;
always@(posedge clk,posedge rst)
begin
sr={s,r};
if(rst==0)
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else
begin
q=1'b0;
end
qb=~q;
end
endmodule

R
output

HDL MANUAL

37

EC Dept, RNSIT

HDL LAB

IVth Sem EC

JK FLIPFLOP
Black Box
j
k

JK FF

clk

q
qb

rst
VHDL CODE
entity jkff is
Port ( j,k,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clk,rst)
variable jk:std_logic_vector(1 downto 0);
variable temp:std_logic:='0';
begin
jk:=j&k;
if (rst ='0')then
if rising_edge(clk) then
case jk is
when "01"=> temp:='0';

VERILOG
module jkff(j,k,clk,rst, q,qb);
input j,k,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]jk;
always@(posedge clk,posedge rst)
begin
jk={j,k};
if(rst==0)
begin
case (jk)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=~q;
default: begin end
endcase
end
else

when "10"=> temp:='1';


when "11"=> temp:=not temp;
when others=> null;
end case;
end if;
else temp:='0';
end if;
q<=temp;
qb<=not temp;
end process;

end
endmodule

q=1'b0;
qb=~q;

end Behavioral;
HDL MANUAL

38

EC Dept, RNSIT

HDL LAB

IVth Sem EC

Truth table
Rst
1
1
1
1
1
0

Clk
1
1
1
1
No+ve egde
-

J
0
0
1
1
-

K
0
1
0
1
-

Q
Previous
0
1
Qb
Previous
0

Qb
state
1
0
Q
state
1

Output(when input 00 and rising edge)


NET "clk" LOC = "p18";
NET "j" LOC = "p84";
NET "k" LOC = "p85";
NET "rst" LOC = "p86";
NET "q" LOC = "p112";
NET "qb" LOC = "p114";
RESULT: Flip-flop operations have been realized and simulated using HDL codes

HDL MANUAL

39

EC Dept, RNSIT

HDL LAB

IVth Sem EC

EXPERIMENT NO.7
AIM: Design 4 bit Binary, BCD counter ( Synchronous reset and Asynchronous reset and
any sequence counters.
COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply.
a)BCD COUNTER
Black Box
clk
rst

q(3 downto 0)

Bcd
counter

Truth table
Rst
1
0
0
0
0
0
0
0
0
0

HDL MANUAL

Clk
X
1
1
1
1
1
1
1
1
1

Q
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

40

EC Dept, RNSIT

HDL LAB
VHDL CODE
entity bcd is
Port ( clr,clk,dir : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3
downto 0);
tc : out STD_LOGIC);
end bcd;
architecture Behavioral of bcd is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0);
begin
if(clr='1')then
temp:="0000";tc<='0';
elsif rising_edge(clkd(21)) then
if (dir='1') then
temp:=temp+1;
elsif(dir='0') then
temp:=temp-1;
end if;
if(dir='1' and temp="1010") then
temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then
temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;

IVth Sem EC
VERILOG CODE
module bcd(clr,clk,dir, tc, q);
input clr,clk,dir;
output reg tc;
output reg[3:0] q;
always@(posedge clk,posedge clr)
begin
if(clr==1)
q=4'd0;
else
begin
if (dir==1)
q=q+1;
else if(dir==0)
q=q-1;
if(dir==1 & q==4'd10)
begin
q=4'd0;tc=1'b1;
end
else if(dir==0 & q==4'd15)
begin
q=1'd9;tc=1'b1;
end
else tc=1'b0;
end
end
endmodule

end Behavioral;

HDL MANUAL

41

EC Dept, RNSIT

HDL LAB

IVth Sem EC

b)GRAY COUNTER
Black Box
clk
en
rst

4 bit
Binary to

q(3 downto 0)

gray

VHDL CODE
entity gray is
Port ( clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2
downto 0));
end gray;
architecture Behavioral of gray is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clr,clkd)
variable temp:std_logic_vector(2 downto 0);
begin
if(clr='0') then
if rising_edge(clkd(21)) then
case temp is
when "000"=> temp:="001";
when "001"=> temp:="011";
when "011"=> temp:="010";
when "010"=> temp:="110";
when "110"=> temp:="111";
when "111"=> temp:="101";
when "101"=> temp:="100";
when "100"=> temp:="000";
when others => null;
end case;
end if;
else temp:="000";
end if;
q<=temp;
end process;
end Behavioral;
HDL MANUAL

VERILOG CODE
module gray(clr,clk, q);
input clr,clk;
output reg[2:0] q;
reg temp=3'd0;
always@(posedge clk,posedge clr)
begin
if(clr==0)
begin
case(temp)
3'd0:q=3'd1;
3'd1:q=3'd3;
3'd2:q=3'd6;
3'd3:q=3'd2;
3'd6:q=3'd7;
3'd7:q=3'd5;
3'd5:q=3'd4;
3'd4:q=3'd0;
endcase
end
else q=3'd0;
end
endmodule

42

EC Dept, RNSIT

HDL LAB

IVth Sem EC

Truth table
Rst
1
0
0
0
0
0
0
0
0
0

Clk
X
1
1
1
1
1
1
1
1
1

HDL MANUAL

En
0
1
1
1
1
1
1
1
1
1

B3
0
0
0
0
0
0
0
0
1
1

B2
0
0
0
0
1
1
1
1
0
0

B1
0
0
1
1
0
0
1
1
0
0

B0
0
1
0
1
0
1
0
1
0
1
43

G3
0
0
0
0
0
0
0
0
1
1

G2
0
0
0
0
1
1
1
1
1
1

G1
0
0
1
1
1
1
0
0
0
0

G0
0
1
1
0
0
1
1
0
0
1

EC Dept, RNSIT

HDL LAB
0
1
0
1
0
1
0
1
0
1
0
1

1
1
1
1
1
1

1
1
1
1
1
1

0
0
1
1
1
1

1
1
0
0
1
1

0
1
0
1
0
1

IVth Sem EC
1
1
1
1
0
1
0
1
0
0
0
0

1
1
1
1
1
1

1
0
0
1
1
0

BINARY COUNTER(UP/DOWN)
Black Box
clk
rst

Binary
counter

qout(3 dt 0)

Truth table
Clk
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Rst
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

VHDL CODE
entity bin_as is
Port ( dir,clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3
downto 0));
end bin_as;
architecture Behavioral of bin_as is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
HDL MANUAL

Qout
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VERILOG
module bin_as(clk,clr,dir, temp);
input clk,clr,dir;
output reg[3:0] temp;
always@(posedge
clk,posedge clr)
begin
if(clr==0)
begin
if(dir==0)
temp=temp+1;
44

EC Dept, RNSIT

HDL LAB
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;

IVth Sem EC
else temp=temp-1;
end
else
temp=4'd0;
end
endmodule

process(clkd)
variable temp:std_logic_vector(3 downto
0):="0010";
begin
if rising_edge(clkd(21)) then
if (clr='0') then
if (dir='1') then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;
end Behavioral;

Output 0000

HDL MANUAL

Output 1111

45

EC Dept, RNSIT

HDL LAB

IVth Sem EC

RESULT: Asynchronous and Synchronous counters have been realized and simulated using
HDL codes.

ADDITIONAL EXPERIMENTS

EXPERIMENT NO.8
AIM: Simulation and realization of Ring counter.
COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply.
RING COUNTER
HDL MANUAL

46

EC Dept, RNSIT

HDL LAB

HDL MANUAL

IVth Sem EC

47

EC Dept, RNSIT

HDL LAB

IVth Sem EC

INTERFACING PROGRAMS
1.WRITE A HDL CODE TO CONTROL THE SPEED, DIRECTION OF
DC & STEPPER MOTOR
DC MOTOR
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
HDL MANUAL

48

EC Dept, RNSIT

HDL LAB
use IEEE.STD_LOGIC_UNSIGNED.ALL;

IVth Sem EC

entity dcmotr is
Port ( dir,clk,rst : in std_logic;
pwm : out std_logic_vector(1 downto 0);
rly : out std_logic;
row : in std_logic_vector(0 to 3));
end dcmotr;
architecture Behavioral of dcmotr is
signal countr: std_logic_vector(7 downto 0);
signal div_reg: std_logic_vector(16 downto 0);
signal ddclk,tick: std_logic;
signal duty_cycle:integer range 0 to 255;
begin
process(clk,div_reg)
begin
if(clk'event and clk='1') then
div_reg<=div_reg+'1';
end if;
end process;
ddclk<=div_reg(12);
tick<= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
when"1110"=> duty_cycle<=255;
when"1101"=> duty_cycle<=200;
when"1011"=> duty_cycle<=150;
when"0111"=> duty_cycle<=100;
when others => duty_cycle<=100;
end case;
end if;
end process;
process(ddclk, rst)
begin
if rst='0'then countr<=(others=>'0');
pwm<="01";
elsif(ddclk'event and ddclk='1') then
countr<= countr+1;
if countr>=duty_cycle then
pwm(1)<='0';
else pwm(1)<='1';
end if;
end if;
end process;
rly<='1' when dir='1' else '0';
HDL MANUAL

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EC Dept, RNSIT

HDL LAB

IVth Sem EC

end Behavioral;
2. DC MOTOR

NET "CLK" LOC="p18";


NET "RESET" LOC="p74";
NET "dir" LOC="p75";
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141";
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";
PRODEDURE:1) Make connection between FRC 9 and FPGA board to the dc motor
connector of VTU card 2
2) Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 2
3) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV
card 2.
4) Connect the down loading cable and power supply to FPGA board.
5) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
6) Make the reset switch on.
7) Press the Hex keys and analyze speed changes for dc motor.
RESULT: The DC motor runs when reset switch is on and with pressing of different keys
variation of DC motor speed was noticed.

STEPPER MOTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity steppermt is
Port ( clk,dir,rst : in std_logic;
dout : out std_logic_vector(3 downto 0));
end steppermt;
architecture Behavioral of steppermt is
signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15
signal shift_reg:std_logic_vector(3 downto 0);
begin
process(clk)
HDL MANUAL

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EC Dept, RNSIT

HDL LAB
IVth Sem EC
begin
if rising_edge (clk) then
clk_div <= clk_div+'1';
end if;
end process;
process(rst,clk_div(15))
-- speed is maximum at 15
begin
if rst='0' then shift_reg<="0001";
elsif rising_edge (clk_div(15)) then
if dir='1' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<= shift_reg ( 2 downto 0) & shift_reg(3);
end if;
end if;
end process;
dout<= shift_reg;
end Behavioral;
NET "clk" LOC = "p18"; NET "dir" LOC = "p85";
NET "rst" LOC = "p84";
NET "dout<0>" LOC = "p7"; NET "dout<1>" LOC = "p5";
NET "dout<2>" LOC = "p3"; NET "dout<3>" LOC = "p141";
PROCEDURE:1) Make connection between FRC 9 and FPGA board to the stepper motor
connector of
VTU card 1
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of
VTU card 1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Visualize the speed variation of stepper motor by changing counter value in the
program.
RESULT: The stepper motor runs with varying speed by changing the counter value

2.WRITE A HDL CODE TO CONTROL EXTERNAL LIGHTS USING


RELAYS
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
HDL MANUAL
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EC Dept, RNSIT

HDL LAB

IVth Sem EC

entity externallc is
Port ( cnt : in std_logic;
light : out std_logic);
end externallc;
architecture Behavioral of externallc is
begin
light<=cnt;
end Behavioral;
NET "cnt" LOC = "p74";
NET "light" LOC = "p7";
PROCEDURE:
1.Make the connections b/w FRC9 of fpga board to external light connector of vtu card 2
2.Make connection b/w FRC1 of fpga board to the dip switch connector of vtucard2
3.Connect the Downloading cable and power supply to fpga board.
1. Then open the xilinx impact software select the slave serial mode and select
respective bit file and click program
2. Make the reset switch on and listen to the tick sound.
RESULT: Once the pin p74 (reset) is switched on the tick sound is heard at the external light
junction.

3.WRITE
HDL
CODE
TO
GENERATE
DIFFERENT
WAVEFORMS(SAWTOOTH, SINE WAVE, SQUARE, TRIANGLE,
RAMP ETC) USING DAC CHANGE THE FREQUENCY AND
AMPLITUDE.
SAWTOOTH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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EC Dept, RNSIT

HDL LAB
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

IVth Sem EC

entity sawtooth is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end sawtooth;
architecture Behavioral of sawtooth is
signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+1;
end if;
end process;
dac<=cnt;
end Behavioral;

SQUARE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity squarewg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end squarewg;
architecture Behavioral of squarewg is
signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector(0 to 7);
signal en: std_logic;
begin
HDL MANUAL

53

EC Dept, RNSIT

HDL LAB
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;

IVth Sem EC

process(temp(3))
begin
if rst='1' then cnt<="00000000";
elsif rising_edge (temp(3)) then
if cnt< 255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process;
end Behavioral;

TRIANGLE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end triangwg;
architecture Behavioral of triangwg is
signal temp: std_logic_vector( 3 downto 0);
signal cnt: std_logic_vector(0 to 8);
signal en:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+1;
end if;
end process;
process( temp(3))
begin
if rst='1' then cnt<="000000000";
HDL MANUAL

54

EC Dept, RNSIT

HDL LAB
elsif rising_edge(temp(3)) then
cnt<=cnt+1;
if cnt(0)='1' then
dac<=cnt(1 to 8);
else
dac<= not(cnt( 1 to 8));
end if;
end if;
end process;

IVth Sem EC

end Behavioral;

RAMP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rampwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end rampwg;
architecture Behavioral of rampwg is
signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+15;
end if;
end process;
dac<=cnt;
end Behavioral;

SINE WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
HDL MANUAL

55

EC Dept, RNSIT

HDL LAB
use IEEE.STD_LOGIC_UNSIGNED.ALL;

IVth Sem EC

entity sinewave is
Port ( clk,rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end sinewave;
architecture Behavioral of sinewave is
signal temp: std_logic_vector(3 downto 0);
signal counter: std_logic_vector(0 to 7);
signal en: std_logic;
begin
process(clk) is
begin
if rising_edge (clk) then
temp<= temp+'1';
end if;
end process;
process(temp(3)) is
begin
if rst='1' then counter<="00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter<= counter+31; en<='0';
elsif counter=0 then en<='0';
else en<='1';
counter<= counter-31;
end if;
end if;
end process;
dac_out<= counter;

4.DAC

NET "CLK" LOC="p18";


NET "dac_out<0>" LOC="p27";
NET "dac_out<1>" LOC="p26";
NET "dac_out<2>" LOC="p22";
NET "dac_out<3>" LOC="p23";
NET "dac_out<4>" LOC="p21";
NET "dac_out<5>" LOC="p19";
NET "dac_out<6>" LOC="p20";
NET "dac_out<7>" LOC="p4";
NET "rst" LOC="p74";

end Behavioral;
PROCEDURE:
1) Make connection between FRC 5 and FPGA and DAC connector of VTU card 2.
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTU
card 2.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
4) Make the reset switch on.
RESULT:The waveform obtained Ramp, Saw tooth, Triangular, Sine and Square waves are
as per the graph.

4. WRITE A HDL CODE TO DISPLAY MESSAGES ON THE GIVEN


SEVEN SEGMENT DISPLAY
VHDL CODE
library IEEE;
HDL MANUAL

56

EC Dept, RNSIT

HDL LAB
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

IVth Sem EC
5. KEY BOARD TO 7 SEGMENT DISPLAY

entity sevkeybrd is
Port ( read : in std_logic_vector(3 downto 0);
clk : in std_logic;
scan : inout std_logic_vector(3 downto 0);
disp_cnt : out std_logic_vector(3 downto 0);
disp1 : out std_logic_vector(6 downto 0));
end sevkeybrd;
architecture Behavioral of sevkeybrd is
signal cnt_2bit:std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk='1' and clk'event then
cnt_2bit<= cnt_2bit+1;
end if;
end process;
process(cnt_2bit)
begin
case cnt_2bit is
when "00" => scan<= "0001";
when "01"=> scan<="0010";
when "10"=>scan<="0100";
when "11"=>scan<="1000";
when others=> null;
end case;
end process;
disp_cnt<="1110";
process(scan,read)
begin
case scan is
when "0001"=>case read is
when "0001"=>disp1<="1111110";
when "0010"=>disp1<="0110011";
when "0100"=>disp1<="1111111";
when "1000"=>disp1<="1001110";
when others =>disp1<="0000000";
end case;
when "0010"=> case read is
when "0001"=>disp1<="0110000";
when "0010"=>disp1<="1011011";
when "0100"=>disp1<="1111011";
when "1000"=>disp1<="0111101";
when others=>disp1<="0000000";
end case;
HDL MANUAL

57

NET "CLK" LOC="p18";


NET "disp_cnt<0>" LOC="p30";
NET "disp_cnt<1>" LOC="p29";
NET "disp_cnt<2>" LOC="p31";
NET "disp_cnt<3>" LOC="p38";
NET "disp<0>" LOC="p26";
NET "disp<1>" LOC="p22";
NET "disp<2>" LOC="p23";
NET "disp<3>" LOC="p21";
NET "disp<4>" LOC="p19";
NET "disp<5>" LOC="p20";
NET "disp<6>" LOC="p4";
NET "read_l_in<0>" LOC="122";
NET "read_l_in<1>" LOC="124";
NET "read_l_in<2>" LOC="129";
NET "read_l_in<3>" LOC="126";
NET "scan_l<0>" LOC="132";
NET "scan_l<1>" LOC="136";
NET "scan_l<2>" LOC="134";
NET "scan_l<3>" LOC="139";

EC Dept, RNSIT

HDL LAB

IVth Sem EC

when "0100"=> case read is


when "0001"=>disp1<="1101101";
when "0010"=>disp1<="1011111";
when "0100"=>disp1<="1110111";
when "1000"=>disp1<="1001111";
when others=>disp1<="0000000";
end case;
when "1000"=> case read is
when "0001"=>disp1<="1111001";
when "0010"=>disp1<="1110000";
when "0100"=>disp1<="0011111";
when "1000"=>disp1<="1000111";
when others=>disp1<="0000000";
end case;
when others=> null;
end case;
end process;
end Behavioral;
PROCEDURE:
1) Make connection between FRC 5 and FPGA board to the seven segment connector of
VTU card 1.
2) Make the connection between FRC 4 to FPGA board to K/B connector of VTU card1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Change the pressing of Hex Keys to watch the display on LCDs ranging from 0000 to
FFFF.
RESULT:The values from 0 to F were displayed on all 4 LCDs with the respective Hex Key
being pressed.

I/O Pin Assignments


FOR DC
MOTOR

Xilinx FPGA
FRC

1
2
3
4
5
6
7
8
9
10

FRC1
74
75
76
78
77
80
79
83
VCC
GND

FRC2
84
85
86
87
93
94
95
100
VCC
GND

HDL MANUAL

FRC3
112
114
113
115
117
118
121
123
VCC
GND

FRC4
122
124
129
126
132
136
134
139
VCC
GND

FRC6
40
41
42
48
50
51
56
57
VCC
GND

FRC7
58
60
63
64
65
66
67
28
VCC
GND

58

&

Stepper

Xilinx FPGA

FRC
1
2
3
4
9
10

FRC9
7
5
3
141
5V
GND

EC Dept, RNSIT

HDL LAB

IVth Sem EC

FRC
1
2
3
4
5
6
7
8
9
10
11
12
13

FRC5
4
20
19
21
23
22
26
27
30
29
31
38
5V

FRC8
96
99
101
102
103
116
120
131
133
137
138
140
5V

FOR ADC
FRC10
62
59
49
47
46
4
43
13
12
11
10
6
5V

14
15
16

-5v
3.3
GND

-5v
3.3
GND

-5v
3.3
GND

FOR LCD & DAC

Constrints file
1. External Light Controller
NET "cntrl" LOC="p74"; => FRC1
NET "light" LOC="p7"; => FRC9
2. DC MOTOR

NET "CLK" LOC="p18";


NET "RESET" LOC="p74";
NET "dir" LOC="p75";
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141";
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";

FRC1

FRC9

FRC7

3. STEPPER MOTOR

NET "CLK" LOC="p18";


NET "dout<0>" LOC="p7";
NET "dout<1>" LOC="p5";
NET "dout<2>" LOC="p3";
NET "dout<3>" LOC="p141";
NET "RESET" LOC="p74";
NET "dir" LOC="p75";

FRC9

FRC1

4.DAC

HDL MANUAL

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EC Dept, RNSIT

HDL LAB
NET "CLK" LOC="p18";
NET "dac_out<0>" LOC="p27";
NET "dac_out<1>" LOC="p26";
NET "dac_out<2>" LOC="p22";
NET "dac_out<3>" LOC="p23";
NET "dac_out<4>" LOC="p21";
NET "dac_out<5>" LOC="p19";
NET "dac_out<6>" LOC="p20";
NET "dac_out<7>" LOC="p4";
NET "rst" LOC="p74";

IVth Sem EC

FRC5

FRC1

5. KEY BOARD TO 7 SEGMENT DISPLAY

NET "CLK" LOC="p18";


NET "disp_cnt<0>" LOC="p30";
NET "disp_cnt<1>" LOC="p29";
NET "disp_cnt<2>" LOC="p31";
NET "disp_cnt<3>" LOC="p38";
NET "disp<0>" LOC="p26";
NET "disp<1>" LOC="p22";
NET "disp<2>" LOC="p23";
NET "disp<3>" LOC="p21";
NET "disp<4>" LOC="p19";
NET "disp<5>" LOC="p20";
NET "disp<6>" LOC="p4";
NET "read_l_in<0>" LOC="122";
NET "read_l_in<1>" LOC="124";
NET "read_l_in<2>" LOC="129";
NET "read_l_in<3>" LOC="126";
NET "scan_l<0>" LOC="132";
NET "scan_l<1>" LOC="136";
NET "scan_l<2>" LOC="134";
NET "scan_l<3>" LOC="139";

FRC5

FRC4

Procedure to download the program on to FPGA


Create new source
Implementation constraints file
User constraints
Create Timing constraints: Give the input and output ports from the port number
look up table(pin assignment) and then save.
Edit constraints to check the specified ports
Click on the source file
Implement design
HDL MANUAL

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EC Dept, RNSIT

HDL LAB

IVth Sem EC
Configure device (impact)after switching on power supply

Select the slave serial mode


Select the source file
Right click on xilinx and select program

Connect input port to dip switch and output port to leds.


Vary the inputs and view the corresponding outputs.

SL.
NO.
4.2.0
4.2.1

Infrastructure

Requirement
AICTE/University
Norms

Actually
provided

10

12

20000/
240000

1-02-05

04

06

40000/
240000

1-02-05

01

01

20000/
20000

1-02-05

Cost/

Year of
purchase

Amount

VHDL LAB
Multi-Vendor Universal Demo
Board(kit includes
motherboard along
with downloading
Cables)

Power supply, Xilinx FPGA-100k


gate density Xilinx CPLD.
Interfacing cards VTU interface-1
& VTU interface-2
along with above motherboards to
perform all experiments of VHDL
lab as per revised VTU syllabus
4.2.2

CM 640 Chipmax

Pattern generator cum Logic


Analyzer-64 channel
4.2.3

Chipscope Pro-logic

Analyzer from AGILENT


Technologies for on-chip
HDL MANUAL

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debugging and real-time analysis
of Xilinx
FPGAs
4.2.4 SiMS-VLSI Universal VLSI
Trainer/Evaluation Kit
J Tag Cable 1No
Power Supply 1No
Operation Manual 1No
4.2.5 SiMS PLD (Spartan-II, CPLD
cool runner, SPROM)(3 Nos)
4.2.6 SiMS-GPIO General purpose
Integrated Interface module
4.2.7 Foundation Express: XILINX
6.1i Version: ISE
Inclusive of all taxes

SL.
NO.
4.2.0
4.2.1

Infrastructure

IVth Sem EC

02

02

38,270.40

19-07-04

1 set each

1 set each

9,954.00

19-07-04

01

01

4,725.00

19-07-04

01

01

42,000.00
Grand Total:

5,44,949.40

Requirement
AICTE/University
Norms

Actually
provided

10

12

20000/
240000

1-02-05

04

06

40000/
240000

1-02-05

Cost/

Year of
purchase

Amount

VHDL LAB
Multi-Vendor Universal Demo
Board(kit includes
motherboard along
with downloading
Cables)

Power supply, Xilinx FPGA-100k


gate density Xilinx CPLD.
Interfacing cards VTU interface-1
& VTU interface-2
along with above motherboards to
perform all experiments of VHDL
lab as per revised VTU syllabus
4.2.2

CM 640 Chipmax

Pattern generator cum Logic


Analyzer-64 channel
HDL MANUAL

62

EC Dept, RNSIT

HDL LAB
4.2.3

01

Chipscope Pro-logic

Analyzer from AGILENT


Technologies for on-chip
debugging and real-time analysis
of Xilinx
FPGAs
4.2.4 SiMS-VLSI Universal VLSI
Trainer/Evaluation Kit
J Tag Cable 1No
Power Supply 1No
Operation Manual 1No
4.2.5 SiMS PLD (Spartan-II, CPLD
cool runner, SPROM)(3 Nos)
4.2.6 SiMS-GPIO General purpose
Integrated Interface module
4.2.7 Foundation Express: XILINX
6.1i Version: ISE
Inclusive of all taxes

IVth Sem EC
01
20000/
20000

02

02

38,270.40

19-07-04

1 set each

1 set each

9,954.00

19-07-04

01

01

4,725.00

19-07-04

01

01

42,000.00
Grand Total:

entity bcd is
Port ( clr,clk,dir : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0);
tc : out STD_LOGIC);
end bcd;
architecture Behavioral of bcd is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0);
begin
if(clr='1')then
temp:="0000";tc<='0';
elsif rising_edge(clkd(21)) then
if (dir='1') then
temp:=temp+1;
elsif(dir='0') then
temp:=temp-1;
end if;
if(dir='1' and temp="1010") then
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HDL LAB
temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then
temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;

IVth Sem EC

end Behavioral;
entity bin_as is
Port ( dir,clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end bin_as;
architecture Behavioral of bin_as is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd)
variable temp:std_logic_vector(3 downto 0):="0010";
begin
if rising_edge(clkd(21)) then
if (clr='0') then
if (dir='1') then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;
end Behavioral;
entity binary is
Port ( dir,clk,clr : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
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end binary;

IVth Sem EC

architecture Behavioral of binary is


signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0):="0010";
begin
if (clr='0') then
if rising_edge(clkd(21)) then
if dir='1' then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;

end Behavioral;
entity gray is
Port ( clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end gray;
architecture Behavioral of gray is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clr,clkd)
variable temp:std_logic_vector(2 downto 0);
begin
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if(clr='0') then
if rising_edge(clkd(21)) then
case temp is
when "000"=> temp:="001";
when "001"=> temp:="011";
when "011"=> temp:="010";
when "010"=> temp:="110";
when "110"=> temp:="111";
when "111"=> temp:="101";
when "101"=> temp:="100";
when "100"=> temp:="000";
when others => null;
end case;
end if;
else temp:="000";
end if;
q<=temp;
end process;

IVth Sem EC

end Behavioral;
entity johnc is
Port ( clk,clr : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end johnc;
architecture Behavioral of johnc is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
q<=(not q(0))& q(3 downto 1);
end if;
end process;

end Behavioral;
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entity ring is
Port ( clk,clr,l : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end ring;
architecture Behavioral of ring is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
if (l='1') then
q<="1000";
else
q<=q(0) & q(3 downto 1);
end if;
end if;
end process;

end Behavioral;
module alu1(a,b,s,en,y);
input [3:0] s,a,b;
input en;
output reg [7:0] y;
always@(a,b,s,en,y)
begin
if(en==1)
begin
case(s)
4'd0:y=a+b;
4'd1:y=a-b;
4'd2:y=a*b;
4'd3:y={4'd0,~a};
4'd4:y={4'd0,(a&b)};
4'd5:y={4'd0,(a|b)};
4'd6:y={4'd0,(a^b)};
4'd7:y={4'd0,~(a&b)};
4'd8:y={4'd0,~(a|b)};
4'd9:y={4'd0,(~a^b)};

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default:begin end
endcase
end
else
y=8'd0;
end
endmodule
module bcd(clr,clk,dir, tc, q);
input clr,clk,dir;
output reg tc;
output reg[3:0] q;
always@(posedge clk,posedge clr)
begin
if(clr==1)
q=4'd0;
else
begin
if (dir==1)
q=q+1;
else if(dir==0)
q=q-1;
if(dir==1 & q==4'd10)
begin
q=4'd0;tc=1'b1;
end
else if(dir==0 & q==4'd15)
begin
q=1'd9;tc=1'b1;
end
else tc=1'b0;
end
end
endmodule
module bin_as(clk,clr,dir, temp);
input clk,clr,dir;
output reg[3:0] temp;
always@(posedge clk,posedge clr)
begin
if(clr==0)
begin
if(dir==0)
temp=temp+1;
else temp=temp-1;
end
else
temp=4'd0;
end
endmodule
module binary(clk,clr,dir, temp);
input clk,clr,dir;
output reg[3:0]temp;
always@(posedge clk)
begin
if(clr==0)
begin
if(dir==0)

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temp=temp+1;
else temp=temp-1;
end
else
temp=4'd0;
end
endmodule
module gray(clr,clk, q);
input clr,clk;
output reg[2:0] q;
reg temp=3'd0;
always@(posedge clk,posedge clr)
begin
if(clr==0)
begin
case(temp)
3'd0:q=3'd1;
3'd1:q=3'd3;
3'd2:q=3'd6;
3'd3:q=3'd2;
3'd6:q=3'd7;
3'd7:q=3'd5;
3'd5:q=3'd4;
3'd4:q=3'd0;
endcase
end
else q=3'd0;
end
endmodule
module jhonson(clk,clr, q);
input clk,clr;
output reg[3:0] q;
always@(posedge clk,posedge clr)
begin
if(clr==1)
q=4'd0;
else
q={(~q[0]), q[3:1]};
end
endmodule
module ring(clk,clr,l, q);
input clk,clr,l;
output reg[3:0] q;
always@(posedge clk,posedge clr)
begin
if(clr==1)
q=4'd0;
else
begin
if (l==1)
q=4'd8;
else
q={q[0], q[3:1]};

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end
end
endmodule
entity bcd is
Port ( clr,clk,dir : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0);
tc : out STD_LOGIC);
end bcd;
architecture Behavioral of bcd is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0);
begin
if(clr='1')then
temp:="0000";tc<='0';
elsif rising_edge(clkd(21)) then
if (dir='1') then
temp:=temp+1;
elsif(dir='0') then
temp:=temp-1;
end if;
if(dir='1' and temp="1010") then
temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then
temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;
end Behavioral;
entity bin_as is
Port ( dir,clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end bin_as;
architecture Behavioral of bin_as is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd)

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variable temp:std_logic_vector(3 downto 0):="0010";


begin
if rising_edge(clkd(21)) then
if (clr='0') then
if (dir='1') then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;
end Behavioral;
ntity binary is
Port ( dir,clk,clr : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
end binary;
architecture Behavioral of binary is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0):="0010";
begin
if (clr='0') then
if rising_edge(clkd(21)) then
if dir='1' then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;

end Behavioral;
entity gray is
Port ( clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end gray;
architecture Behavioral of gray is
signal clkd:std_logic_vector(21 downto 0);

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begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clr,clkd)
variable temp:std_logic_vector(2 downto 0);
begin
if(clr='0') then
if rising_edge(clkd(21)) then
case temp is
when "000"=> temp:="001";
when "001"=> temp:="011";
when "011"=> temp:="010";
when "010"=> temp:="110";
when "110"=> temp:="111";
when "111"=> temp:="101";
when "101"=> temp:="100";
when "100"=> temp:="000";
when others => null;
end case;
end if;
else temp:="000";
end if;
q<=temp;
end process;
end Behavioral;
entity johnc is
Port ( clk,clr : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end johnc;
architecture Behavioral of johnc is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
q<=(not q(0))& q(3 downto 1);
end if;
end process;

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end Behavioral;
entity ring is
Port ( clk,clr,l : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end ring;
architecture Behavioral of ring is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
if (l='1') then
q<="1000";
else
q<=q(0) & q(3 downto 1);
end if;
end if;
end process;

end Behavioral;
FLIP FLOPS
entity dff is
Port ( d,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process (clk)
variable temp: std_logic;
begin
if rising_edge(clk) then
temp:=d;
end if;
q<=temp;qb<=not temp;
end process;

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end Behavioral;
entity jkff is
Port ( j,k,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;

process(clk,rst)
variable jk:std_logic_vector(1 downto 0);
variable temp:std_logic:='0';
begin
jk:=j&k;
if (rst ='0')then
if rising_edge(clk) then
case jk is
when "01"=> temp:='0';
when "10"=> temp:='1';
when "11"=> temp:=not temp;
when others=> null;
end case;
end if;
else temp:='0';
end if;
q<=temp;
qb<=not temp;
end process;
end Behavioral;
entity srff is
Port ( s,r,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end srff;
architecture Behavioral of srff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clk,rst)

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variable sr:std_logic_vector(1 downto 0);


variable temp1,temp2:std_logic:='0';
begin
sr:=s&r;
if (rst ='0')then
if rising_edge(clk) then
case sr is
when "01"=> temp1:='0'; temp2:='1';
when "10"=> temp1:='1'; temp2:='0';
when "11"=> temp1:='1'; temp2:='1';
when others=> null;
end case;
end if;
else temp1:='0'; temp2:='1';
end if;
q<=temp1;qb<=temp2;
end process;
end Behavioral;
entity tff is
Port ( t,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end tff;
architecture Behavioral of tff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process (clk)
variable temp:std_logic:='0';
begin
if rising_edge(clk) then
if (t='1') then
temp:=not temp;
else
temp:=temp;
end if;
end if;
q<=temp;qb<=not temp;
end process;
end Behavioral;
VERILOG FP
module dff(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0)

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temp=d;
else
temp=temp;
q=temp;
qb=~ temp ;
end
endmodule
module jkff(j,k,clk,rst, q,qb);
input j,k,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]jk;
always@(posedge clk,posedge rst)
begin
jk={j,k};
if(rst==0)
begin
case (jk)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=~q;
default: begin end
endcase
end
else
q=1'b0;
qb=~q;
end
endmodule
module srff(s,r,clk,rst, q,qb);
input s,r,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]sr;
always@(posedge clk,posedge rst)
begin
sr={s,r};
if(rst==0)
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else
begin
q=1'b0;
end
qb=~q;
end
endmodule
module tff(t,clk,rst, q,qb);

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input t,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0) begin
if(t==1) begin
temp=~ temp;
end
else
temp=temp;
end
q=temp;qb=~temp;
end
endmodule
module alu1(a,b,s,en,y);
input [3:0] s,a,b;
input en;
output reg [7:0] y;
always@(a,b,s,en,y)
begin
if(en==1)
begin
case(s)
4'd0:y=a+b;
4'd1:y=a-b;
4'd2:y=a*b;
4'd3:y={4'd0,~a};
4'd4:y={4'd0,(a&b)};
4'd5:y={4'd0,(a|b)};
4'd6:y={4'd0,(a^b)};
4'd7:y={4'd0,~(a&b)};
4'd8:y={4'd0,~(a|b)};
4'd9:y={4'd0,(~a^b)};
default:begin end
endcase
end
else
y=8'd0;
end
endmodule

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