Beruflich Dokumente
Kultur Dokumente
and Arbitration
Did you vote for Bush or Gore?
Didnt have enough time to decide.
Well, which hole did you punch?
Both, but not very hard...
WARD &
HALSTEAD
6.004
NERD KIT
3/04/03
L08 - Synchronization 1
Digital Values:
Digital Time:
Problem: Which transition
happened first? questions
Solution: Dynamic Discipline:
avoid asking such questions
in close races
tS
VOUT
VOH
VIH
VIL
Clk
VOL
VOL VIL
VIH VOH
VIN
tH
3/04/03
tCD
tPD
L08 - Synchronization 2
DQ
In
Combinational
logic
DQ
Combinational
logic
DQ
Out
Combinational
logic
DQ
Out
Clk
Combinational
logic
DQ
Combinational
logic
DQ
Combinational
logic
DQ
Out
3/04/03
L08 - Synchronization 3
But what
About the
Dynamic
Discipline?
0
1
B0
B1
Lock
U(t)
(Unsynchronized)
Synchronizer
S(t)
(Synchronized)
Which edge
Came FIRST?
Clock
6.004 Spring 2003
3/04/03
L08 - Synchronization 4
at t B
at t C
Arbiter specifications:
finite tD (decision time)
finite tE (allowable error)
value of S at time tC+tD:
1 if tB < tC tE
0 if tB > tC + tE
0, 1 otherwise
Arbiter
B:
>t E
C:
tD
S:
CASE 1
3/04/03
For NO finite
value of tE and tD
is this spec
realizable, even
with reliable
components!
>t E
tD
CASE 2
tD
CASE 3
L08 - Synchronization 5
at t B
at t C
Arbiter
With
Withno
noforbidden
forbiddenzone,
zone,all
allinputs
inputshave
haveto
to
be
bemapped
mappedto
toaavalid
validoutput.
output. As
Asthe
theinput
input
approaches
discontinuities
in
the
mapping,
approaches discontinuities in the mapping,
itittakes
takeslonger
longerto
todetermine
determinethe
theanswer.
answer.
Given
a
particular
time
bound,
you
Given a particular time bound, youcan
canfind
find
an
aninput
inputthat
thatwont
wontbe
bemapped
mappedto
toaavalid
valid
output
outputwithin
withinthe
theallotted
allottedtime.
time.
o
B
Earlier
6.004 Spring 2003
(t B=t C)
C
Earlier
3/04/03
t B-t C
L08 - Synchronization 6
Unsolvable?
that cant be true...
DECISION TIME is TPD of flop.
at t B
at t C
master
slave
3/04/03
L08 - Synchronization 7
0
1
Vout
Q
Y
Vout
2. Vin = Vout
Latched in
a 1 state
Latched in
an undefined
state
VTC of
inverter pair
VTC of feedback
path (Vin=Vout)
Latched in
a 0 state
Vin
3/04/03
L08 - Synchronization 8
3/04/03
Observed Behavior:
typical metastable symptoms
Following a clock edge on an asynchronous input:
CLK
D
We may see exponentially-distributed metastable intervals:
Q
Or periods of high-frequency oscillation (if the feedback path is long):
3/04/03
L08 - Synchronization 10
Mechanical Metastability
If we launch a ball up a hill
we expect one of 3
possible outcomes:
State A
a) Goes over
b) Rolls back
c) Stalls at the apex
Metastable State
State A
State B
L08 - Synchronization 11
Vout
Vout
Vin
Vin
3/04/03
Our active devices always have a fixed-point voltage, VM, such that
VIN=VM implies VOUT = VM
3/04/03
L08 - Synchronization 13
Sketch of analysis I.
Assume asynchronous 0->1
at TA, clock period CP:
A
Synchronizer
S(t)
(Synchronized)
C
Clock
V0
VM
t A-t C
< tS+tH
P[ V 0 VM ]
CP
6.004 Spring 2003
3/04/03
CP
2
(tS + tH ) (VH VL )
L08 - Synchronization 14
Vin
Vout
1
C
3/04/03
VH
Slope = A
Vin
VL
Vout(t)- VM e t(A-1)/RC
e t/
K e -T/
L08 - Synchronization 15
3x10-16
1 year
33.2 ns
3x10-17
10 years
100 ns
10-45
1030 years!
[For comparision:
Age of oldest hominid fossil: 5x106 years
Age of earth: 5x109 years]
3/04/03
L08 - Synchronization 16
Reconciliation: 80s-90s
L08 - Synchronization 17
Ancient Metastability
Metastability is the occurrence of a persistent invalid
output an unstable equilibria.
The idea of Metastability is not new:
I Shoulda
Taken 6.004!
3/04/03
L08 - Synchronization 18
Folk Cures
the perpetual motion machine of digital logic
Bad Idea # 1: Detect metastable state & Fix
Async
Input
FF
"FIXER"
"Clean"
Output
delay
Bad Idea #2: Define the problem away by making metastable point a valid output
valid
"0"
valid
"1"
3/04/03
L08 - Synchronization 19
"Metastable States":
Inescapable consequence of bistable systems
Eventually a metastable state will resolve itself to valid binary
level.
However, the recovery time is UNBOUNDED ... but influenced by
parameters (gain, noise, etc)
Probability of a metastable state falls off EXPONENTIALLY with
time -- modest delay after state change can make it very
unlikely.
Our STRATEGY; since we cant eliminate metastability, we will do
the best we can to keep it from contaminating our designs
6.004 Spring 2003
3/04/03
L08 - Synchronization 20
Modern Reconciliation:
delay buys reliability
A metastable state here
will probably resolve itself
to a valid level before it
gets into my circuit.
In
DQ
DQ
Combinational
logic
DQ
Out
Clk
In
DQ
DQ
DQ
Combinational
logic
DQ
Out
Clk
3/04/03
L08 - Synchronization 21
Arbiter
2. Bounded-time Synchronizer:
Asynchronous
Input
> 3.14159 ?
3/04/03
0 or 1,
finite tpd
L08 - Synchronization 22
Arbiter Done
0 or 1
> 3.14159 ?
Done
3/04/03
L08 - Synchronization 23
Data1
CKL2
CKL1
Mesochronous communication:
Data1
CLK2
Data2
delay
CLK1
CLK2
6.004 Spring 2003
3/04/03
L08 - Synchronization 24
Every-day Metastability - I
Ben Bitdiddle tries the
famous 6.004 defense:
Ben leaves the Bit Bucket
Caf and approaches fork in
the road. He hits the barrier
in the middle of the fork, later
explaining I cant be expected
to decide which fork to take in
bounded time!.
Bit
Bucket
Cafe
3/04/03
L08 - Synchronization 25
Every-day Metastability - II
GIVEN:
ST
P
O
PLAUSIBLE STRATEGIES:
A. Move at 55. At calculated distance D from light, sample color (using an
unbounded-time synchronizer). GO ONLY WHEN stable GREEN.
B. Stop 1 foot before intersection. On GREEN, gun it.
6.004 Spring 2003
3/04/03
L08 - Synchronization 26
Summary
The most difficult decisions
are those that matter the least.
As a system designer
Avoid the problem altogether, where possible
Use single clock, obey dynamic discipline
Avoid state. Combinational logic has no metastable
states!
Sometimes,
I just like
to sit in
my maze
motionless-for a very
long time.
3/04/03
L08 - Synchronization 27