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Universiti

J Malaysia
PAHANG

nineeiing . TechnoIoy Creativity

FACULTY OF MANUFACTURING ENGINEERING

FINAL EXAMINATION
COURSE

DIGITAL ELECTRONICS

COURSE CODE

BFM2313

LECTURER

: PROF IR DR AHMAD FAIZAL MOHD

ZAIN

DATE

16 JANUARY 2013

DURATION

3 HOURS

SESSION/SEMESTER :

SESSION 2012/2013 SEMESTER I

PROGRAMME CODE :

BFM

INSTRUCTIONS TO CANDIDATE:

1. Answer ALL questions.

2. All answers to a new question should start on new page.
3. All the calculations and assumptions must be clearly stated.

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of FOUR (4) printed pages including front page.

CONFIDENTIAL

BFM/121311BFM2313

ANSWER ALL QUESTIONS

QUESTION 1 (25 MARKS)

An engine has 4 fail-safe sensors. The engine should keep running unless any of the
following conditions arise:
If sensor 2 is activated.
If sensor 1 and sensor 3 are activated at the same time.
If sensor 2 and sensor 3 are activated at the same time.
If sensors 1,3,4 are activated at the same time.

(a) Derive the truth table for this system.

[4 marks]
(b) Design, using Karnaugh Map techniques, a minimum AND-OR gate network for this
system. Draw the resulting digital circuit diagram.
[8 marks]
(c) Design, a digital circuit that will implement the minimal AND-OR gate network found in
question (b) using both
i.
ii.

NAND gates only and

NOR gates only

Assume that each logic gate can have any number of inputs and that inverted inputs are
available.
[6 marks]
(d) If the time delay experienced by a NAND gate is 1 Ons and the time delay experienced in a
NOR gate is 8ns. Which implementation of (c) is faster? By how long?
[3 marks]
(e) Prove the rule of Boolean algebra: (A + B)(A + C) A + BC
[4 marks]

CONFIDENTIAL

BFMJ1213I/BFM2313

QUESTION 2 (25 MARKS)

a) Explain the operation of an exclusive OR gate. Draw the symbol. Calculate the truth
table for its operation.
[4 marks]
b) Give 2 ways of expressing an exclusive OR gate using AND, OR and NOT gates.
Draw the two expressions as circuits that are equivalent for implementing this
operation using AND, OR and NOT gates.
[8 marks]
c) Explain the operation of NAND and NOR gates using figures and truth-tables. Why
are these gates important in digital electronics? Explain and prove De Morgan's
Theorem.
[13 marks]
QUESTION 3 (25 MARKS)
a) Describe clearly the operation a shift register. An 8-bit shift register has a 80 MHz clock.
What is the total delay through the register?
[5 marks]
b) Show with general block diagrams how to achieve each of the following, using a flip-flop, a
decade counter, and a 4-bit binary counter, or any combination of these:
Divide-by-20 counter
(i)
Divide-by-32 counter
(ii)
(iii) Divide-by- 160 counter
Divide-by-320 counter
(iv)
[10 marks]
c) Implement the decoding of a binary state 2 and binary state 7 of a 3-bit synchronous counter.
Show the entire counter timing diagram and the output waveforms of the decoding gates.
Binary 2 = Q3 QQ and binary 7 = QQjQ0.
[10 marks]

CONFIDENTIAL

BFM/121311BFM2313

QUESTION 4 (25 MARKS)

(a) Figure 1 shows the basic circuit for an S-R latch. Explain its operation with the aid of a
truth table. 'What is its limitation?

R
Figure 1: S-R Latch

[5 marks]

(b) From the basic S-R circuit in part (a) above, show how a J-K flip-flop can be formed to
overcome the limitations by modifying the basic S-R circuit to convert into a JK flip-flop
with asynchronous set and reset inputs. Describe your answer with circuit diagrams, truth
table and timing diagrams where necessary.
[10 marks]

(c) How can a JK flip-flop be used as a 1-bit memory storage device? Use this configuration
to build a 4-bit parallel data storage device.

[10 marks]

END OF EXAMINATION PAPER

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