IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.

10, OCTOBER 2010

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Space-Vector Modulated Multilevel Matrix Converter

Meng Yeong Lee, Patrick Wheeler, and Christian Klumpner

AbstractA matrix converter is an acac power converter

topology that has received extensive research attention as an
alternative to traditional acdcac converter. A matrix converter
is able to convert energy from an ac source to an ac load without
the need of a bulky and limited-lifetime energy-storage elements.
The indirect three-level sparse matrix converter (I3SMC) is a new
topology from this family that can synthesize three-level voltage in
order to improve the output performance in terms of reduced harmonic content. This paper discusses the operating principles and a
space-vector-modulation scheme for this topology. Simulation and
experimental results are shown to prove the ability of this topology
to generate multilevel output voltages as well as to maintain a
set of sinusoidal balanced input currents. The performance of the
converter is compared with the conventional matrix converter and
an alternative multilevel matrix-converter topology in order to
demonstrate the advantages and disadvantages of the I3SMC.
Index TermsMatrix converter, multilevel converter, neutralpoint-clamped and three-level converter.

I. I NTRODUCTION

MATRIX converter is a direct power-conversion topology that can convert energy from an ac source to an ac
load without the need for bulky and limited-lifetime energystorage elements in the dc link. Even though this topology has
some disadvantages, such as limited voltage transfer ratio (0.86)
and a high number of power semiconductor device requirements, the matrix converter has received extensive research
attention due to its significant advantages: adjustable input
power factor, regeneration capability, and high-quality inputcurrent waveforms.
Matrix-converter topologies can be divided into two types:
direct matrix converters (MCs) and indirect matrix converters (2MCs). Fig. 1(a) shows a conventional direct matrix
converter, which has nine bidirectional switches. The typical bidirectional-switch configurations used in this converter
are shown in Fig. 1(b). The 2MC comprises a four-quadrant
current-source rectifier connected to a two-level voltage-source
inverter (VSI) [Fig. 1(c)]. By applying appropriate modulation
scheme [1][5], [17], [18], the direct converter and 2MC are
able to generate input and output waveforms with the same
quality.
However, in some applications, the 2MC may be preferred
to the direct matrix converter due to simpler and safer commutation of switches [6], the possibility of further reducing the
required number of the power semiconductor switches [7], and
Manuscript received August 17, 2009; revised November 5, 2009; accepted
November 26, 2009. Date of publication January 8, 2010; date of current
version September 10, 2010.
The authors are with the Department of Electrical and Electronic Engineering, University of Nottingham, Nottingham, NG72RD, U.K.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2038940

Fig. 1. Matrix-converter topologies. (a) Direct matrix converter. (b) Typical

bidirectional switches. (c) 2MC.

the possibility of constructing a direct converter topology with

multiple input and output ports [8].
The multilevel matrix converter is a new topology from
this family that incorporates the multilevel converter concept
with a matrix converter. There are several types of multilevel
matrix-converter topologies that have been proposed [9][11].
Having the ability to generate multilevel output voltages, the
multilevel matrix converter is able to generate better quality
output waveforms in terms of harmonic content, but at the cost
of a more complicated circuit configuration and modulation
strategy.
In [12], a three-level matrix-converter topology with reduced
number of switches has been proposed: indirect three-level
sparse matrix converter (I3SMC). This topology is a combination of a three-level neutral-point-clamped VSI [12], [13] and
a 2MC. Having two additional insulated-gate bipolar transistor
switches connected as an additional inverter stage leg (neutralpoint commutator) in the dc link, as shown in Fig. 2, the outputvoltage capability of I3SMC can be enhanced from two to three
levels in the line-to-supply neutral voltages.
This addition results in an improved performance in terms of
output-voltage harmonic contents. The additional voltage level
is obtained by connecting the middle point (o) of the neutralpoint commutator to the neutral-point of the star-connected
input filter capacitors.
This paper discusses the operating principles and a spacevector modulation (SVM) for the I3SMC. In Section II, a

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TABLE I
S WITCHING C OMBINATIONS OF THE B UCK S TAGE

Fig. 2. I3SMC.

Fig. 3. 3MC.
Fig. 5. Definition of triangles within the sector 1 of the space-vector diagram
of the three-level neutral-point-clamped VSI.

Fig. 4. Three-level neutral-point-clamped VSI.

modulation scheme applied to a three-level neutral-pointclamped VSI is explained in order to facilitate the explanation
of the SVM applied to the I3SMC in Section III. Simulation and
experimental results for the I3SMC are shown in Sections IV
and V to verify the ability of this topology to generate multilevel
output-voltage waveforms as well as sinusoidal input currents.
Finally, the performance of the I3SMC is compared with a
2MC and a three-level-output-stage matrix converter (3MC)
(Fig. 3) in order to show the advantages and disadvantages of
the proposed converter topology.
II. SVM F OR THE T HREE -L EVEL
N EUTRAL -P OINT-C LAMPED VSI
The modulation principles of a three-level neutral-pointclamped VSI shown in Fig. 4 have been comprehensively
explained in [12] and [13]. This section briefly explains an
SVM scheme for this converter as the foundation of an I3SMC

modulation strategy. As shown in Fig. 4, this converter comprises a three-level dual buck stage connected to a two-level
VSI stage. At any instant in time, the three-level dual buck
stage can supply two out of the three voltage levels available
at the dc link (p, n and o) to the two-level VSI terminals (p_inv
and n_inv) based on the switching combinations presented
in Table I. Each voltage level is represented by a switching
state: P = Vdc , O = 0, and N = Vdc . Therefore, each output
voltage, VXo (x {A, B, C}), of the two-level VSI has three
possibilities: Vdc , 0 V, and Vdc .
Fig. 5 shows sector 1 of the space-vector diagram for the
three-level neutral-point-clamped VSI. Three types of vectors
are defined based on the switching-state combinations formed
at the outputs: zero voltage vector (V0 ), small voltage vectors
(SVVs) (V1 and V3 ), and large voltage vectors (V2 and V4 ).
Each sector consists of seven triangles (T 1 T 7). To synthesize a reference output voltage vector Vout , three nearest
voltage vectors are selected based on the triangle in which Vout
is located. Table II presents the duty-cycle equation of each
selected vector for each triangle, where mU is the modulation
index of the converter and out is the angle of Vout within the
respective sector.
Similar to conventional multilevel neutral-point-clamped
converter, the connection of the output to the neutral-point
(o) of the three-level neutral-point-clamped VSI can cause
uneven charging/discharging of the dc-link capacitors due to the
neutral-point current. Without proper control, the uneven charging voltage levels of the dc-link capacitors would impact on
the ability of the converter to properly generate the three-level

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TABLE II
D UTY-C YCLE E QUATIONS FOR S ELECTED V ECTORS OF E ACH T RIANGLE

output waveform, causing output-voltage distortion. To maintain the dc-link capacitor voltages, the average neutral-point
current over a switching period must be maintained at zero [14].
For this three-level neutral-point-clamped VSI, only SVVs
contribute neutral-point current. As discussed in [15], the redundant switching states of each SVV connect the same output phase current to the neutral-point but with opposite sign.
Therefore, in this SVM, both redundant switching states (e.g.,
POO/ONN) of selected SVV (e.g., V1 ) have to be equally applied within a switching period in order to balance the neutralpoint current so that a zero-average neutral-point current can be
obtained.
III. SVM FOR THE I3SMC
Comparing Fig. 2 with Fig. 4, the combination of the rectifier
and the neutral-point commutator obviously performs the same
function as the three-level dual buck stage. At any instant in
time, there are three voltage levels available at the dc link;
two are supplied by the rectifier (the positive voltage level
at p and the negative voltage level at n) and one by the
neutral-point commutator (the zero voltage level at o). The
zero voltage level of this topology is the neutral-point voltage
of the star-connected input filter capacitors. By controlling
the rectifier and neutral-point commutator to supply only two
voltage levels to the two-level inversion stage at any instant, the
I3SMC is obviously able to generate three-level output voltages
in the same way as the three-level neutral-point-clamped VSI
discussed in Section II.
In [12] and [16] an SVM has been proposed to modulate
the I3SMC to generate the desired input currents and output
voltages. For each stage, SVM is used to produce a combination
of vectors to synthesize the reference vector. The input current
vector Iin is the reference vector for the rectification stage,
while the output voltage vector Vout is the reference for the
inversion stage. After determining the vectors and duty cycles,
the switching pattern combines the switching states for the
rectification and inversion stages uniformly in order to obtain
the correct input currents and output voltages in each switching
period.
A. Rectification Stage
For the I3SMC, the rectifier is modulated using SVM to
generate maximum dc-link voltage and to maintain a set of
balanced sinusoidal input currents. As shown in Fig. 6, the

Fig. 6. Generation of the reference input current vector Iin at the rectification
stage.

space-vector diagram of the rectifier consists of six active current vectors with fixed directions and three zero current vectors,
which are defined based on the valid switching combinations
formed by the rectifier. Each current vector represents the
connection of input phase voltages to the dc-link terminals. For
example, vector I1 (ac) represents the connection of the positive
input phase voltage a to the p terminal and the negative input
phase voltage c to the n terminal.
To synthesize the reference vector Iin for the I3SMC, two
adjacent active current vectors I and I are selected. The
duty cycles of I and I are given by (1), where the rectifiers
modulation index mI is set to unity and in is the angle of Iin
within the respective sector, i.e.,


in
d = mI sin
(1)
d = mI sin(in ).
3
The calculated duty cycles are then adjusted, using (2), so
that they occupy the whole switching period. Over a switching
period, the average dc-link voltage generated by the rectifier
Vpn_avg is as given as
dR
=

d
d + d

dR
=

d
d + d

R
Vpn_avg = dR
Vll + d Vll .

(2)
(3)

For the I3SMC, the selected active current vectors define

the voltage levels available at the dc link. For example, if the
current vector I1 is applied, the voltage levels available at the
dc link are the following: P = Vao , O = the neutral point
voltage, and N = Vco . At any time, only two voltage levels can

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be supplied to the inversion stage. Therefore, the modulation

of the inversion stage determines how the rectifier and neutralpoint commutator supply the voltage levels to the inverter.
B. Inversion Stage
Due to the design similarity between the three-level neutralpoint-clamped VSI discussed in Section II and the I3SMC,
the SVM for the three-level neutral-point-clamped VSI can
be applied to the inversion stage of the I3SMC in order to
generate multilevel output voltages. The reference vector Vout
is synthesized using three nearest voltage vectors, and the duty
cycle of each selected vector is determined using the equations
shown in Table II, where the modulation index of the inversion
stage mU is given as

3 |Vout |
mU =
.
(4)
Vpn_avg
The rectifier and the neutral-point commutator are modulated
so that only two voltage levels are supplied to the inverters
terminals based on the selected voltage vector. For example,
when the current vector I1 (ac) is applied to the rectifier, the
following can be derived:
1) For output vector V1 (POO), the required voltage levels
are p_inv = P and n_inv = O. Hence, only the switches
that connect the input phase voltage a to p_inv and
the neutral-point voltage o to n_rminv are turned ON ,
while the others are OFF. The voltage applied across the
inverters terminals is Vp_invn_inv = Vao .
2) For vector V2 (PNN), the required voltage levels are
p_inv = P and n_inv = N . Only the switches that connect the input phase voltage a to p_inv and the input
phase voltage c to n_inv are ON , while the others are OFF.
Therefore, Vp_invn_inv = Vac .
Based on the switching pattern, the voltage Vp_invn_inv
is applied to the outputs to generate the output line-to-line
voltages for the I3SMC. By applying the input phase-to-neutral
voltages to the outputs at low modulation indexes, the generated
output voltage ripple is much lower than the voltage ripple
generated by the use of the input line-to-line voltages. Hence,
the output-waveform harmonic content is reduced, as will be
shown in Section V.
C. Switching Pattern for the I3SMC
The switching pattern shown in Fig. 7 clearly illustrates how
the voltage levels are supplied to the inverters terminals based
on the selected current and voltage vectors within a switching
period. Fig. 7 is based on an example where Iin is located in sector 2, and Vout is located in T 6 of sector 1. The current vectors
I1 (= I ) and I2 (= I ) are selected for the rectification stage,
while the voltage vectors V2 , V3 , and V4 are selected for the
inversion stage. The voltage vectors are arranged in a doublesided switching sequence: V3V4V2V3V3V2V4V3,
but with unequal halves because each half has to be applied
to each rectifier switching state: I1 and I2 . As shown in Fig. 7,
both redundant switching states (PPO/OON) of V3 are equally

Fig. 7.

Switching pattern of the I3SMC.

TABLE III
C IRCUIT S PECIFICATIONS

applied within the switching pattern. This arrangement ensures

that zero-average neutral-point current is obtained within a
switching period so that the voltage levels of the input filter
capacitors as well as the output performance of the converter
can be maintained, as discussed in Section II.
IV. S IMULATION R ESULTS
The I3SMC shown in Fig. 2 has been simulated using
SABER, based on the specifications shown in Table III. The
converter is implemented using ideal switches. The control
strategy uses the measured input phase voltages (referenced
to the neutral-point of the input filters) Vao , Vbo , and Vco , to
determine the reference angle of the input-current vector. This
is because, according to the modulation strategy, the input currents generated by the I3SMC are synchronized with the input
voltages. In addition, the magnitudes of the input phase voltages
are used to determine the average dc-link voltage supplied to the
inversion stage, as given in (3). In this simulation, the converter
is evaluated using an RL load. The desired reference output
voltage vector is provided for the control block of the inversion
stage to determine the duty cycles for the switches.
Fig. 8 shows the waveforms generated by the I3SMC as the
voltage transfer ratio is stepped from 0.4 to 0.8. The waveforms
shown in this figure consist of the dc-link voltage (Vpn ), the
potentials at the dc-link terminal referenced to the neutralpoint (Vpo and Vno ), the output terminal voltage (VAo ), the
output line-to-line voltage (VAB ), and the load currents (iA , iB ,
and iC ).
There are three voltage levels available at the dc links: Vpo ,
0 V, and Vno . However, at any instant, the inversion stage can
only be operated with two voltage levels. Therefore, depending
on the selected voltage vectors, the rectifier and neutral-point
commutator provide the required voltage levels to the inversion
stage. During the voltage-transfer-ratio transition, there is a
noticeable increase in the dc-link voltage Vpn , as shown in

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Fig. 9. Input waveforms for the I3SMC. (a) The voltage levels of the starconnected input filter capacitors. (b) The input-current waveforms.
TABLE IV
S WITCHING F REQUENCY, AVERAGE VOLTAGE S TRESS , AND C URRENT
R ATING FOR O NE S WITCH OF THE N EUTRAL -P OINT C OMMUTATOR

Fig. 8. Output waveforms generated by the I3SMC with the voltage transfer
ratio stepped from 0.4 to 0.8.

Fig. 8(a). This is because, to generate higher output voltages

at high modulation indexes, the rectifier and the neutral-point
commutator constantly connect the input line-to-line voltages
(e.g., Vab ) to the inversion stages terminals p_inv and n_inv
instead of the input line-to-neutral point voltages (e.g., Vao ),
which are mostly used at low modulation indexes. The switching in Vpo and Vno , shown in Fig. 8(b), shows the operation of
the rectifier and neutral-point commutator in order to control
the voltage levels supplied to the inversion stage.
The output terminal voltage, VAo , shown in Fig. 8(c), shows
that the I3SMC generates three distinctive voltage levels at the
output terminals. These levels are the positive and negative
envelopes of the rectified input voltages and the zero voltage
level. As shown in Fig. 8(d), a transition in the output line-toline voltage VAB from three to five levels shows that the I3SMC
is able to generate multilevel output voltages. To verify that
the voltage levels are properly applied to generate the desired

outputs, the load currents of the I3SMC are shown in Fig. 8(e).
These currents are balanced and sinusoidal.
Fig. 9 shows the voltage levels of the star-connected input
filter capacitors and the input-current waveforms. By applying
the redundant switching states of selected SVVs equally, a zeroaverage neutral-point current over a switching period can be
obtained. As shown in Fig. 9(a), the voltage levels of the input
filter capacitors remain balanced, proving that the modulation
strategy is able to balance the neutral-point current. Then, the
waveforms in Fig. 9(b) clearly show that the converter is able
to generate sinusoidal and balanced input-current waveforms,
even with the presence of neutral-point current.
Since the neutral-point commutator has to be constantly commutated to supply the required voltage levels to the inversion
stage, it is important to investigate the voltage stress, switching
frequency, and current rating for the switches of the neutralpoint commutator with respect to the load rating. Using the
specifications given in Table III, the converter is operated at
different voltage transfer ratios, and one switch of the neutralpoint commutator is measured to determine the average voltage
stress, switching frequency, and the average current stress,
which are shown in Table IV.
Due to the connection of middle point o to the neutral-point
of the input filter capacitors, the maximum voltage stresses
across the switches of the neutral-point commutator are limited
to the connected input phase voltages. As shown in Table IV,
when the voltage transfer ratio is increased from 0.2 to 0.8,
the average voltage stress across the switch is increased. On the
other hand, the per unit (with the average dc-link current as the
base unit) average current stress for the switch reduces. This

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Fig. 10. I3SMC prototype.

is due to the dominance of large voltage vectors in synthesizing

the reference vector when the voltage transfer ratio is increased,
increasing the OFF-state time of the switches for the neutralpoint commutator.

V. E XPERIMENTAL R ESULTS
To validate the simulation results, a prototype of the I3SMC,
shown in Fig. 10, was developed. Using a 120-V (rms) supply,
the converter was evaluated based on the specifications shown
in Table III, with different modulation indexes, using a balanced
RL load.
The voltage transfer ratio is stepped from 0.4 to 0.8, and
the waveforms from the prototype, shown in Fig. 11, clearly
correspond to the waveforms in Fig. 8. The increase in Vpn
during the voltage-transfer-ratio transition proves that the rectifier and the neutral-point commutator connect the input lineto-line voltages to the inversion stages terminals in order to
generate higher output voltages at high modulation indexes.
At low modulation indexes, only the input line-to-neutral point
voltages are used, so the magnitude of Vpn is limited to the peak
levels of the input phase voltages.
Referring to Fig. 11, the input and output current waveforms
of the prototype show proper converter operation. A transition
from three to five levels in the output line-to-line voltage VAB
during the voltage-transfer-ratio transition, verifies the ability of
the converter to generate multilevel output-voltage waveforms.
By constructing the output waveforms with multiple voltage
levels, the I3SMC is obviously able to generate higher quality
output waveforms than a 2MC with identical specifications.
To make an output performance comparison, the prototype
of the I3SMC was operated as an indirect matrix-converter
topology by disabling the gating signals to the neutral-point
commutator. At a high modulation index (Vout_peak = 135 V),
shown in Fig. 12, the I3SMC evidently generates five distinctive
voltage levels for the output line-to-line voltage VAB . By comparing the output waveforms for the two topologies, the outputwaveform harmonics for the I3SMC are obviously lower, as
shown in Fig. 12(b). Compared with the 2MC, the outputvoltage harmonics are reduced from 14.1 to 13.9 V (fsw ) and
38.1 to 25 V (2fsw ).

Fig. 11. Experimental waveforms generated by the I3SMC with the voltage
transfer ratio stepped from 0.4 to 0.8. (a) The dc-link voltage Vpn . (b) The
potentials at the dc-link terminals referenced to the neutral-point Vpo and Vno .
(c) The input voltage Vao and the input current ia . (d) The output line-to-line
voltage VAB and the output current iA .

At a low modulation index, (Vout_peak = 68 V), shown

in Fig. 13, the I3SMC is able to construct the low outputvoltage waveforms with smaller voltage levels. As shown in
Fig. 13(a), the magnitude of VAB for the I3SMC is limited to
the input phase-to-neutral voltages instead of the line-to-line
input voltages for the 2MC, shown in Fig. 13(c). As a result,
the output-voltage ripple is lower, and the harmonic content is
reduced. By comparing Fig. 13(b) with Fig. 13(d), the output
switching frequency harmonics for the I3SMC are significantly
lower, reduced from 8.5 to 5.6 V (fsw ) and from 40.5 to
12.1 V(2fsw ). Based on the results shown in Figs. 12 and 13,
the I3SMC evidently has a better output performance than the
2MC in terms of harmonic content of the output voltage.
In this paper, the output performance of the I3SMC is also
compared with the 3MC. Both multilevel matrix converters
integrate a three-level neutral-point-clamped converter concept
with an indirect matrix-converter topology. The only difference
is that the I3SMC has a simpler circuit configuration, while the
3MC is more complicated and is able to achieve the switching
states (medium voltage vectors) that are not achievable by the
I3SMC. A prototype of the 3MC has been developed and was
modulated using SVM [11] based on the same specifications
shown in Table III with Vin_rms = 120 V. As discussed in [11],
the modulation on the 3MC ensures that a zero-average neutralpoint current is obtained for every switching period in order to
maintain the voltage levels of the input filter capacitors as well
as the performance of the converter.

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Fig. 12. Output line-to-line voltages and output-voltage spectra (a)(b) the I3SMC and (c)(d) the 2MC at a high modulation index (V out_peak = 135 V).

Fig. 13. Output line-to-line voltages and output-voltage spectra; (a)(b) the I3SMC and (c)(d), the 2MC at a low modulation index (V out_peak = 68 V).

To compare the output waveform quality for both topologies,

the total harmonic distortion (THD) for the output line-toline voltage VAB are calculated, as shown in Fig. 14, where
the fundamental output frequency is 30 Hz and the number
of harmonics included in the THD calculation is 1000 (up to
30 kHz). In this figure, the THD for VAB of the 2MC is also
presented. The three-level matrix-converter topologies clearly
have a better output performance than the 2MC in terms of
the harmonic content in the output voltages. By having better
quality output-voltage waveforms, the distortion in the load
current will be lower, giving an advantage to the three-level
matrix converters in applications where the load provides low
filtering inductances.
Comparing the I3SMC to the 3MC, the THD for both multilevel matrix-converter topologies are obviously similar at low
voltage transfer ratios (< 0.5). This similarity is because the
modulations of the inversion stages for both topologies are
identical; only the SVVs and zero voltage vectors are used to
synthesize the reference output vector. However, at high voltage

Fig. 14. THD for the output line-to-line VAB of the I3SMC, the 3MC and
the 2MC.

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Fig. 15. Input-current waveforms of the I3SMC.

Fig. 16. Input-side comparison between the I3SMC and the 2MC at a low modulation index (V out_peak = 68 V) and a high modulation index (V out_peak =
135 V).

transfer ratios (> 0.5), the ability to achieve the medium voltage
vectors enables the 3MC to synthesize the reference output
vector with a better selection of the nearest three space vectors,
reducing the harmonic content in the output waveforms. Therefore, as shown in Fig. 14, the THD for the I3SMC is higher than
for the 3MC. The decrease in the difference between the THDs,
when the voltage transfer ratio approaches 0.8, is because the
large voltage vectors of both multilevel matrix converters get
more dominant in synthesizing the reference output vector. As
a result, the THDs for both multilevel topologies, as well as the
2MC, converge when the voltage transfer ratio reaches 0.8.
Based on Fig. 14, the 3MC appears superior to the I3SMC
and the 2MC. However, the complicated circuit configuration
of the 3MC is undoubtedly a disadvantage. On the other hand,
the I3SMC has a simpler circuit configuration than the 3MC
and is able to generate multilevel output voltages to improve
the output waveforms quality as compared with the 2MC. This
clearly gives an advantage to the I3SMC.
In addition, the inversion stage of the I3SMC has lower
switching losses at high modulation indexes. This advantage

is due to the fact that there is no switching in the inversion

stage for certain change of switching states in the switching pattern. For example, if the reference vector Vout is located in triangle T 4, the switching pattern for the inversion
stage is PPOPOOPNNONNOON. The switching states
POO, PNN, and ONN actually represent the same switching state (PNN) in the inversion stage. Therefore, no switching is required, reducing the power losses in the inversion
stage.
To evaluate the input-side performance of the I3SMC,
Figs. 15 and 16 show the input-current waveforms and spectra of the input current ia for the converter. For comparison
purposes, the spectra of ia for the 2MC are also shown in
Fig. 16. The waveforms in Fig. 15 clearly demonstrate that the
modulation strategy is able to modulate the I3SMC to generate
a set of sinusoidal balanced input currents despite the presence
of neutral-point current. However, in terms of input-current
quality, the 2MC is better than the I3SMC. As shown in Fig. 16,
the input-current harmonics for the I3SMC are relatively higher
than the 2MC, particularly the seventh-order harmonic content

LEE et al.: SPACE-VECTOR MODULATED MULTILEVEL MATRIX CONVERTER

at 350 Hz. This is proven by the THD for the input current of
each topology, shown in Fig. 16, where the fundamental input
frequency is 50 Hz and the number of harmonics included in
the THD calculation is 40 (up to 2 kHz).
For the I3SMC, the operation of the rectifier and neutralpoint commutator to supply the voltage levels required by the
inversion stage impacts on the ability of the rectifier to properly
generate sinusoidal input currents. Based on the modulation
on the rectifier, discussed in Section II, the input currents
are synthesized by distributing the impressed dc-link current
accordingly to the input phases. However, the use of zero
voltage vectors causes discontinuity in the dc-link current, and
the SVVs are generated by disconnecting the rectifier from one
of the dc link. This inevitably affects the rectifier to properly
generate sinusoidal input currents. Therefore, the input-current
distortions for the I3SMC are relatively higher than the 2MC,
which is clearly a disadvantage.
In addition, the OFF-state switches for the inversion stage
have to withstand high voltage stresses, which are proportional
to the connected input line-to-line voltage, at high modulation
indexes. In this case, the 3MC obviously has the advantage
because the connections of clamping diodes always limit the
voltage stresses across the OFF-state switches of the inversion
stage to half the dc-link voltages (proportional to input phase
voltages).
In addition, in order to supply the required voltage levels to
the inversion stage, the rectifier and neutral-point commutator
for the I3SMC have to be constantly commutated under hardswitching situations, where neither the dc-link current nor the
voltage across the devices are zero. Therefore, depending on
the direction of the dc-link current, there is a switching loss at
either the rectifier or the neutral-point commutator during every
commutation. In this case, the 2MC has the advantage because
the rectification stage for this converter can be commutated
under soft-switching situations, where the dc-link current is
zero due to the zero voltage vector produced by the inversion
stage.
VI. C ONCLUSION
In this paper, the operating principles and the SVM scheme
for a three-level neutral-point-clamped matrix converter have
been discussed. By applying the proposed modulation scheme,
the I3SMC is able to synthesize multilevel output voltages and
sinusoidal input currents. Simulation and experimental results
clearly show that the I3SMC is able to produce better output
performance, particularly at low modulation indexes, in terms
of output waveform harmonic content when compared with a
conventional matrix converter. Compared with the 3MC, the
simpler circuit configuration of the I3SMC clearly has the
advantage since both topologies equally have the ability to
generate multilevel output voltages, but the output waveforms
quality of the 3MC is relatively better at high voltage transfer
ratios. In this paper, the disadvantages of the I3SMC are also
discussed, where the input-current distortions for this converter
are higher than the conventional matrix converter, and the
commutations of the rectifier and neutral-point commutator
lead to additional switching losses.

3393

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Meng Yeong Lee was born in Selangor, Malaysia,

in 1979. He received the B.S. degree (honors) in
electronic engineering from the Multimedia University, Selangor, Malaysia, in 2002 and the M.Sc.
degree in electrical engineering from the University
of Nottingham, Nottingham, U.K., in 2003, where he
is currently working toward the Ph.D. degree.

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 10, OCTOBER 2010

Patrick Wheeler received the B.Eng. degree (honors) and the Ph.D. degree in electrical engineering for
his work on matrix converters from the University of
Bristol, Bristol, U.K., in 1990 and 1994, respectively.
He has been with the University of Nottingham,
Nottingham, U.K., where he was a Research Assistant in the Department of Electrical and Electronic
Engineering in 1993, became a Lecturer in the Power
Electronics, Machines and Control Group in 1996,
and has been a Full Professor with the same research
group since January 2008. He has published over 200
papers in leading international conferences and journals. His research interests
are in power conversion and More electric-aircraft technology.

Christian Klumpner was born in Resita, Romania,

in 1972. He received the B.Sc. degree in electromechanical engineering from the University of
Resita, Resita, Romania, in 1995, and the M.Sc.
and Ph.D. degrees in electrical engineering from the
Politehnica University of Timisoara, Timisoara,
Romania, in 1996 and 2001, respectively.
From 1996 to 1997, he was with Bee Speed,
Timisoara, Romania. Between 1998 and 2000, he
was a Guest Researcher with the Institute of Energy
Technology, Aalborg University, Aalborg, Denmark,
working on matrix converters under the auspices of the Danfoss Professor
Program. From 2001 to 2003, he was a Research Assistant Professor with the
Institute of Energy Technology, Aalborg University, continuing the research in
direct power conversion under the auspices of the Innovation Post-Doc Program
supported by the Danish Research Agency and Danfoss Drives A/S. Since
October 2003, he has been a Lecturer with the School of Electrical Engineering,
University of Nottingham, Nottingham, U.K. His research interests include
power electronics and ac drives, with special focus on direct power conversion.
Dr. Klumpner is the recipient of the Isao Takahashi Power Electronics Award
for outstanding achievements in power electronics at the International Power
Electronic Conference (IPEC2005) organized by the Institute of Electrical
Engineers of Japan, Niigata, Japan.