Research Paper

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2331687, IEEE Transactions on Power Electronics
IEEE Transactions on Power Electronics
1
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
Space-Vector versus Nearest-Level Pulse Width

Modulation for Multilevel Converters
Yi Deng, Student Member, IEEE, and Ronald G. Harley, Fellow, IEEE
AbstractThis paper studies the inherent relationship between

two widely used pulse width modulation (PWM) methods for
multilevel converters, i.e., the space vector modulation (SVM)
method, also called space vector pulse width modulation
(SVPWM), and the nearest-level modulation method. The
nearest-level modulation method directly controls the voltage of
each phase, while the SVM method simultaneously deals with all
phases. It is demonstrated in this paper that the two modulation
methods are functionally equivalent: with proper common-mode
voltage injections, the nearest-level modulation method is
equivalent to the SVM method; by selecting the appropriate
redundant switching sequences and the corresponding duty
cycles, the SVM method is equivalent to the nearest-level
modulation method. Nevertheless, the SVM method can
conveniently provide more flexibility of optimizing the switching
patterns, without the need of designing sophisticated commonmode voltages. An efficient and flexible modulation method for
any multiphase multilevel converter is therefore proposed, which
combines the advantages of the nearest-level modulation and the
SVM methods, i.e., both with less computational burden and high
flexibility of optimizing the output waveforms. Simulation and
experimental results validate the analysis.
Index TermsMultilevel converter, multiphase converter,
modular multilevel converter (MMC), nearest-level modulation,
pulse width modulation (PWM), space vector modulation (SVM),
space vector pulse width modulation (SVPWM).
I. INTRODUCTION
ULTILEVEL converters are widely adopted in high-power

applications due to their superior performance compared
to two-level converters, with advantages such as reduced
voltage stress on the power devices, lower harmonics, and
lower instantaneous rate of voltage change (dv/dt) [1]. Starting
with the three-level converter presented in [2], three basic
topologies have been proposed for multilevel converters
during the past decades: diode-clamped (neutral-clamped) [2][4], capacitor-clamped (flying capacitors) [5], and cascaded HThis work was supported in part by the U.S. National Science Foundation
under Grants EFRI #0836017 and ECCS #1232070. Any opinions, findings,
and conclusions or recommendations expressed in this work are those of the
authors and do not necessarily reflect the views of the National Science
Foundation.
Y. Deng is with the School of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA 30332, USA (e-mail:
ydeng35@gatech.edu).
R. G. Harley is with the School of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA 30332, USA and also a
Professor Emeritus in the School of Engineering, University of KwaZuluNatal, Durban, South Africa (e-mail: rharley@ece.gatech.edu).
bridge with separate dc sources [6]. Another emerging

topology called the modular multilevel converter (MMC) was
introduced in the early 2000s [7], which has attracted much
research interests recently, due to its significant merits such as
modularity and scalability to meet any voltage level
requirements [8]-[11].
Together with the evolution of the topologies, many pulse
width modulation (PWM) methods have been developed for
multilevel converters. Most of those modulation methods can
be classified into three typical categories: a) carrier-based
modulation, including phase-shifted PWM [12]-[16] and
phase-disposition PWM [17] [18]; b) space vector modulation
(SVM) [19]-[23]; and c) nearest-level modulation [24] [25],
also called submodule-unified modulation [26] or singlephase modulation [27]. Space vector modulation works with
line-to-line voltages (i.e., it simultaneously deals with all
phases), while the other two methods are phase-voltage
modulation techniques. Different from carrier-based
modulation methods, nearest-level modulation avoids the use
of any triangular carrier wave, by directly computing the
switching states and duty cycles for each phase of the
converter. This difference brings the significant advantage to
nearest-level modulation of more flexibility and easy digital
implementation, especially when the converter level number is
large. A nearest-level-control (NLC) modulation method has
also been reported for multilevel converters [28] [29]. As an
extension of the NLC, during each switching cycle nearestlevel modulation approximates the reference voltage by two
nearest voltage levels instead of one, which introduces the
PWM operation (i.e., eliminates the volt-second error in the
NLC method) and therefore leads to reduced harmonics.
It has been shown in [30] [31] that by selecting proper
common-mode voltage injections, carrier-based modulation
can be functionally equivalent to SVM. However, SVM can
conveniently provide more flexibility to optimize switching
waveforms, such as redundant switching states and adjustable
duty cycles [31]-[33], and is more suited to digital
implementations. The obstacle for applying SVM to multilevel
converters is the difficulty caused by the largely increased
number of switching states and switching sequences that
accompany the higher number of levels. Generally, for a threephase n-level converter, there are n3 switching states and 6(n1)2 triangles in the space vector diagram [20]. Several SVM
methods [19]-[23] are known for three-level converters, but
due to some drawbacks (as discussed in detail in [32]), those
methods are not readily extended to four or higher level
0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
2
converters. The determination of all redundant switching

states and appropriate switching sequences are the most
difficult tasks for SVM methods.
Because of the abovementioned challenges of SVM
methods, nearest-level modulation is attracting much
attention, especially for the MMCs [24]-[26]. Nearest-level
modulation modulates each phase of the converter based on
two discrete voltage levels, which is the same as for a dc-dc
converter, and thus is easy to implement when the level
number of the converter is high. Recently, a fast and
generalized SVM method for any multilevel converter has
been presented in [32], which generates all the available
switching states and switching sequences based on two simple
and general mappings, and calculates the duty cycles simply
as if for a two-level SVM, thus independent of the level
number of the converter. Since now both the SVM and the
nearest-level modulation methods are well suited to multilevel
converters, their relationship, which is not fully understood,
should be comprehensively evaluated in order to avoid
continuous confusion among practicing engineers.
The objective of this paper is to establish the inherent
relationship between the SVM and the nearest-level
modulation methods, despite their apparent differences. It
leads to an efficient and flexible modulation method for any
multiphase multilevel converter. The rest of this paper is
organized as follows: Section II reviews the principles of the
SVM and the nearest-level modulation methods; Sections III
and IV demonstrate the equivalence between the SVM and the
nearest-level modulation methods; Section V further compares
the two modulation methods and introduces the generalized
and flexible modulation method for any multiphase multilevel
converter; Section VI presents some typical simulation and
experimental results; and Section VII concludes this paper.
II. PRINCIPLE OF SVM AND NEAREST-LEVEL MODULATION
A. Space Vector Modulation
The SVM method proposed in [32], as illustrated in Fig. 1,
is considered as an example to demonstrate the principle of
space vector modulation methods for n-level converters.
Though other SVM methods can be realized by different
approaches, they obey the same principle, as introduced
below.
Fig. 1(a) shows the space vector diagram of a five-level
converter and a reference vector Vref located inside it.
Increasing the level number of the converter by one always
forms an additional hexagonal ring of equilateral triangles,
which surrounds the outermost hexagon H0. In order to
synthesize the reference vector Vref, it is the task of an SVM
method to detect the modulation triangle P1P2P3 (i.e., the
nearest three vectors OP1, OP2, and OP3), to determine the
switching sequence (sequence of the nearest three vectors),
and to calculate the duty cycles (needed durations) of the
nearest three vectors.
The modulation triangle P1P2P3 is detected in [32] by
determining a set of nested hexagons (i.e., H1, H2, and H3) that
respectively correspond to a specific converter level number.
Fig. 1. SVM method proposed in [32]: (a) detecting the modulation

triangle; (b)-(c) two switching sequence modes.
After the equivalent two-level hexagon H3 that encloses the tip

of the reference vector Vref is detected, the origin of the
reference vector is shifted to the center of the two-level
hexagon H3 and a remainder vector Vref is generated. Based
on the remainder vector Vref, the switching sequences [e.g.,
142 141 041 031 in Fig. 1(b)] and duty cycles are
obtained in the same way as for a two-level converter, as
shown in Figs. 1(b) and (c). A more detailed explanation for
the symbols in Fig. 1 can be found in [32].
For a three-phase n-level converter, an output voltage space
vector that represents the switching states of all the phases is
defined [32] as
= ( + + )

(1)
where Vdc is the dc-link voltage of the converter; Sa, Sb, and Sc
(Sa, Sb, Sc=0, 1, n-1) are the switching states of phases A, B,
and C, respectively. Accordingly, the voltage of phase h (h=A,
B, or C) relative to the negative terminal of the dc-link is
ShVdc/(n-1). The definition in (1) makes the side length of
each modulation triangle (e.g., P1P2P3) in the space vector
diagram to be Vdc.
3
Corresponding to (1), the reference vector Vref of the n-level

converter is generated [32] as
= ( 1) + +
(2)
= #$ %&$ + #' %&' + #( %&(
(3)
where , !, and " are respectively the reference voltages

of phases A, B, and C relative to the negative terminal of the
dc-link. The nearest three vectors OP1, OP2, and OP3
[calculated from (1)] synthesize the reference vector as
follows [19]
where D1, D2, and D3 are the duty cycles of OP1, OP2, and
OP3, respectively.
The SVM method simultaneously deals with all the phases
(i.e., directly works on the line-to-line voltages), as shown in
(2). If a carrier-based or nearest-level modulation method is
adopted, the reference voltage of phase h (h=A, B, or C) is

=)
= )
= )
*+,
(
*+,
(
*+,
(
cos(1) + 2
(4a)
cos 1 ( 3 + 2
'
(4b)
cos 1 + ( 3 + 2
'
(4c)
where m is the modulation index; is the phase angle of the

phase A voltage; Vcom is the common-mode voltage and can be
constant or time-variant (such as third-order harmonics),
depending on the application [25] [34].
Substituting (4) into (2) rewrites the reference vector Vref as
= ( 1) ()
(
'
4 )
(5)
Equations (4) and (5) indicate that the common-mode voltage

Vcom has no influence on the reference vector Vref or the lineto-line voltages. Therefore, compared to the other two types of
modulation methods, the SVM method can be more flexibly
implemented in any modulation range without the need of
sophisticated reference voltage signals.
B. Nearest-Level Modulation
Unlike the SVM methods, the nearest-level modulation
method [24]-[26] directly controls the phase voltages of the
converter and allows the line-to-line voltages to be developed
implicitly. Fig. 2 illustrates the general approach of the
nearest-level modulation method. For each switching cycle,
the switching state Sh of phase h (h=A, B, or C) in (1) has two
values, i.e., Kh and Kh+1, and the corresponding duty cycles
are respectively 1-Dh and Dh. The reference voltage of each
phase in (4) is approximated by the two nearest voltage levels
KhVdc/(n-1) and (Kh+1)Vdc/(n-1), based on [25]
5 = (1 #5 )
67 *+,
89$
+ #5
(67 :$)*+,
89$
(67 :;7 )*+,

89$
(6)
Fig. 2. The reference voltage and the corresponding output phase

voltage Vh (h=A, B, or C) during a switching cycle Ts for the nearest-level
modulation method.
The switching states and duty cycles of each phase are

consequently obtained [25] as
<5 = int *
#5 = *
*7
*7
+,/(89$)
+, /(89$)
(7)
<5
(8)
where int(x) means the integer part of x. Considering the

definition of the switching state, the reference voltage of phase
h (h=A, B, or C) should be within the following range
0 5
(9)
which implies that if the common-mode voltage is a constant

(e.g., 2 = ) /3), the modulation index m should be
less than 0.866. However, there is no such restriction for the
SVM methods.
It is shown by (6)-(9) that for the nearest-level modulation
method, the switching states and the corresponding duty
cycles for each phase are influenced by the common-mode
voltage Vcom, and thus sometimes dedicated reference voltages
are required in order to achieve a better performance, such as
higher modulation indexes [25]. This is discussed in more
detail in the next sections. Substituting (4) into (9) gives the
following feasible region for the common-mode voltage
min($ , $ , $ ) 2 max($ , $ , $ )
(10)
where min(Va1, Vb1, Vc1) and max(Va1, Vb1, Vc1) respectively

mean the minimum and maximum value among Va1, Vb1, and
Vc1; and Va1, Vb1, and Vc1 respectively represent the
fundamental-frequency components of (h=A, B, or C) as
$ = )
$ = )
*+,
(
*+,
(
cos(1)
(11a)
cos 1 ( 3
'
(11b)
4
$ = )
*+,
(
cos 1 + ( 3
'
(11c)
C. Apparent Difference between SVM and Nearest-Level

Modulation
Illustrated in Fig. 3 are the switching sequence and the
corresponding duty cycles of the SVM and the nearest-level
modulation methods. For the SVM method, the continuous
switching sequence pattern (i.e., all the phases are modulated
during a switching cycle) is considered as an example in the
following analysis. The discontinuous SVM patterns [34] (i.e.,
eliminating either the first or last switching state in each
switching sequence) can be analyzed in a similar way.
As shown in Fig. 3(a), for the SVM method, four switching
states compose a switching sequence and the first and last
switching states are redundant switching states. For example,
the switching sequences shown in Fig. 1 are 142 141
041 031 for mode=1 (descending mode) and 031 041
141 142 for mode=2 (ascending mode) [32]. Since the
redundant switching states (e.g., 142 and 031) produce the
same voltage space vector, their duty cycles (i.e., d01 and d02)
can be freely adjusted as long as the summation is a constant
[32] [34]:
HI$ + HI' = 1 H$ H' , HI$ 0 and HI' 0
(12)
I$ + N
$ + N
' + N
I' + N
MI$ + NO M$ + N O M' + N O MI' + N O
I$ + N
$ + N
' + N
I' + N
(13)
When the reference vector is located in the low modulation

regions, e.g., m< (n-2)/(n-1) in (5), for any switching sequence
shown in Fig. 3(a), a set of redundant switching sequences can
be generated by the SVM method [32] [34] [35] as
where k is an integer and
min(I$ , I$ , I$ ) N
Through the above description, no obvious relationship

between the SVM and the nearest-level modulation methods
can be observed. It also seems that compared to the SVM
method, two degrees of freedom, i.e., the redundant switching
sequences and the adjustable duty cycles, are lost in the
nearest-level modulation method. The essential reason for this
phenomenon is discussed below in detail, together with
demonstrating the equivalence of the two modulation
methods.
III. EQUIVALENCE OF SVM TO NEAREST-LEVEL
MODULATION
2 max(I$ , I$ , I$ ) , if I' > I$
(14a)
1 max(I$ , I$ , I$ ) , if I' < I$
(14b)
1 min(I$ , I$ , I$ ) N
Fig. 3. The switching states and the corresponding duty cycles of the
modulation methods: (a) SVM; (b) nearest-level modulation in ascending
mode; (c) nearest-level modulation in descending mode.
where min(Sa01, Sb01, Sc01) and max(Sa01, Sb01, Sc01) are

respectively the minimum and maximum values among Sa01,
Sb01, and Sc01.
The nearest-level modulation method also generally
arranges the switching sequences in two modes, i.e., the
ascending and descending modes, as respectively shown in
Figs. 3(b) and (c). For every switching cycle, the switching
states of each phase are increasing (from Kh to Kh+1) in the
ascending mode while decreasing (from Kh+1 to Kh) in the
descending mode. Note that in order to reduce the harmonics
in line-to-line voltages, all the phases should adopt the same
switching sequence mode (ascending or descending) for each
switching cycle.
The SVM method can equivalently realize the switching

sequences and the duty cycles generated by the nearest-level
modulation method, as demonstrated below. Now the
switching states Kh and Kh+1 (h=A, B, or C) and the
corresponding duty cycles 1-Dh and Dh (h=A, B, or C) shown
in Figs. 3(b) and (c) are already generated by the nearest-level
modulation method based on (6)-(9), for any valid commonmode voltage. Without loss of generality, assume
# # #
(15)
According to (15), the switching states and the

corresponding duty cycles for the three phases, generated by
the nearest-level modulation method, can be arranged in the
following two ways to construct two switching sequences:
5
< + 1
< + 1
<
<
M< + 1O M< + 1O M< + 1O
M< O
< + 1
<
<
<
#
# #
# #
1 #
<
<
< + 1
< + 1
M< O
M< + 1O M< + 1 O M< + 1O
<
<
<
< + 1
1 #
# #
# #
#
(16a)
(16b)
which are equivalent to the descending and ascending

switching sequences shown in Figs. 3(c) and (b), respectively.
For example, Fig. 4 illustrates the switching sequence
obtained from (16b); reversing it gives the sequence in (16a).
Each switching sequence in (16) can be represented as the
sequence shown in Fig. 3(a), but is it a result of the SVM
method? To answer this question, (6) is re-written as
= (HI$ I$ + H$ $ + H' ' + HI' I' ) /( 1)
(17a)
= (HI$ I$ + H$ $ + H' ' + HI' I' ) /( 1)
(17b)
= (HI$ I$ + H$ $ + H' ' + HI' I' ) /( 1)
(17c)
which by respectively multiplying (17b) with and (17c)

with , leads to the following equation

'
( 1) V + ( + ( X
'
= HI$ VI$ + I$ ( + I$ ( X

'
'
+H$ V$ + $ ( + $ ( X
+H' V' + ' ( + ' ( X
+HI' I' + I' + I'

(18)
It is seen that (17) gives a particular solution to (18), by

separating the components of each phase.
According to (2), the left side of (18) is exactly the
reference vector Vref. Comparing (18) with (3) indicates that
each switching sequence in (16) actually represents a valid
switching sequence for the SVM method under the continuous
modulation pattern [32] [34]. In (16a), the switching state of
each phase is descending in the switching sequence, such as
the switching sequence 142 141 041 031 for mode=1
shown in Fig. 1. On the contrary, (16b) represents an
ascending switching sequence, such as the switching sequence
031 041 141 142 for mode=2 shown in Fig. 1.
Fig. 4. The switching sequence shown in (16b)
The above analysis reveals that the result of the nearestlevel modulation method is a particular solution to the SVM
method. Since for the nearest-level modulation method the
common-mode voltage Vcom can only have a fixed value at any
given time, while for the SVM method Vcom can be any value,
the fixed common-mode voltage in (17) causes the loss of the
two degrees of freedom (i.e., the redundant switching
sequences and the adjustable duty cycles). In other words, the
common-mode voltage is the essential reason that results in
the apparent difference between the SVM and the nearestlevel modulation methods.
Note that for a given reference vector, there is only one
valid switching sequence for each mode (ascending or
descending) if the first switching state is determined [32] [34].
Therefore, the corresponding switching sequence can be
selected based on the reference voltage of phase h (h=A, B,
or C), or the common-mode voltage, adopted by the nearestlevel modulation method. The first switching state of the
switching sequence generated by the SVM method is
I$
< + 1
MI$ O = M< + 1O , if (16a) is adopted
I$
< + 1
(19a)
I$
<
MI$ O = M< O , if (16b) is adopted
<
I$
(19b)
HI$
#
H$
# #
] ^=]
^ , if (16a) is adopted
# #
H'
1 #
HI'
(20a)
which consequently yields the remainder vector Vref in Fig. 1

for the SVM method [32]. The corresponding duty cycles are
6
0.9
0.8
Vcom, max
Vcom / Vdc
0.7
0.6
0.5
0.4
0.3
Vcom, min
0.2
0.1
0
0.005
0.01
0.015
0.02
t [s]
(a)
0.9
0.8
Vcom / Vdc
0.7
0.6
0.5
Vcom, max
Vcom, min
0.4
0.3
0.2
0.1
0
0.005
0.01
0.015
0.02
t [s]
(b)
Fig. 5. Feasible region of the common-mode voltage for different
modulation index: (a) m=0.9; (b) m=0.6.
1
Area / A0
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
Substituting (7) and (8) into (19) and (20) reveals that the
effect of adjusting the common-mode voltage in the nearestlevel modulation method is equivalently achieved in the SVM
method by selecting the proper redundant switching sequence,
as in (19), and adjusting the duty cycles of the switching
states, as in (20).
Furthermore, since the duty cycle Dh (h=A, B, or C) is the
fractional part of ( 1) / , as expressed in (8), its
adjustment only means a minor change to the common-mode
voltage. Large variations of the common-mode voltage are
handled in (19) by adjusting the redundant switching sequence
[i.e., the switching state Kh (h=A, B, or C)]. If the adjustment
of the common-mode voltage is small, i.e., not cause any
switching state Kh (h=A, B, or C) to change, the duty cycles of
the middle two switching states (i.e., d1 and d2) in the
switching sequence are constant in (20). The reason is that the
common-mode voltage has the same effect on the duty cycles
of all the phases as in (8), so the effect is eliminated in the
subtraction between the duty cycles of any two phases.
Therefore, in this case, only the duty cycles of the first and the
last switching states (i.e., d01 and d02) need to be adjusted in
the SVM method.
The feasible region of the common-mode voltage for
different modulation indexes (e.g., m=0.9 and 0.6) of threephase converters is illustrated in Fig. 5, where Vcom, max and
Vcom, min respectively represents the maximum and minimum
limits of the common-mode voltage as in (10). The
fundamental frequency for Fig. 5 is 50 Hz. A comparison
between Figs. 5(a) and (b) reveals that the feasible region
(encircled by the waveforms of Vcom, max and Vcom, min) of the
common-mode voltage is larger for m=0.6 than for m=0.9. The
area of the feasible region for the common-mode voltage
according to a set of different modulation indexes (from 0 to
1) is shown in Fig. 6, where the area is normalized with
respect to A0 (i.e., the area of the feasible region for the
common-mode voltage when m=0). Figs. 5 and 6 demonstrate
that when the modulation index decreases, the adjustable
range of the common-mode voltage becomes larger and
therefore more redundant switching states/sequences need to
be generated by the SVM method according to (19). This has
already been verified for the SVM method in [32] [34].
In order to observe the influence of the common-mode
voltage on the duty cycles, the switching states in (19) are kept
unchanged when the common-mode voltage varies. For
example, to produce the same switching states with those
caused by Vcom, min, the maximum value of the common-mode
voltage is
+,
7,cde
2_ = min `min5a,, ghhhhhihhhhhj
5$ , 2,2l m
89$
b6
Fig. 6. Area of the feasible region of the common-mode voltage according

to different modulation index (m)
HI$
1 #
H$
# #
] ^=]
^ , if (16b) is adopted
# #
H'
#
HI'
(20b)
:$f*
*,kc,7
(21)
where min(x, y) means the smaller value between x and y; Kh,

(h=A, B, or C) is the switching state of phase h obtained
from (7) for Vcom, min; Vh1 is the fundamental-frequency
min
7
0.5b2_ 2,2_8 f cos (3pq)
0.7
where =2*50 rad/s is the fundamental angular frequency.

As discussed above, the switching state of each phase is
always Kh = Kh, min, for any common-mode voltage between
Vcom, min and Vmid. Therefore, when Vcom= 0.5(Vmid + Vcom, min),
the duty cycles of the first and the last switching states in each
switching sequence are equal, i.e., d01/d0 is always 0.5 where
d0= d01+d02. The third-order harmonic added to the commonmode voltage in (22) causes the normalized duty cycle of the
first switching state (i.e., d01/d0) to vary, as shown in Fig. 7(b),
and the variations for the descending mode (solid line) and the
ascending mode (dashed line) are symmetric with respect to
d01/d0= 0.5.
It can be concluded that for any common-mode voltage
injection, a nearest-level modulation method can be
equivalently realized by an SVM method by selecting the
proper redundant switching sequence and duty cycles. The
influence of the common-mode voltage is reflected in the
SVM by the redundant switching states and their duty cycles
in the following two steps: 1) determine the proper switching
sequence based on (19), called coarse tuning; 2) adjust the
duty cycles of the first and the last switching states in the
switching sequence based on (20), called fine tuning.
IV. EQUIVALENCE OF NEAREST-LEVEL MODULATION TO
SVM
On the other hand, it can be shown that any switching
sequence and corresponding duty cycles generated by the
SVM method can be equivalently obtained from a nearestlevel modulation method.
For any optimized switching sequence (with the minimum
number of switch transitions in every switching cycle under
continuous modulation) generated by the SVM method, as
shown in Fig. 3(a), there are only two successive values Sh and
Sh+1 (h=A, B, or C) for the switching state of each phase [32]
[34]. For example, the switching state of phase B for the
reference vector shown in Fig. 1 can only have the values of 4
and 3 in the switching sequence 142 141 041 031 for
mode=1 (descending mode) or 031 041 141 142 for
mode=2 (ascending mode). Since the first and the last
switching states in the switching sequence are redundant
switching states, the value of Sh (h=A, B, or C) can be
obtained as
Vcom, max
Vcom
0.6
0.5
0.4
Vcom, min
(22)
0.3
0.2
0
0.005
0.01
0.015
0.02
t [s]
(a)
1.5
Descending mode
Ascending mode
1
d01 / d0
2 = 0.5b2_ + 2,2_8 f
0.8
Vcom / Vdc
component of phase h reference voltage as shown in (11);

Vcom, h represents the common-mode voltage required for phase
h to change its switching state to Kh, min+1; and [minh=a,b,c(Vcom,
h)] gives the minimum value among Vcom, h (h=A, B, or C).
Fig. 7 demonstrates the required duty cycle d01 of the first
switching state for a five-level converter as an example, when
the modulation index is m=0.9, for a common-mode voltage:
0.5
-0.5
0
0.005
0.01
0.015
0.02
t [s]
(b)
Fig. 7. Influence of the common-mode voltage on the duty cycle of the
first switching state in each switching sequence, for modulation index
m=0.9 of a five-level converter: (a) the common-mode voltage Vcom in
(22); (b) the duty cycle d01 of the first switching state in each switching
sequence for the two switching sequence modes.

I$
M O = MI$ O , if I' > I$ (ascending mode)

I$

I'
M O = MI' O , if I' < I$ (descending mode)

I'
(23a)
(23b)
The required reference voltage (h=A, B, or C) for the

nearest-level modulation method can be generated based on
(17), and the duty cycles of the same switching state can be
combined for each phase. For instance, if the switching
sequence is 031 041 141 142 (mode=2), the reference
voltages for the three phases are respectively
= (HI$ + H$ )
( + 1)

+ (H' + HI' )
1
1
= ( + H ) /( 1)
(24a)
8
= HI$
( + 1)

+ (H$ + H' + HI' )
1
1
= ( + H ) /( 1)
= (HI$ + H$ + H' )
( + 1)

+ HI'
1
1
= ( + H ) /( 1)
in each switching sequence are constant [32] [34], so the

adjustment for the common-mode voltage in (26) is
(24b)
(24c)
where [Sa, Sb, Sc]T = [0, 3, 1]T, and
H
H' + HI'
MH O = MH$ + H' + HI' O
H
HI'
(25)
For any other continuous switching sequence, an equation

similar to (24) can be generated. In fact, (23) and (25) are
respectively the reverse processing of (19) and (20).
For a valid switching sequence of an n-level converter
generated by the SVM method, 0 Sh n-1 and 0 Sh+1 n-1
(h=A, B, or C), so the reference voltages (h=A, B, or C) for
the nearest-level modulation method obtained from (17) or
(24) meet the constraint in (9). Therefore, these reference
voltages can be applied to the nearest-level modulation
method. Based on the switching states in (23) and the duty
cycles in (25) for these reference voltages, the switching
sequence of the SVM method can be equivalently produced by
the nearest-level modulation method according to (16).
The corresponding common-mode voltage Vcom is
1
2 = ( + + )
3
=

s t (HI$ 5I$ + H$ 5$ + H' 5' + HI' 5I' )u
3( 1)
5a,,
(26)
For example, for the switching sequence 031 041 141
142 (mode=2), substituting (24) into (26) yields
+,
( + + + H$ + 2H' + 3HI' ) (27)
2 = ((89$)
The duty cycles (i.e., d01 and d02) of the first and the last
switching states in the switching sequence can be freely
adjusted as long as the summation is a constant, as shown in
(12). When the reference vector is located in the low
modulation regions, as expressed in (13), a set of redundant
switching sequences can be generated by the SVM method.
According to (26) and (27), the two degrees of freedom (i.e.,
the redundant switching sequences and the adjustable duty
cycles) provided by the SVM method can be equivalently
achieved in the nearest-level modulation method by adjusting
the common-mode voltage. For a given reference vector, the
duty cycles (i.e., d1 and d2) of the middle two switching states
2 = (N + HI' )

,
1
if I' > I$ (i. e. , ascending mode)
(28a)
if I' < I$ (i. e. , descending mode)
(28b)
2$ = 0.5b2_ + 2,2_8 f
(29a)
2 = (N HI' )

,
1
where k denotes the change of the redundant switching states

as in (13), and d02 represents the adjustment for the duty
cycle of the last switching state. For example, (28a) shows the
required adjustment for the common-mode voltage in (27).
Fig. 8 illustrates the relationship between the commonmode voltage and the duty cycle of the last switching state for
a five-level converter when the modulation index is m=0.9, in
ascending switching sequence mode. Vcom, max and Vcom, min are
respectively the maximum and minimum limits of the
common-mode voltage as in (10); and Vmid is the commonmode voltage obtained from (21). In Fig. 8(b), ,w x, ,wyz ,
and ,wy{ respectively represent the corresponding reference
voltages of phase A when the common-mode voltages are
Vcom, max, Vcom, min, and Vmid. According to (28), the adjustable
range of the duty cycle (d02) of the last switching state for the
common-mode voltage Vmid is depicted in Fig. 8(c), where
d02, max and d02, min are respectively the adjustments of d02 in
order to achieve the maximum and minimum limits of the
common-mode voltage. The adjustment (d02) of d02 can be
any value between d02, max and d02, min, and this adjustment
can be realized in the nearest-level modulation method by
tuning Vmid based on (28).
Note that there are generally two types of outermost
modulation triangles for any multilevel converter. Fig. 9
shows the outermost triangles of a five-level converter as an
example. For a given reference vector, the type I triangle (with
one vertex on the five-level hexagon) leads to two switching
sequences for each switching sequence mode, e.g., 031 041
141 142 and 030 031 041 141 for the
ascending mode for P1P2P3. The type II triangle (with two
vertexes on the five-level hexagon) generates only one
switching sequence for each switching sequence mode, e.g.,
031 041 042 142 for the ascending mode for
P1P2P4. These two types of outermost modulation triangles
are reflected by the relationship between Vcom, max and Vmid in
Fig. 8. If Vmid < Vcom, max, then the reference vector is located in
a type I triangle, and the maximum and minimum limits of the
common-mode voltage cause different switching sequences. In
contrast, when Vmid = Vcom, max, the reference vector is located
in a type II triangle. The following common-mode voltages
make the duty cycles of the first and the last switching states
in each switching sequence to be equal, for a type I triangle:
9
0.8
Vcom, max
Vcom / Vdc
0.7
Vmid
0.6
0.5
0.4
Vcom, min
0.3
0.2
0
0.005
0.01
0.015
0.02
t [s]
(a)
1.2
1
Va, max
0.8
Va / Vdc
Fig. 9. Switching states for the outermost modulation triangles of a fivelevel converter
0.6
0.4
0.2
0
-0.2
0
Va, min
*
Va, mid
0.005
0.01
0.015
Fig. 10. Switching states of phase h (h=A, B, or C) for the nearest-level

modulation method, in order to obtain the switching sequence generated
by the SVM method shown in Fig. 3(a)
0.02
t [s]
(b)
1.5
d
02, max
02, min
d02
0.5
0
-0.5
-1
-1.5
0
0.005
0.01
0.015
0.02
t [s]
(c)
Fig. 8. An example of the relationship between the common-mode voltage
and the duty cycles, for modulation index m=0.9 of a five-level converter:
(a) the common-mode voltage Vmid; (b) the reference voltage of phase A;
(c) the available adjustment region of the duty cycle of the last switching
state.
2' = 0.5b2_ + 2,2l f
(29b)
For a type II triangle, only (29a) is applied. Similar

conclusions can be obtained when the reference vectors are
located in the low-modulation regions.
It should be also noted that sometimes the optimized
switching sequence [32] [34] discussed in this section may not
be adopted by the SVM method. For example, the switching
states of the nearest three vectors are selected in [4] for
achieving the best capacitor voltage balancing, without
considering minimizing the number of switch transitions. The
question then is whether the nearest-level modulation method
can equivalently realize the SVM method in these conditions?
The answer is yes. No matter what switching states are
selected by the SVM method, the required reference voltage of
each phase can always be generated based on (17) for the
nearest-level modulation method. Consequently, the switching
sequence can be obtained similarly from (16) as a reverse
process, except that the reference phase voltage may be
approximated by other voltage levels instead of the two
nearest levels. Fig. 10 shows a general arrangement of the
switching states for the nearest-level modulation method, in
order to obtain the switching sequence shown in Fig. 3(a).
In summary, by selecting the proper common-mode voltage
injection and appropriately arranging the switching states and
the corresponding duty cycles for each phase, a nearest-level
modulation method can equivalently achieve an SVM method.
10
V. RESPECTIVE ADVANTAGES OF SVM AND NEAREST-LEVEL

MODULATION
It has been demonstrated in the previous sections that the
SVM and the nearest-level modulation methods can produce
identical switching sequences despite their apparent
differences. However, due to their respective advantages these
two modulation methods have different suitable applications,
as introduced below.
A. Flexible Switching Patterns
Compared to the nearest-level modulation, the SVM
method is much more convenient to handle the tasks when
particular switching patterns are desired, e.g., in the
applications of capacitor voltage balancing for diode-clamped
multilevel converters [3] [4] [35] where the optimal switching
sequence and duty cycles are needed. The SVM method can
flexibly adjust the redundant switching sequences and duty
cycles [32], while the same function achieved by the nearestlevel modulation method requires sophisticated selection of
the common-mode voltage, as illustrated in Figs. 5-8.
Considerable computational effort may be needed by the
nearest-level modulation method to search for the best
common-mode voltage, especially when the reference vector
is located in the low-modulation regions. As explained before,
the essential reason is: the common-mode voltage is fixed in
the nearest-level modulation method, while it can be any value
in the SVM method.
B. Computational Complexity
The major advantage of the nearest-level modulation
method is the less computational burden compared to previous
SVM methods. However, the fast and generalized SVM
method proposed in [32] has overcome the drawbacks of the
previous SVM methods and achieved the same time
complexity [i.e., O(n), where n is the level number of the
converter] with the nearest-level modulation method, if the
nearest-level modulation method is also desired to generate all
the redundant switching sequences. Therefore, computational
complexity is no longer an obstacle for the SVM method. The
SVM method in [32] can be further simplified for three-phase
multilevel applications, which will be introduced in future
papers.
C. Multiphase Multilevel Applications
Since the nearest-level modulation method directly controls
the voltage of each phase, it is more suitable than the SVM
method for multiphase multilevel applications. Based on the
relationship between the two modulation methods established
in the previous sections, an efficient and flexible modulation
method for any multiphase multilevel converter is proposed as
follows. It combines the advantages of the nearest-level
modulation and the SVM methods, i.e., both with less
computational burden and high flexibility of optimizing the
switching patterns.
For a p-phase n-level converter, the reference voltage y of
phases i (i=1, 2, p) is
_ = ) cos 1 (| 1)
'
}
+ 2
(30)
Assume the duty cycles Di of phase i (i=1, 2, p) obtained

from (8) have the following relationship
#$ #' #}
(31)
which leads to two switching sequences in two modes

(descending and ascending modes) similar to (16), but now
there are p+1 switching states in each switching sequence. As
discussed before, for each valid switching sequence, the duty
cycles of the middle switching states are constant. Therefore,
only the duty cycles (i.e., D1 and 1-Dp) of the first and the last
switching states need to be adjusted, and the summation of
these two duty cycles should be kept constant.
If the redundant switching sequences similar to (13) are
required, or the duty cycles of the first and the last switching
states need to be tuned, then the corresponding adjustment of
the common-mode voltage is [similar to (28)]
2 = (N + H) /( 1)
(32)
where k denotes the change of the redundant switching states

as in (13); and d represents the adjustment for the duty cycle
of the switching state [K1+1, K2+1, , Kp+1]T, i.e., the first
switching state if (16a) is adopted (descending mode), or the
last switching state if (16b) is adopted (ascending mode). The
feasible range of d is
#$ H 1 #}
(33)
In summary, the proposed multiphase multilevel

modulation method contains the following steps:
1) Step 1: Select a typical common-mode voltage. Calculate
the switching states and the duty cycles based on (7) and (8).
2) Step 2: Arrange the switching states and duty cycles of
each phase as in (16).
3) Step 3: If needed, adjust the common-mode voltage
within its feasible region [similar to (10)] according to (32).
4) Step 4: Generate the reference voltage for each phase
from (30) based on the adjusted common-mode voltage.
Fig. 11 demonstrates the simulated output waveforms of a
five-phase five-level converter as an example, when the
modulation index is m=0.45, for a typical common-mode
voltage:
2 = 0.5b2,2l + 2,2_8 f
(34)
where Vcom, max and Vcom, min are respectively the maximum and
minimum limits of the common-mode voltage. The
fundamental frequency and switching frequency in the
simulation are 50 Hz and 5 kHz, respectively. In the figures,
and Va respectively denote the reference and the actual
output voltages of the 1st phase; ! (= ! ) and Vab
respectively represent the reference and the actual output lineto-line voltages (1st phase to 2nd phase).
11
0.7
0.65
Vcom, max
0.7
Vcom
0.6
Vcom / Vdc
Vcom / Vdc
0.6
0.55
0.5
0.45
0.4
0.4
Vcom, min
0.35
0.3
0
0.5
0.005
0.01
0.015
0.3
0.02
0.005
0.01
t [s]
0.015
0.02
t [s]
(a)
(a)
1.2
0.7
1
*
Va
com, max
0.6
0.6
Vcom / Vdc
Va / Vdc
0.8
Va
0.4
0.2
0.5
0.4
0.3
-0.2
0
com
0.005
0.01
0.015
0.02
t [s]
0.005
com, min
0.01
0.015
0.02
t [s]
(b)
(b)
Fig. 12. The common-mode voltage obtained from different ways: (a) the
SVM method in [32]; (b) the relationship in (29).
0.8
0.6
Vab / Vdc
0.4
0.2
0
Vab
Vab
-0.2
-0.4
-0.6
-0.8
0
0.005
0.01
0.015
0.02
t [s]
(c)
Fig. 11. Simulated output waveforms of a 5-phase 5-level converter for
the common-mode voltage in (34) when modulation index m=0.45: (a) the
common-mode voltage; (b) the output voltage of the 1st phase; (c) the lineto-line voltage (1st phase to 2nd phase).
VI. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results
Simulations are implemented in Matlab/Simulink for a

three-phase five-level converter, to compare the SVM [32] and
the nearest-level modulation methods. In the simulation, the
switching frequency is 5 kHz (fundamental frequency is 50
Hz), the modulation index is 0.9, and the duty cycles of the
first and the last switching states in each switching sequence
are equal.
Fig. 12 illustrates the common-mode voltage Vcom for this
operating condition, calculated in two ways: a) based on (17)
for each switching sequence generated by the SVM method; b)
obtained from (29) based on the equivalence of the nearestlevel modulation method. It is seen that these two ways give
exactly the same result of the common-mode voltage. Fig.
13(a) shows the phase voltage Va (phase A) of the converter
generated by the SVM method, where * is the corresponding
reference phase angle in (5). Based on the common-mode
voltage shown in Fig. 12(b), the same phase voltage is
produced by the nearest-level modulation method as illustrated
in Fig. 13(b), where is the reference phase voltage. The
simulation results in Figs. 12 and 13 demonstrate the
equivalence of the two modulation methods.
12
1.2
1
1.2
*/(2)
dc
0.6
0.4
0.2
0.2
-0.2
0
0.8
V /V
dc
0.4
V /V
0.6
0.8
0.005
0.01
0.015
-0.2
0
0.02
t [s]
V*
a
0.005
0.01
0.015
0.02
t [s]
(a)
(b)
Fig. 13. Simulated phase A voltage of the five-level converter in Matlab Simulink: (a) the SVM method in [32]; (b) the nearest-level modulation method.
(a)
(b)
Fig. 14. Experimental results from the DSP outputs of the phase voltage (phase A) for the five-level converter, represented by the corresponding switching states
generated by the two modulation methods: (a) the SVM method in [32]; (b) the nearest-level modulation method.
13
B. Experimental Results
An experiment is also carried out based on a
TMS320CF2812 DSP (digital signal processor) to
demonstrate the equivalence between the SVM method [32]
and the nearest-level modulation method. The experiment is
implemented by first running the SVM and then the nearestlevel modulation algorithm on the DSP in real time for any
received reference voltage, for the three-phase five-level
converter. The DSP does not send gate signals to drive any
power electronic switches, but instead sends the switching
states generated by the two modulation algorithms to a digitalto-analog converter for observation, which represent the
voltages of the converter as described in (1). An actual
converter is not required for this experiment.
For the experiment, the switching frequency is 500 Hz in
order to highlight the switch transitions. Other operation
conditions are the same as that adopted in the simulations;
again, the common-mode voltage obtained from (29) is
applied to the nearest-level modulation method. Fig. 14
demonstrates the corresponding experimental results from the
DSP outputs of the SVM method and the nearest-level
modulation method, which also indicate the equivalence of the
two modulation methods.
mode voltage, for achieving the desired redundant switching

sequences and tuning the corresponding duty cycles, is
established.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
VII. CONCLUSION
This paper has studied the inherent relationship between the
space vector modulation (SVM) method and the nearest-level
modulation method for multilevel converters. It is concluded
that the SVM and the nearest-level modulation methods are
functionally equivalent: 1) by injecting the proper commonmode voltage, the nearest-level modulation method can
equivalently realize the SVM method; 2) by selecting the
appropriate redundant switching sequence and duty cycles (of
the first and the last switching states in each switching
sequence), the SVM method can equivalently realize the
nearest-level
modulation
method.
Simulation
and
experimental results validate the analysis.
However, these two modulation methods have different
suitable applications, due to their respective advantages. The
SVM method is much more convenient to handle the tasks
when particular switching patterns are desired, e.g., in the
application of capacitor voltage balancing for multilevel
converters where the optimal switching sequence and duty
cycles are preferred. The essential reason is: the commonmode voltage is fixed in the nearest-level modulation method,
while it can be any value in the SVM method. In contrast,
because of the phase-voltage modulation approach, it is more
suitable for the nearest-level modulation method to apply to
multiphase multilevel converters.
Based on the relationship between the nearest-level
modulation and the SVM described in this paper, a general
and flexible modulation method for any multiphase multilevel
converter is proposed. It combines the advantages of the
nearest-level modulation and the SVM methods, i.e., both with
less computational burden and high flexibility of optimizing
the switching patterns. The adjustment rule of the common-
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
J. Rodriguez, J. S. Lai, and F. Z. Peng, Multilevel inverters: A survey

of topologies, controls, and applications, IEEE Trans. Ind. Electron.,
vol. 49, no. 4, pp. 724-738, Aug. 2002.
A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped
PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523,
Sept./Oct. 1981.
S. Busquets-Monge, S. Alepuz, J. Rocabert, and J. Bordonau,
Pulsewidth Modulations for the Comprehensive Capacitor Voltage
Balance of n-Level Three-Leg Diode-Clamped Converters, IEEE
Trans. Power Electron., vol. 24, no. 5, pp. 1364-1375, May 2009.
M. Saeedifard, R. Iravani, and J. Pou, Analysis and Control of DCCapacitor-Voltage-Drift Phenomenon of a Passive Front-End Five-Level
Converter, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 3255-3266,
Dec. 2007.
J. Amini, An Effortless Generalized Space Vector Based Modulation
for N-level Flying Capacitor Multilevel Inverter with Capacitor Voltage
Balancing Capability, IEEE Trans. Power Electron., vol. PP, no. 99,
pp. 1, 2014.
M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Prez, A
Survey on Cascaded Multilevel Inverters, IEEE Trans. Ind. Electron.,
vol. 57, no. 7, pp. 2197-2206, July 2010.
A. Lesnicar and R. Marquardt, An innovative modular multilevel
converter topology suitable for a wide power range, in Proc. IEEE
Power Tech Conf. Proc., June 2003.
M. Guan and Z. Xu, Modeling and Control of a Modular Multilevel
Converter-Based HVDC System Under Unbalanced Grid Conditions,
IEEE Trans. Power Electron., vol. 27, no. 12, pp. 4858-4867, Dec.
2012.
F. Deng and Z. Chen, A Control Method for Voltage Balancing in
Modular Multilevel Converters, IEEE Trans. Power Electron., vol. 29,
no. 1, pp. 66-76, Jan. 2014.
D. C. Ludois, and G. Venkataramanan, Simplified Terminal Behavioral
Model for a Modular Multilevel Converter, IEEE Trans. Power
Electron., vol. 29, no. 4, pp. 1622-1631, Apr. 2014.
S. Shao, P. W. Wheeler, J. C. Clare, and A. J. Watson, Fault Detection
for Modular Multilevel Converters Based on Sliding Mode Observer,
IEEE Trans. Power Electron., vol. 28, no. 11, pp. 4867-4872, Nov.
2013.
M. Hagiwara and H. Akagi, Control and experiment of pulse width
modulated modular multilevel converters, IEEE Trans. Power
Electron., vol. 24, no. 7, pp. 17371746, Jul. 2009.
H. Mohammadi and M. T. Bina, A Transformerless Medium-Voltage
STATCOM Topology Based on Extended Modular Multilevel
Converters, IEEE Trans. Power Electron., vol. 26, no. 5, pp. 1534
1545, May 2011.
Q. Tu, Z. Xu, and L. Xu, Reduced Switching-Frequency Modulation
and Circulating Current Suppression for Modular Multilevel
Converters, IEEE Trans. Power Del., vol. 26, no. 3, pp. 20092017,
Jul. 2011.
E. Solas, G. Abad, et al., Modular Multilevel Converter With Different
Submodule ConceptsPart I: Capacitor Voltage Balancing Method,
IEEE Trans. Ind. Electron., vol. 60, no. 10, pp. 45254535, Oct. 2013.
D. Montesinos-Miracle, M. Massot-Campos, J. Bergas-Jane, S.
Galceran-Arellano, and A. Rufer, Design and Control of a Modular
Multilevel DC/DC Converter for Regenerative Applications, IEEE
Trans. Power Electron., vol. 28, no. 8, pp. 39703979, Aug. 2013.
M. Saeedifard and R. Iravani, Dynamic performance of a modular
multilevel back-to-back HVDC system, IEEE Trans. Power Del., vol.
25, no. 4, pp. 29032912, Oct. 2010.
J. Mei, B. Xiao, et al., Modular Multilevel Inverter with New
Modulation Method and Its Application to Photovoltaic Grid-Connected
Generator, IEEE Trans. Power Electron., vol. 28, no. 11, pp. 50635073, Nov. 2013.
N. Celanovic, D. Boroyevich, A fast space vector modulation algorithm
for multilevel three phase converters, IEEE Trans. Ind. Appl., vol. 37,
no. 2, pp. 637-641, Mar./Apr. 2001.
14
[20] A. Gupta, A. Khambadkone, A space vector PWM scheme for
multilevel inverters based on two-level space vector PWM, IEEE
Trans. Ind. Electron., vol. 53, no. 5, pp. 1631-1639, Oct. 2006.
[21] H. Zhang, A. Jouanne, et al., Multilevel inverter modulation schemes to
eliminate common-mode voltages, IEEE Trans. Ind. Appl., vol. 36, no.
6, pp. 1645-1653, Nov./Dec. 2000.
[22] J. Seo, C. Choi, and D. Hyun, A new simplified space-vector PWM
method for three-level inverters, IEEE Trans. Power Electron., vol. 16,
no. 4, pp. 545- 550, Jul 2001.
[23] B. Jacob, M. R. Baiju, Vector-Quantized Space-Vector-Based Spread
Spectrum Modulation Scheme for Multilevel Inverters Using the
Principle of Oversampling ADC, IEEE Trans. Ind. Electron., vol. 60,
no. 8, pp. 2969-2977, Aug. 2013.
[24] A. Antonopoulos, L. Angquist, and H. P. Nee, On dynamics and
voltage control of the modular multilevel converter, in Proc. Eur. Conf.
Power Electron., Sept. 2009, pp. 1-10.
[25] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, Modulation, losses,
and semiconductor requirements of modular multilevel converters,
IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2633-2642, Aug. 2010.
[26] Z. Li, P. Wang, et al., An Improved Pulse Width Modulation Method
for Chopper-Cell-Based Modular Multilevel Converters, IEEE Trans.
Power Electron., vol. 27, no. 8, pp. 3472-3481, August 2012.
[27] J. I. Leon, .S. Vazquez, J. A. Sanchez, et al., Conventional SpaceVector Modulation Techniques Versus the Single-Phase Modulator for
Multilevel Converters, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp.
2473-2482, July 2010.
[28] Q. Tu and Z. Xu, Impact of Sampling Frequency on Harmonic
Distortion for Modular Multilevel Converter, IEEE Trans. Power Del.,
vol. 26, no. 1, pp. 298-306, Jan. 2011.
[29] S. Kouro, R. Bernal, H. Miranda, C. A. Silva, and J. Rodriguez, HighPerformance Torque and Flux Control for Multilevel Inverter Fed
Induction Motors, IEEE Trans. Power Electron., vol. 22, no. 6, pp.
2116-2123, Nov. 2007.
[30] K. Zhou and D. Wang, Relationship Between Space-Vector Modulation
and Three-Phase Carrier-Based PWM: A Comprehensive Analysis,
IEEE Trans. Ind. Electron., vol. 49, no. 1, pp. 186-196, Feb. 2002.
[31] W. Yao, H. Hu, and Z. Lu, Comparisons of Space-Vector Modulation
and Carrier-Based Modulation of Multilevel Inverter, IEEE Trans.
Power Electron., vol. 23, no. 1, pp. 45-51, Jan. 2008.
[32] Y. Deng, K. H. Teo, C. Duan, T. G. Habetler, and R. G. Harley, A Fast
and Generalized Space Vector Modulation Scheme for Multilevel
Inverters, IEEE Trans. Power Electron., vol. 29, no. 10, pp. 5204-5217,
Oct. 2014.
[33] Y. Deng, K. H. Teo, and R. G. Harley, A Fast and Generalized Space
Vector PWM Scheme and Its Application in Optimal Performance
Investigation for Multilevel Inverters, in Proc. IEEE Energy
Conversion Congress and Exposition (ECCE), Sept. 2013, pp. 39773983.
[34] B. P. McGrath, D. G. Holmes, and T. Lipo, Optimized Space Vector
Switching Sequences for Multilevel Inverters, IEEE Trans. Power
Electron., vol. 18, no. 6, pp. 1293-1301, Nov. 2003.
[35] Y. Deng, K. H. Teo, and R. G. Harley, Generalized DC-Link Voltage
Balancing Control Method for Multilevel Inverters, in Proc. IEEE
Applied Power Electronics Conference and Exposition (APEC), March
2013, pp. 1219-1225.
Yi Deng (S12) received the B.S. and M.S. degrees

in electrical engineering from Tsinghua University,
Beijing, China, in 2008 and 2010, respectively. He is
currently working toward the Ph.D. degree in
electrical engineering at Georgia Institute of
Technology, Atlanta, GA, USA.
In 2012 and 2013 respectively from May to
August, he was a research intern in Mitsubishi
Electric Research Laboratories, Cambridge, MA,
where he filed three patents. His research interests
include power electronics (especially in medium
voltage and high power areas), electric machines and their drive systems,
renewable energy grid integration, FACTS devices, and power system control
and operation.
Ronald G. Harley (M77-SM86-F92) received the

M.Sc.Eng. degree (cum laude) in electrical
engineering from the University of Pretoria,
Pretoria, South Africa, in 1965, and the Ph.D. degree
from the University of London, London, U.K., in
1969.
He is currently a Regents Professor with the
School of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, USA, and
also a Professor Emeritus in the School of
Engineering, University of KwaZulu-Natal, Durban, South Africa. He has
coauthored more than 500 papers in refereed journals and international
conference proceedings and holds six patents. His research interests include
the dynamic behavior of electric machines, power systems and their
components, and controlling them by the use of power electronics and
intelligent control algorithms.
Dr. Harley received the Cyril Veinott Electromechanical Energy
Conversion Award from the IEEE Power Engineering Society for
Outstanding contributions to the field of electromechanical energy
conversion in 2005 and the IEEE Richard H. Kaufmann Field Award with
the citation For contributions to monitoring, control and optimization of
electrical processes including electrical machines and power networks in
2009.

Research Paper

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Research Paper

Hochgeladen von

Copyright:

Verfügbare Formate

This article has been accepted for publication in a future issue of this journal, but has not been

Space-Vector versus Nearest-Level Pulse Width

AbstractThis paper studies the inherent relationship between

ULTILEVEL converters are widely adopted in high-power

bridge with separate dc sources [6]. Another emerging

converters. The determination of all redundant switching

Fig. 1. SVM method proposed in [32]: (a) detecting the modulation

After the equivalent two-level hexagon H3 that encloses the tip

Corresponding to (1), the reference vector Vref of the n-level

 = #$ %&$ + #' %&' + #( %&(

where  , !, and " are respectively the reference voltages

where m is the modulation index; is the phase angle of the

Equations (4) and (5) indicate that the common-mode voltage

(67 :;7 )*+,

Fig. 2. The reference voltage  and the corresponding output phase

The switching states and duty cycles of each phase are

where int(x) means the integer part of x. Considering the

which implies that if the common-mode voltage is a constant

where min(Va1, Vb1, Vc1) and max(Va1, Vb1, Vc1) respectively

C. Apparent Difference between SVM and Nearest-Level

When the reference vector is located in the low modulation

where k is an integer and

min( I$ , I$ , I$ ) N

Through the above description, no obvious relationship

 2 max( I$ , I$ , I$ ) , if I' > I$

 1 max( I$ , I$ , I$ ) , if I' < I$

1 min( I$ , I$ , I$ ) N

where min(Sa01, Sb01, Sc01) and max(Sa01, Sb01, Sc01) are

The SVM method can equivalently realize the switching

According to (15), the switching states and the

which are equivalent to the descending and ascending

which by respectively multiplying (17b) with    and (17c)

with    , leads to the following equation

= HI$  V I$ + I$   ( + I$   ( X

+H'  V ' + '  ( + '  ( X

+HI'   I' + I'    + I'    

It is seen that (17) gives a particular solution to (18), by

Fig. 4. The switching sequence shown in (16b)

which consequently yields the remainder vector Vref in Fig. 1

Fig. 6. Area of the feasible region of the common-mode voltage according

where min(x, y) means the smaller value between x and y; Kh,

0.5b2_ 2,2_8 f cos (3pq)

where =2*50 rad/s is the fundamental angular frequency.

2 = 0.5b2_ + 2,2_8 f

component of phase h reference voltage as shown in (11);

The required reference voltage  (h=A, B, or C) for the

in each switching sequence are constant [32] [34], so the

where [Sa, Sb, Sc]T = [0, 3, 1]T, and

For any other continuous switching sequence, an equation

if I' > I$ (i. e. , ascending mode)

if I' < I$ (i. e. , descending mode)

2$ = 0.5b2_ + 2,2_8 f

where k denotes the change of the redundant switching states

Fig. 10. Switching states of phase h (h=A, B, or C) for the nearest-level

2' = 0.5b2_ + 2,2 l f

For a type II triangle, only (29a) is applied. Similar

V. RESPECTIVE ADVANTAGES OF SVM AND NEAREST-LEVEL

Assume the duty cycles Di of phase i (i=1, 2, p) obtained

which leads to two switching sequences in two modes

where k denotes the change of the redundant switching states

In summary, the proposed multiphase multilevel

VI. SIMULATION AND EXPERIMENTAL RESULTS

Simulations are implemented in Matlab/Simulink for a

= #$ %&$ + #' %&' + #( %&(

where , !, and " are respectively the reference voltages

Fig. 2. The reference voltage and the corresponding output phase

min(I$ , I$ , I$ ) N

2 max(I$ , I$ , I$ ) , if I' > I$

1 max(I$ , I$ , I$ ) , if I' < I$

1 min(I$ , I$ , I$ ) N

which by respectively multiplying (17b) with and (17c)

with , leads to the following equation

= HI$ VI$ + I$ ( + I$ ( X

+H' V' + ' ( + ' ( X

+HI' I' + I' + I'

0.5b2_ 2,2_8 f cos (3pq)

2 = 0.5b2_ + 2,2_8 f

The required reference voltage (h=A, B, or C) for the

2$ = 0.5b2_ + 2,2_8 f

2' = 0.5b2_ + 2,2l f