Chapter 3-Protected-Mode Software Architecture

of Intel Architecture-32 Processors

ECE3166- Advanced Microprocessors

Tutorial 3
1.

What function is served by the GDTR? What is stored in GDT?

2.

The content of the GDTR is 0013000000FFH. The descriptor for the

LDT is loaded at (starting) address 00130040H. What should be the
value loaded in the LDTR?

3.

Which control register contains the MSW? What must be done to turn
on paging?

4.

What are the names and sizes of the three fields in a selector? What
does TI equal 1 mean?

5.

What happens when the following instruction sequence is executed in

protected mode?
MOV AX, 1007H
MOV DS, AX

6.

Assume that the above instructions select a descriptor that specifies

the base as 00200000H and limit as FFFFH. If SI = 0100H, what is the
physical address of the data to be obtained from [SI]?

7.

Data segment selector register selects a descriptor at address

00100220H. The contents of the descriptor are:
[00100220H] =0110H
[00100222H] =0000H
[00100224H] =1A20H
[00100226H] =0000H
What are the LIMIT & the BASE of the data segment?

8.

Find the linear addresses of the instruction and the source operand for
the following instruction:
MOV EDX, [EAX]
Assuming that the GDT base address is 1010 AC80H, and the contents
of the registers and memory are as shown below:
Register Contents
Register Contents
LDTR
0020H
CS
0018H
EIP
0000 0030H
DS
0017H
EAX
0000 2000H
ES
0123H
SS
0053H

Chapter 3-Protected-Mode Software Architecture

of Intel Architecture-32 Processors

Contents (hex)
Linear address +0
+2
+4
1010AC80H
0000 A000 FB10
1010AC88H
0000 A000 FB10
1010AC90H
0000 2000 FB10
1010AC98H
1000 2000 FB10
1010ACA0H
0100 AC68 8240
1010ACA8H
0100 AC58 8240
1010ACB0H
0000 C000 FB10
1010ACB8H
0000 0000 0000
1010ACC0H
0000 0000 0000
1010ACC8H
B000 20C0 FB10
9.

+6
A01F
B01F
A01F
A01F
2200
0000
A01F
0000
0000
8A1F

ECE3166- Advanced Microprocessors

Contents (hex)
Linear address +0
+2
+4
2240AC50H
0000 0000 0000
2240AC58H
0000 0000 0000
2240AC60H
0000 0000 0000
2240AC68H
2000 2000 FB10
2240AC70H
0000 0000 0000
2240AC78H
0000 1000 FB10
2240AC80H
0000 0000 0000
2240AC88H
0000 2000 FB10
2240AC90H
0000 0000 0000
2240AC98H
0000 0000 0000

+6
0000
0000
0000
801F
0000
801F
0000
A01F
0000
0000

How large is the 80386DXs virtual address space? What is the

maximum number of segments that can exist in the virtual address
space? What part of the 80386DX is used to translate virtual address to
physical addresses?

10. Into how many pages is the 80386DXs address space mapped when
paging is enabled? What is the size of a page?
11. What are the three elements of the linear address that is produced by
segment translation when paging is enabled? Give the size of each
element. What is the purpose of the translation look aside buffer?
12. Write a short sequence of instructions to (a) clear the task-switched bit
of the machine status word, (b) load the local descriptor table register
with the selector 02F0H from the BX register.
13. A page table entry contains F1000007H. Find out the base address of
the page frame. Also interpret the bits (D, A, U/S, R/W, P).
14. Briefly explain whether the following accesses will cause any protection
violation or not.
a) DS selector register index selects a descriptor whose access rights
byte is 18H.
b) An attempt is made to read an operand from a code segment whose
access rights byte is 1AH.
c) An attempt is made to read a double word with an offset of 1FFDH
from a segment whose LIMIT is 1FFFH.
15. What does CPL stand for? RPL?
16. Is the (80386DX) protection mechanism active in virtual 8086 mode? If
so, what is the privilege level of virtual 8086 program?