MADANAPALLE INSTITUTE OF TECHNOLOGY & SCIENCE

III B.Tech I Semester First Mid-Term Examinations: SEP 2015

LICA (Descriptive Exam)
ECE(A,C,&D)
Date: 11/09/2015 (FN)
Time: 90 min
Max.Marks:30
Answer any three of the following
1. Write short notes on :
(a)Level Translator
(b)What is the voltage at Point A and Point B for the circuit shown in below figure below
if V1= 5V and V2= 5.1V (10M)

2. (a) Write Ideal Characteristics of an op-amp? The CMRR of an op-amp is 10000. Two sets
of signals are applied to it. First set is V1 = +20 V and V2 = 20 V and the second set is
V1= 540 V and V2 = 500 V. Calculate the percentage difference in output voltage for the
two sets of signal. (5M)
(b) Briefly explain why negative feedback is desirable in amplifier applications and derive
the output voltage expression for ideal inverting amplifier (5M)
3. (a) draw the equivalent circuit of an op-amp and discuss about Op-amp stability? (5M)
(b) Define slew rate and derive the expression for it. List the causes of slew rate. (5M)
4. (a) Explain ideal differentiator circuit and obtain output voltage expression? (5M)
(b) Deign an practical differentiator circuit with input signal frequency 5 kHz? Assume
necessary parameters? (5M)
5. (a) Draw the schematic of 3 Op-amp Instrumentation amplifier and derive output voltage
expression?(5M)
(b)Draw the circuit of three input inverting type summing amplifier and derive the
expression for output voltage. (5M)

MADANAPALLE INSTITUTE OF TECHNOLOGY & SCIENCE, MADANAPALLE

III B.Tech I Semester First Mid Term Examinations: SEP 2015
LICA (Objective)
ECE- Section (A,C,&D)
Roll:
Date: 11 /09/2015 (FN)
Time: 20min
Max. Marks: 10
1

In differential amplifier the output is taken between two collectors the it is called
a) Unbalanced output b)Balanced output c) single input d) None of the above

The circuit in which the output current is forced equal to the input current is called as
a) Constant Current Bias method b) cascading of differential amplifiers c) current mirror circuit d) All of the above

The _____________is a multiterminal device which is internally quite complex

(a)FET (b)BJT (c)op-amp (d)none
If Ad=162.068 and Ac=0.3414 then find CMRR___________

a) 53db

b)96db c)20db

d)47db

The two input signals are different from each other then the differential amplifier is worked in__________________
a) Common Mode b) Differential Mode c) Multiplication Mode d) None of these

The value of CMRR is ____________ when the RE is high

(a)low (b)moderate (c) high (d) none

The average value of the two currents flowing into the op-amp input terminals is called
a) Input bias current b) Input offset current c) Input offset voltage d) output offset voltage

PSRR is also called as

a) Output power b) Supply voltage Rejection Ratio c) Power Supply Sensitivity d) Both (b) and (c)

For an ideal op-amp input resistance ______

a)Zero b)Infinite c)unity d) all of the above

10

Most of the linear ICs are based on the two transistor differential amplifier because of its
(a) input voltage dependent linear transfer characteristic(b)high voltage gain
(c) high input resistance (d)high CMRR

11

In 8-pin IC741 the output terminal Pin No:

a)1 b) 4 c) 5 d) 6

The gain for Inverting amplifier is

12

a)

Rf
R1

b)

Rf
1

R1

c)1 d) 0

In voltage follower circuit

13

a) V0

Vin b) V0 Vin

c) V0

Vin

d) V0

Vin

14

The common mode input is the value of the two inputs________

(a) RMS (b) Average (c) Form (d) Peak

15

If a step input is applied to integrator the output response

a)Train of impulses b) Cosine c)Ramp d) sine

16

The typical value of gain nearly__________

(a)103 (b)10 (c)104 (d) 105

17

In open loop configuration, the op-amp works in

(a) Reverse region (b) Saturation region (c) Cut-off region (d) Linear region

18

PSRR of an op-amp should be_______________

a)zero b)infinite c)high d)none

19

If the differential and common mode gains of differential amplifier are 50 and 0.2,then the C MRR will be
(a)10
(b) 49.8 (c) 50.2 (d) 250

20

The voltage that appears at the output of an op-amp even when the differential input voltage is zero
(a)input offset voltage (b)output offset voltage (c)both (d)none