IJIRST International Journal for Innovative Research in Science & Technology| Volume 2 | Issue 1 | June 2015

ISSN (online): 2349-6010

Layout Design of CMOS Buffer to Reduce Area

and Power
Mohd. Shariq Mahoob
M. Tech Scholar
Department of Electronics & Communication Engineering
National Institute of Technical Teachers Training &
Research Chandigarh, UT, India

Rajesh Mehra
Associate Professor
Department of Electronics & Communication Engineering
National Institute of Technical Teachers Training & Research
Chandigarh, UT, India

Abstract
High speed digital Input buffer circuits are used in a wide variety of digital applications. A very common application of these
input buffers is in memory devices. Memory circuits needs clean and full level digital data in the memory array. The digital data
traveling through various digital circuitries gets distorted by adding delays in the signals like low voltage signal levels, slow fall
and rise times, etc. The buffer circuits take these input signals with imperfections and convert them in to full digital logic levels
by slicing the data signals at correct levels which depends upon the switching point voltage. In this paper layout of CMOS
buffer is drawn; first one is auto-generated and second one is semi-custom layout. Then a comparison of various properties of the
two layouts is done.
Keywords: Buffer, CMOS technology, Leakage Power, Threshold Voltage, VLSI
_______________________________________________________________________________________________________

I. INTRODUCTION
The VLSI system designer has shown keen interest in low power and less surface area for designing of digital circuit in recent
past and trend still continues. The above basic requirement has not been fulfilled by the conventional complementary metal oxide
semiconductor (CMOS) gates; hence remedy to this problem has been effectively given by the transmission gate, which gave
better result in the field of power and surface area. The high intensity research effort in low power microelectronics is due to
vigorous development in the field of portable system and cellular network [1].
Heat dissipation and power consumption are major problems in VLSI implementation. The solution to this problem lies in the
reduction of power supply voltage, switching frequency and capacitance of transistors [3]. The strength of a signal is measured
by how closely it approximates an ideal voltage source [2]. Leakage current is of primary concern for low-power, highperformance digital CMOS circuits. The exponential increase in the leakage component of the total chip power can be attributed
to threshold voltage scaling, which is essential to maintain high performance in active mode, since supply voltages are scaled.
Numerous design techniques have been proposed to reduce standby leakage in digital circuits. Leakage power has become a
serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a
small penalty in performance [3]. Logic gates are an essential part of modern digital circuits which are implemented in the
complementary metal oxide semiconductor (CMOS) technology. Dynamic Power and Leakage power are the two components of
power consumption [4].The main contributors to the total power consumption are dynamic and leakage power. Switching power
and short circuit power are essential part of dynamic power. CMOS logic in combination with spurious transition, also known as
glitches are unnecessary power dissipation well known source. The highly desirable target is reducing glitch power. [5]

II. CMOS BUFFER

High speed input signals travel through the various digital circuits and gets distorted when it proceed towards the chip i.e. the
digital data traveling through various digital circuitry gets distorted by adding delays in the signals like low voltage signal levels,
slow rise and fall times, etc. Input buffers circuits are present at a chips input and convert input signals with these. undesirable
features in to clean, full logic level digital signals for use inside the chip by slicing the data signals at correct levels which
depends upon the switching point voltage. The switching point voltage is defined as the voltage at which the input and the
output transitions from logic high to logic low or vice versa. If the switching point is very high, the output data has appropriate
low noise margin and if the switching point is very low, the output data has high noise margin. If the input signal is triangle wave
with slow rise and fall times the bits at the output of the buffer will have variations in the pulse width transitioning either too fast
or too slow [6]. Input buffer circuits are used in a wide variety of digital applications. One of the common applications of the
input buffers is in the memory devices. Generally input buffers employing differential amplifiers couple the data signals between
the input terminals and the main memory array. If the buffer doesnt segment the data at the correct instant of time, timing errors
can take place i.e., the bits of data at the output of the buffer gets distorted. If the input signal is sliced too high or low, the output

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Layout Design of CMOS Buffer to Reduce Area and Power

(IJIRST/ Volume 2 / Issue 1 / 003)

signals width is incorrect. This can be depicted in the figure 1.1 shown below. Typically these input buffers are used after the
ESD protection circuit [7].
Many techniques have been employed to reduce power dissipation in VLSI circuits and lowering the supply voltage V DD is the
most effective to decrease the power dissipation, since CMOS power quadrically depends on V DD. However low VDD requires
low threshold voltage Vth, but then the sub-threshold leakage power increases exponentially. Hence there is a great necessity to
optimize Vth to achieve the required performance at minimum power dissipation [8].

III. LAYOUT DESIGN

Fig.1. shows the block diagram of buffer circuit. In this block diagram two PMOS and two NMOS have been used.

Fig. 1: Block diagram of buffer circuit

Fig.2 indicates the layout of buffer circuit of auto-generated using DSCH and Microwind tool. In Fig.3 semi-custom design of
buffer circuit has been shown using lambda rule.

Fig. 2: Auto-generated layout of buffer circuit

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Layout Design of CMOS Buffer to Reduce Area and Power

(IJIRST/ Volume 2 / Issue 1 / 003)

Fig. 3: Semi-custom layout of buffer circuit

IV. SIMULATION RESULTS

Fig.4 and fig.5 indicate the timing diagram (Voltage vs Voltage) and hysteresis output of buffer circuit.

Fig. 4: Timing Diagram of buffer circuit

Fig. 5: Hysteresis curve of buffer circuit

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Layout Design of CMOS Buffer to Reduce Area and Power

(IJIRST/ Volume 2 / Issue 1 / 003)

Table 1:
Comparison of different layout
Parameter

Auto-generated

Semicustom Design

Area
Power

28.5 m2
4.217 W

17.9 m2
4.184 W

V. CONCLUSION
Thus we see that there is a great reduction in area and power of layout is obtained in case of semicustom layout design. Also the
power consumption of auto-generated layout is more as compare to semicustom layout design. Surface area of Auto-generated
layout of buffer circuit is 28.5 m2 and surface area of semi custom design of buffer circuit is 17.9 m2. The power consumed
by auto-generated layout and semi custom layout is 4.217 W and 4.184 W respectively.

ACKNOWLEDGEMENTS
The authors would also like to thank Director, National Institute of Technical Teachers Training & Research, Chandigarh, India
for their constant inspirations and support throughout this research work.

REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]

Saradindu Panda, A.banerjee, B.maji and Dr. A.K. Mukhopadhyay, Power and delay comparison in between different types of full adder circuits,
International Journal of advanced research in electrical, electronics and instrumentation engineering, volume 1, issue 3.pp.168-172, 2012.
Neil H.E.Weste, David Harris and Ayan Banaerjee, CMOS VLSI design. Pearson Education,Inc., pp. 11, Third Edition, 2005.
AshokaSanthanur, Luca Benini, RowBased Power Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in
Nanometer CMOS Circuits, IEEE Transactions on VLSI Systems, Vol. 19, Issue: 3, pp. 469-482, March 2011.
Anup K. Sultania, Dennis Sylvester, and Sachin S. Sapatnekar, Gate Oxide Leakage and Delay Tradeoffs for Dual-Tox Circuits, IEEE Transactions on
Very Large Scale Integration (VLSI) systems, Vol. 13, Issue: 12, pp. 1362-1375, December 2005.
SarveshBhardwaj and SarmaVrudhula, Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue: 3, pp. 445-455, March 2008.
R. Jacob Baker, CMOS Circuit Design, Layout and Simulation, 2nded. Boise, ID:Wiley-IEEE, 2005.
R. Jacob Baker, Harry W. Li and David E. Boyce, CMOS Circuit Design, Layout and Simulation, John Wiley and Sons publishers, ISBN-81-203-1682-7.
Tadahiro Kuroda Optimization and control of VDD and VTH for low-power, high-speed CMOS design, in Proceedings of IEEE/ACM international
conference on Computer-aided design San Jose, California, Page(s): 28 - 34 ,2002.

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