Beruflich Dokumente
Kultur Dokumente
VLSI
M.Tech/M.E IEEE Project List 2015-16
Nanocdac, 08297578555, info@nsrcnano.com
CODE
PROJECT TITLE
NVD-01
2015
NVD-03
NVD-04
2015
NVD-05
2015
NVD-08
NVD-09
2015
NVD-10
2015
NVD-11
NVD-12
2015
NVD-13
2014(T)
NVD-16
2014(T)
NVD-17
2014(T)
NVD-18
2014(T)
NVD-19
2014(T)
NVD-02
NVD-06
NVD-07
NVD-14
NVD-15
NVD-20
NVD-21
YEAR
2015
2015
2015
2015
2015
2015
2014(T)
2014(T)
2014(T)
2014
NVD-22
2014
NVD-23
2014
NVD-24
2013(T)
NVD-25
2013(T)
NVD-26
2013(T)
NVD-27
2013(T)
2013
2013
NVD-28
NVD-29
NVD-30
NVD-31
NVD-32
NVD-33
NVD-34
NVD-35
2013
2013
2013
2013
2013(T)
2013(T)
2013
NVD-40
NVD-41
2013
NVD-42
2013
NVD-36
NVD-37
NVD-38
NVD-39
NVD-43
2013(T)
2013
2013
2013
2013
NVD-44
2013
NVD-45
2013
NVD-46
NVD-47
2013
NVD-48
2012(T)
NVD-49
2012(T)
NVD-50
2012(T)
2012(T)
NVD-51
NVD-52
NVD-53
NVD-54
2013
2012(T)
2012
2012
2015(T)
NVL-02
2015(T)
NVL-04
2015(T)
NVL-05
2015(T)
NVL-06
2015(T)
NVL-07
2015
NVL-08
An Efficient Design Technique for Low Power Dynamic Feed through Logic
with Enhanced Performance for wide fan-in gates
2015
NVL-03
2015(T)
NVL-09
2015
NVL-10
2015
NVL-11
2015
NVL-12
Design of high speed ternary full adder and three input XOR circuits using
CNTFETs
2015
NVL-13
2015
NVL-14
2015
NVL-15
NVL-16
NVL-17
NVL-18
NVL-19
NVL-20
NVL-21
NVL-22
NVL-23
NVL-24
NVL-25
NVL-26
NVL-27
Cadence2015
Cadence2015
Cadence2015
Cadence2015
2014(T)
2014(T)
2014(T)
2014(T)
2014(T)
2014(T)
2014
2014(T)
2013(T)