16 Bit SRAM Implementation and Analysis

Project
by

Aamodh K , Arjun S Kumar and Vikas Bhardwaj

(M.Tech VLSI Design)

What Is Our Project All About

Figure: Image Source : Intel

Why SRAM Based Project

Reason 1 : Innovation in SRAM is still in vogue in industry

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December 2013: Taiwan Semiconductor Manufacturing

Company (TSMC) unveil SRAM cell of size 0.07 um2 in 16nm
technology.[1]
February 2015: Intel respond by unveiling worlds smallest (
cell size of 0.05 um2) SRAM till date in 14nm technology,
capable of storing 14.5Mb per mm2 [2]
Intel and TSMC plan to unveil FinFET SRAM at 10nm
technology in 2016. [3]

Why SRAM Based Project

Reason 2 : It is interesting to learn about a part of a product

we use very often.
Applications of SRAM:
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Cache memory on processors

Registers
LCD TVs [4]
Printer [5]

Project Agenda

Design of 16 Bit 6T SRAM Cell

Design of peripheral circuitry Decoder, Sense Amplifier,

Pre-charge circuit, Write enable circuitry

Simulation and Testing of 16 bit SRAM at circuit and layout

level
Characterization of 6T SRAM Cell based on

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Static Noise Margin

Read and Write Delay
Static Power Dissipation

Block diagram of 16 bit SRAM

Schematic of 1 bit 6T SRAM

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Design details to take care of:

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Cell Ratio (CR)

Pull-up Ratio (PR)

Why worry about cell ratio and pullup ratio

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To prevent destructive read

Need Of Peripheral Circuitry

Sense Amplifier
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To nullify the negative effect of parasitic bit and word line

capacitances.
To increase the logic detection speed during read operation.

Need Of Peripheral Circuitry

Decoder
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To select a particular SRAM cell among the array of 16 SRAM

cells
Pseudo NMOS logic 2-to-4 NOR decoder to be used.
Reason for choosing NOR decoder over NAND decoder: NOR
decoder consumes lesser power.

Need Of Peripheral Circuitry

Pre charge circuit:

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To prevent unwanted toggling of cell state by maintaining

preset voltage on bit lines.

Need Of Peripheral Circuitry

Data enable circuit

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To control the data write operation.

Perfomance Parameters

Static Noise Margin (SNM):

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SNM of SRAM is defined as minimum amount of noise voltage

on the storing nodes of SRAM required to flip the state of cell.
How do we plan to measure SNM? Using NGSpice and Perl
scripting.

Measuring SNM

Figure: SNM original plot from [6]

Perfomance Parameters

Write delay
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Read delay
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Delay in writing data into the cell

Delay in reading data out of the cell

Static Power Dissipation

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Power dissipation in Hold state of the cell

Resources To Be Used

For circuit simulation: NgSpice,IRSim

For layout design: Magic

For Layout Versus Schematic: Netgen

For calculation of Read and Write delay: Perl/Python

Timeline

Circuit diagram

SRAM cell design

SRAM cell design :

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For Vdd=3.3V and mobility and threshold voltage values in

level 49 ngspice model
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Cell Ratio>4.051 (selected value: 4.2)

Pullup Ratio<0.481 (selected value: 0.4)

Plots Obtained

Layout

References
1. Intel vs. TSMC: An Update
http :
//electroiq.com/blog /2014/01/intel vs tsmc anupdate
2. Intel Carves Tiny SRAMs at 14nm
http : //www .eetimes.com/document.asp?doci d = 1325734
3. TSMC Outlines 16nm, 10nm Plans
http : //www .eetimes.com/document.asp?doci d = 1326286

4. http : //www .st.com/st web

ui/static/active/en/resource/technical/document/applicationn ote/C
5. http : //www .memoryx.com/troyajn.html
6. E. Seevinck, F. List, and J. Lohstroh, Static-noise margin
analysis of mos sram cells Solid-State Circuits, IEEE Journal
of,, vol. 22, no. 5, pp. 748 754, Oct. 1987.