Module Code: 14ELEC05H

Module Title: VLSI Technology

Module Leader: Dr. Hassan Mostafa

Semester : ONE

Total mark : 100

Instructions:
1. Answer all questions.
2. The exam consists of 2 questions in Four pages including this cover page.
3. A formula sheet is attached at end of this booklet.
4. The exam allowed time is ONE hour.
5. Electronic calculators are allowed.
6. Clearly show all steps used in your solutions.
7. The allocation of marks is shown in brackets next to each question.
8. This is a closed book exam.

Question

Q1

Q2

Total Mark

50

50

100

Mark
Out of

Q1. Given

the following logic expression, answer the following questions:

= (A.B) + (A.C.E)
I.

Implement the above logic expression using static CMOS logic. You
should use the minimum number of transistors. What is the number of
transistors you have used in your design?

[10 marks]

II.

Size the NMOS and PMOS devices such that the output resistance is the
same as that of an inverter with an NMOS W/L = 2 and PMOS W/L =3 .

[6 marks]

III.

What are the input patterns that results in the worst case LOW-to-HIGH
and HIGH-to-LOW propagation delay times?

[4 marks]

IV.

Calculate the worst case LOW-to-HIGH and HIGH-to-LOW propagation

delay times.

[8 marks]

V.

What are the input patterns that results in the best case LOW-to-HIGH
and HIGH-to-LOW propagation delay times?

[4 marks]

VI.

Calculate the best case LOW-to-HIGH and HIGH-to-LOW propagation

delay times.

[8 marks]

VII.

Draw a stick diagram for the above CMOS transistor network and
estimate the layout area.

[10 marks]
[Total 50]

Hint: Calculate the delays in terms of the output capacitance CL, and the equivalent inverter resistances RN and RP.

Q2. Consider the following circuit driving a capacitive load of 1pF. Given that Vtn = |Vtp| = 0.6V, kn' = 3kp' =
115A/V2.

I.

Assume that the input In swings from rail to rail (i.e., 0 to 2.5V), what is
the swing on the output node out?

[4 marks]

II.

At the switching threshold VM = 1.75V, what is the mode of operation of

M1 and M2? Justify your answer.

[7 marks]

III.

Assuming (W/L)M1 = 4, find (W/L)M2 such that VM = 1.75V.

[8 marks]

IV.

Using the sizing in part III. above, find the LOW-to-HIGH and the
HIGH-to-LOW propagation delays.

[8 marks]

V.

Assume that the input switches at a clock frequency of 10MHz with a

swing from 0 to VDD and zero rise/fall times, Calculate the average static
and dynamic power dissipation.

[7 marks]

VI.

What is the maximum switching frequency allowed for the input signal?

[5 marks]

VII.

Calculate the static and dynamic power dissipation at this maximum

frequency.

[5 marks]

VIII. What are the advantages/disadvantages of adding the Vlow = 1V between

the source of the NMOS transistor and the ground? Justify your answers.

[6 marks]
[Total 50]

Formula sheet:
-------------------You may make use of the following formulas--------------------

MOSFET UNIFIED MODEL:

50% propagation delay = 0.69 RC

RN = (kn*W/L*(VGS-Vt))-1