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### Solution ECE-438, MOS Transistor

Chapter 3, Digital Integrated Circuits, J. M. Rabaey, 2 nd Edition

1) Given the data in the table below for a short channel NMOS transistor with

V DSAT =0.6V and k =100 A/V 2 , calculate V T0 , , , 2 f and W/L.

V

GS

V

DS

V

BS

I

D ( A)

1

2.5

1.8

0

1812

2

2

1.8

0

1297

3

2

2.5

0

1361

4

2

1.8

-1

1146

5

2

1.8

-2

1039

For Short-Channel device:

2

I

D

k

W

L

(

VV

min

GS

V

T

)

V

min

2

(1

V

DS

)

,

where V min = min(V GS -V T , V DS , V DSAT ).

To begin with: the operation regions need to be determined.

For any of these data to be in saturation:

V T should be: V GS – V T > V DSAT

2- V T > 0.6 => 1.4

> V T

This is a quite high value in our process. Thus, we can assume that all data are taken in

velocity saturation. We will check this assumption later.

I

In Velocity Sat.:

D

k

W

V

DSAT

(

V

GS

V

T

V

DSAT

)(1

V

DS

)

Eq.1

L

2

V DSAT and V DS are constant in 1 & 2 =>

V

V

T

V

DSAT

I

GS

1

D

1

2

=>

I

D

2

V

V

V

DSAT

GS

2

T

2

1812

2.5

V

T

0.3

=> V T0 = 0.44V

1297

2

V

T

0.3

Page:

1

In 2 & 3 V DSAT and V GS are constant =>

 1297 1 1.8 1361 1 2.5

0.08 V

1

 Using data 2 & 4: V T = 0.587 V (1) Using data 2 & 5: V T = 0.691 V (2)

Both these values satisfy V T < 1.4 V so all the data in our table were taken in velocity

saturation.

• V T

V

T

• 0 2
2
V
SB
F
F

(1) and (2) can be used along with V T0 = 0.44 V to conclude:

0.29 V 2
1

and 2

also using 2 nd set of data

I D = 1297 A and Eq.1 => F
W
0.6
15

L

V

2) An NMOS device is plugged into the test configuration shown below in Figure P1.

The input V in =2V and the current source draws a constant current of 50 A. R is a

variable resistor that can assume values between 10k and 30k . Transistor M 1

experiences short channel effects and has following transistor parameters:

k =110 10 -6 V/A 2 , V T =0.4 and V DSAT =0.6V. The transistor has a W/L=2.5/0.25. For

simplicity, body effect and channel length modulation can be neglected.

• a) When R=10k find the operation region, V D and V S .

• b) When R=30k again determine the operation region, V D and V S .

Figure P1

Page:

2  (a) R=10 K
therefore V D 2.5 10 0.05 2
V
we can assume transistor is in SAT.
k
W
I
V
V
2
D
GS
T
2
L
6
110
10
2.5
6
50
10
2
V
0.4
2
S
2
0.25
Therefore,
V
1.3
V.
S
As
V
V
0.3
,
V
0.7
and
V
0.6
, our assumption is correct and the
GS
T
DS
DSAT
device is in saturation region.
(b)
R 30 K therefore V
2.5 30 0.05 1
V
D
It is obvious that in this case the transistor is not in velocity saturation (because
V
S
Would be 1.22 which is greater than
V
) .
D
Assuming the device is in linear region
2
W
V
DS
I
k
VV
(
V
)
D
DS
GS
T
L
2
2
1
V
6
6
S
50 10
110 10
10(1
V
)(2
V
0.9
)
S
S
2
V
0.93
S
To check our assumption:
V
2 0.93 1.07
GS
V
0.07
DS
So our first assumption is correct and
V
0.93
S
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3

3) Consider the circuit shown in Figure P2.

 a) Write down the equations (and only those) which are needed to determine the voltage at node X. Do NOT plug in any values yet. Neglect short channel effects and assume that p = 0. b) Draw the (approximate) load lines for both PMOS transistor and resistor. Mark some of the significant points. c) Determine the required width of the transistor (for L = 0.25µm) such that X equals 1.5 V. d) We have, so far, assumed that M1 is a long-channel device. Redraw the load lines Assuming that M1(PMOS) is velocity-saturated. Will the voltage at X rise or fall?

(Use Table 3-2, Page 103) Figure P2

PMOS is always in Saturation. V
2 L
W
b)
a)
k
Tp
V
2 2.5 V
X
p
=2.5/20k=125uA
VDD/R
c)
X
1
x
VSD, VX
R
W
1.5 0.4
6
2
30 10
L
2
k
20

Page:

4 Voltage at node X would go up since the current drive of PMOS is lower.
W/L = 2.755 , W = 0.69 m
VSD, VX
d)

4) The circuit of Figure P3 is known as a source-follower configuration. It achieves a DC

level shift between the input and output. The value of this shift is determined by the

current I 0 . Assume device is in saturation = 0.4, 2| f | = 0.6 V, V T0 = 0.43 V, k = 115

µA/V 2 , and = 0. The NMOS device has W/L = 5.4µ/1.2µ such that the short channel

effects are not observed.

• a) Derive an expression giving V i as a function of V o and V T (V o ). If we neglect

body effect, what is the nominal value of the level shift performed by this circuit?

• b) The NMOS transistor experiences a shift in V T due to the body effect. Find V T

as a function of V o for V o ranging from 0 to 1.5V with 0.25 V intervals. Plot V T vs.

• V o .

• c) Plot V o vs. V i as V o varies from 0 to 1.5 V with 0.25 V intervals. Plot two

curves: one neglecting the body effect and one accounting for it. How does the

body-effect influence the operation of the level converter? At V o (body effect) =

1.5 V, find V o (ideal) and, thus, determine the maximum error introduced by body

effect. Figure P2

Page:

5 k W
n
2
a)
I
(
VV V
)
D
iot
2
L
2
I
D
VV V
W
ioT
k
n
L
Neglecting body effect V T =V T0
2
I
D
V
VV
i
W
o
T0
k
n
L
2
I
D
Level Shift
V
W
t
0
k
n
L
LS = 0.8V
b)
V
V
2
V
2
T
T
0
F
SB
F
V
0.43 0.4
V
0.6
0.6
T
o
Page:
6

c)

VV

oi L
k
W
I
n
D
2

V

t

o

Plot Vi versus Vo for two different cases:

1) V T = V T0 (neglecting body effect, γ=0)

If body effect is neglected, Vi=Vo+constant (linear relation)

Vo=1.5 V ==> Vi=2.3V

2) V T = V T (V o ) (accounting for body effect, γ=0.4)

Vo=1.5V ==> Vi=2.57 V

Maximum error due to body effect=2.57-2.3=0.27 V. Page:
7

5) The curves below in Figure P4 represent the gate voltage (V GS ) vs. drain current (I DS )

of two NMOS devices, which are on the same die and operate in sub-threshold region.

Due to process variations on the same die the curves do not overlap.

Also assume that the transistors are within the same circuit configurations as Figure P5 in

If the input voltages are both V in = 0.2V. What would be the respective durations to

discharge the load of C L = 1pF attached to the drains of these devices.

(Assume voltage charge for C L is 1V)  Figure P4
Figure P5

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8

 V in = 0.2 Or V in = 0.2 t C V I t 1 1 pF 1 x 10 3 8 t 2 1 pF 1 x 10 9 5

I DS = 3 e–8 A (1)

I DS = 5 e–9 A (2)

 33.3 s 200 s

6) Compute the gate and diffusion capacitances for transistor M1 of Figure P6.

Assume that drain and source areas are rectangular, and are 1 µm wide and 0.25 µm long.

0.5

Use the parameters of Example 3.5 to determine the capacitance values. Assume m j = 0.5

and m jsw = 0.44. Also compute the total charge stored at input node, for the following

initial conditions:

• a) V in

= 2.5 V, V out = 2.5 V, 0.5 V, and 0 V.

• b) V in = 0 V, V out = 2.5 V, 0.5 V, and 0 V. Figure P6

Page:

9

Cox = 6 fF/ m 2 , MOS dimensions L = 0.25 m and W = 1 m

 Cut-off : C g = C ox. WL + 2C o. W Linear : C g = C ox. WL + 2C o. W

Sat-Vel.Sat: C g = 0.66C ox. WL + 2C o. W

Diffusion Cap (C d )

NOTE: Ldrain=0.5um (drain length) is not L for the MOSFET P
D
)
jsw
(2
L W
Drain Perimeter=W+2Ldrain
Cd=Cj*Area+Cjsw*perimeter

Drain Area=W*Ldrain

CLW

j D

C

C

C

C

D

d

0

j

j

1

m

mj

DS

V

D

0

j

C

jsw

C

0

1

jsw

DS

V

D

### -

0  m
jsw
mjsw
 a) C g C d = 0.827 fF V out = 0.5 V C g C d = 1.263 fF V out = 0 V C g C d = 1.56 fF b)

V in = 2.5V,

V out = 2.5V Vel. Saturation.

= 1.62 fF , Q = 4.05 fC = 4.05 e –15 C

Linear Reg.

= 2.12 fF , Q = 5.3 fC

Linear Reg.

= 2.12 fF , Q = 5.3 fC

V in = 0V => Cut off

Regardless of V DS

C g = C ox. WL

C g = 2.12 fF, Q =0

And C d s are the same as Part a.

 V in = 2.5V => C d = 0.827 fF V out = 0.5 V => C d = 1.263 fF V out = 0 V => C d = 1.56 fF

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