WARRIOR-JNTU

http://WARRIOR-JNTU.blogspot.com
JNTU ONLINE EXAMINATIONS [Mid 2 - DICA]

1. ABCD are four naturally BCD digits, the Boolean expression for combinational logic
circuit which detect the input digits divisible by 3 is [01D01]
a)
b)
c)
d)
2. The Boolean expression for output IDLE of generic 8 input priority encoder in terms of I0
to I7 is [01D02]
a) (I_0 + I_1+ I_2+ I_3 + I_4 + I_5+ I_6+ I_7)1
b)
c)
d) (I_0 + I_1+ I_2+I_3+I_5+I_6+I_7)1
3. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then S is
[01M01]
a)
b)
c)
d)
4. _ _ _ _ _ _ has extra inverters on its select inputs [01M02]
a) 74X139
b) 74X130
c) 74X129
d) 74X119
5. For 74X139 dual 2 to 4 decoder,011 input gives _ _ _ _ _ _ output. [01M03]
a) 0111
b) 1011
c) 1111
d) 1100
6. One of the following is dual 2 to 4 decoder [01S01]
a) 74LS139
b) 74X130
c) 74X129
d) 74X119
7. _ _ _ _ _ _ contains two independent or identical 2 to 4 decoders [01S02]
a) 74X139
b) 74X130
c) 74X129
d) 74X119
8. For _ _ _ _ _ _ , the outputs and enable input are active low. [01S03]
a) 74X139

ORKUT COMMUNITY

WARRIOR-JNTU
b) 74X130
c) 74X129
d) 74X119
9. One of the following is 3 to 8 decoder [01S04]
a) 74X138
b) 74X130
c) 74X119
d) 74X36
10. 74 X 138 has [01S05]
a) three enable inputs
b) two enable inputs
c) four enable inputs
d) one enable input
11. 10011 input in seven segment decodes as _ _ _ _ _ _ _ _ _ output. [02D01]
a) 1111001
b) 1111101
c) 1011001
d) 1111000
12. If G1,G2A,G2B are enable inputs, C,B,A are inputs, then output Y 5 in terms of enable &
input signal for 3 to 8 decoder is [02D02]
a) G1. G2A. G2B.C.B.
b) G2A. G2B.C.B.
c) G1. G2A. G2B.C.B1
d) G1. G2A. G2B.B.
13. For 74 X 138, 3 to 8 decoder 100000 input gives [02M01]
a) 11111110
b) 11111100
c) 11011110
d) 10111110
14. If I0 to I7 are inputs and Y0 to Y2 are outputs of 8 to 3 encoder, then Y2 in terms of inputs
is [02M02]
a)
b)
c)
d)
15. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then Q is [02S01]
a)
b)
c)
d)
16. A seven segment decoder has _ _ _ _ _ _ _ _ as its input code [02S02]
a) 4 bit BCD
b) 6 bit excess 3
c) 3 bit octal
d) 3 bit hex
17. _ _ _ _ _ _ _ _ is seven segment decoder [02S03]

ORKUT COMMUNITY

WARRIOR-JNTU
a) 74X49
b) 74X138
c) 74X491
d) 74X149
18. Blanking input in 74X49 is [02S04]
a) Bi _ L
b) Bi _ H
c) B _ L
d) Bi _ U
19. 10111 input gives _ _ _ _ _ _ _ _ _ _ _ output in seven segment decoder [02S05]
a) 1110000
b) 1110001
c) 1110010
d) 1100000
20. The 1 out of 2n coded outputs of n bit binary decoder used to control a set of [02S06]
a) 2n devices
b)
devices
c)
devices
d) 2 n devices
21. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then T is [03D01]
a)
b)
c)
d)
22. 001111111 input produce _ _ _ _ _ _ _ _ in 74 X 148, 8 bit priority encoder. [03D02]
a) 11101
b) 11001
c) 10101
d) 11100
23. The Boolean expression for output A0 of generic 8 input priority encoder in terms of
intermediate variable H0 to H7 is [03M01]
a)
b)
c)
d)
24. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then P is
[03M02]
a)
b)
c)
d)
25. The Boolean expression for output A2 of generic 8 input priority encoder in terms of
intermediate variables H0 to H7 is [03M03]
a)
b)
c)

ORKUT COMMUNITY

WARRIOR-JNTU
d)
26. 0XX011111 gives _ _ _ _ _ _ _ _ output in priority encoder [03M04]
a) 10101
b) 00101
c) 10001
d) 10100
27. The IDLE output in generic 8 input priority encoder is asserted if _ _ _ _ _ are asserted.
[03S01]
a) no inputs
b) I1, I4
c) I2,I6
d) I4,I5
28. _ _ _ _ _ _ _ _ is a priority encoder [03S02]
a) 74 X 148
b) 74 X 146
c) 74 X 48
d) 74 X 144
29. 74 X 148 inputs are [03S03]
a) active low
b) active high
c) inverted
d) buffered & inverted
30. 74 X 148 outputs are [03S04]
a) active low
b) active high
c) buffered
d) inverted
31. _ _ _ _ _ _ _ must be asserted for any of its output to be asserted in 74 X 148 [04D01]
a) EI _ L
b) EO _ H
c) EO _ L
d) EI _ H
32. Shown in figure (a) represents

Figure(a)
[04M01]
a) Inverting active low enable buffer
b) Inverting active high enable buffer
c) non Inverting active low enable buffer
d) non Inverting active high enable buffer
33. Shown in figure (a) represents

ORKUT COMMUNITY

WARRIOR-JNTU

Figure(a)
[04M02]
a) Non - inverting active high enable buffer
b) inverting active low enable buffer
c) non Inverting active low enable buffer
d) Inverting active high enable buffer
34. Shown in figure (a) represents

Figure(a)
[04M03]
a) Non - inverting active low enable buffer
b) inverting active low enable buffer
c) non Inverting active high enable buffer
d) Inverting active high enable buffer
35. Shown in figure (a) represents

Figure(a)
[04M04]
a) Inverting active high enable buffer
b) Non - inverting active low enable buffer
c) inverting active low enable buffer
d) Non - inverting active high enable buffer
36. EO _ L signal is an enable output designed to be connected to _ _ _ _ _ _ _ _ _ input of
another 74 X148. [04S01]
a) EI L
b) EO H
c) EO L
d) EI H

ORKUT COMMUNITY

WARRIOR-JNTU
37. _ _ _ _ _ _ _ _ _ _ is asserted when the device is enabled in 74 X 148. [04S02]
a) GS L
b) GO H
c) GO L
d) GS H
38. _ _ _ _ _ _ _ _ _ used to describe prioritization in VHDL. [04S03]
a) if then else
b) port
c) assert
d) while
39. The purpose of conv _ std _ logic _ vector (j, n) in VHDL coding of 74 X 148, 8 input
priority encoder is to convert integer j to [04S04]
a) std logic vector
b) std logic
c) real
d) std ulogic
40. _ _ _ _ _ _ _ _ is enable input in 74 X 148 [04S05]
a) EI L
b) EI1 L
c) EI1 H
d) EI H
41. In 74 X 245, if G=0 and dir = 0 indicate [05D01]
a) transfer data from a source on bus B to a destination bus A
b) transfer data from a source on bus A to a destination bus B
c) transfer data independently
d) trans receive depending on chip enable
42. _ _ _ _ _ _ _ _ must be asserted to enable devices three state outputs in three state buffer
[05M01]
a) G1 L, G2 L
b) G2 H, G3 L
c) G1 L, G3 H
d) G1 H, G3 L
43. 74 X 541 input has _ _ _ _ _ _ of hysteris [05M02]
a) 0.4 V
b) 0.6V
c) 0.8V
d) 0.3V
44. _ _ _ _ _ _ _ _ _ _ contains four independent Non - inverting three state buffer. [05S01]
a) 74 X 126
b) 74 X 120
c) 74 X 129
d) 74 X 136
45. _ _ _ _ _ _ _ _ _ _ contains four independent Non - inverting three state buffer. [05S02]
a) 74 X 125
b) 74 X 135
c) 74 X 146

ORKUT COMMUNITY

WARRIOR-JNTU
d) 74 X 136
46. _ _ _ _ _ _ _ _ _ _ is octal Non - inverting three state buffer [05S03]
a) 74 X 541
b) 74 X 546
c) 74 X 451
d) 74 X 544
47. number of don't care inputs in a BCD adder (consider 9 inputs BCD adder) is [05S04]
a) 312
b) 214
c) 412
d) 300
48. _ _ _ _ _ _ _ _ _ is octal three state Trans receiver [05S05]
a) 74 X 245
b) 74 X 254
c) 74 X 243
d) 74 X 241
49. _ _ _ _ _ _ _ _ _ _ _ contains inverting buffer [05S06]
a) 74540
b) 74542
c) 74543
d) 74504
50. _ _ _ _ _ _ _ _ _ in 74 X 245 determines direction of transfer [05S07]
a) dir
b) G1 L
c) G2 L
d) G L
51. General logic equation for multiplexer output: I y is [06D01]
a)
b)
c)
d)
52. In 74 X 245, if G=0 and dir = 1 indicate [06M01]
a) transfer data from a source on bus A to a destination bus B
b) transfer data from a source on bus B to a destination bus A
c) transfer data independently
d) trans receive independently depending Al also
53. In 74X245 , if G=1 and dir = X indicate [06M02]
a) transfers data on busses A & B independently
b) transfer data from a source on bus A to a destination bus B
c) transfer data from a source on bus B to a destination bus
d) trans receive independently A or B
54. If _ _ _ _ _ _ _ _ _ _ _ is asserted, then three state buffer for selected direction is enabled
in 74 X 245 [06S01]

ORKUT COMMUNITY

WARRIOR-JNTU
a) G L
b) G1 L
c) G2 L
d) dir
55. _ _ _ _ _ _ _ _ _ used between two bi-directional busses [06S02]
a) 74 X 245
b) 74 X 541
c) 74 X 151
d) 74 X 148
56. _ _ _ _ _ _ _ _ _ _ contains pairs of three state buffers connected in opposite directions
between each pair of pins, so data can be transferred in either direction. [06S03]
a) bus trans receiver
b) asynchronous bus receiver
c) synchronous bus transmitter
d) programmable interface
57. _ _ _ _ _ _ _ _ _ _ _ is a 8 input 1 bit multiplexer [06S04]
a) 74 X 151
b) 74 X 541
c) 74 X 155
d) 74 X 148
58. For 74 X 151, input 0001 produces [06S05]
a) D1 & D11
b) D1 & D21
c) D5 & D51
d) D5 & D61
59. For 74 X 151, input 0101 produces [06S06]
a) D5 & D51
b) D1 & D11
c) D5 & D61
d) D1 & D21
60. _ _ _ _ _ _ _ _ _ _ _ is 2 input, 4 bit multiplexer. [06S07]
a) 74 X 157
b) 74 X 541
c) 74 X 155
d) 74 X 148
61. The square of three bit binary number
is represented as PQRSTU. Then Boolean
expression for R is [07D01]
a)
b)
c)
d)
62. The square of three bit binary number
is represented as PQRSTU. Then Boolean
expression for Q is [07D02]
a)
b)
)
c)

ORKUT COMMUNITY

WARRIOR-JNTU
d)
)
63. Three state outputs in multiplexer useful when [07M01]
a) n input multiplexers are combined to form larger multiplexer.
b) n -1 input multiplexers are combined to form larger multiplexer
c) n input multiplexers are combined to form larger demultiplexer
d) n -1 input multiplexers are combined to form larger demultiplexer
64. 32 input, 1 bit multiplexer contains [07M02]
a) 74 X 139, four 74 X 151
b) 74 X 136, two 74 X 151
c) 74 X 131, four 74 X 155
d) 74 X 130, four 74 X 159
65. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then R is
[07M03]
a)
b) AD + CD + BC1
c)
d)
66. ABCD are four naturally BCD digits, the Boolean expression for combinational logic
circuit which detect numbers that are greater than or equal to 7 is [07M04]
a) A + BCD
b) [A + BCD]1
c) A + BC+D
d) A + B+CD
67. _ _ _ _ _ _ _ _ _ _ is 4 input , 2 bit multiplexer [07S01]
a) 74 X 153
b) 74 X 151
c) 74 X 541
d) 74 X 148
68. _ _ _ _ _ _ _ _ _ _ has three state outputs. [07S02]
a) 74 X 251
b) 74 X 153
c) 74 X 541
d) 74 X 148
69. _ _ _ _ _ _ used as 1 bit 8 output demultiplexer. [07S03]
a) 74 X 138
b) 74 X 251
c) 74 X 153
d) 74 X 541
70. _ _ _ _ _ _ is 9 bit parity generator. [07S04]
a) 74 X 280
b) 74 X 86
c) 74 X 138
d) 74 X 153
71. The square of three bit binary number
is represented as PQRSTU. Then Boolean
expression for U is [08D01]
a) A0

ORKUT COMMUNITY

WARRIOR-JNTU
b)
c)
d)
72. The square of three bit binary number
is represented as PQRSTU. Then Boolean
expression for P is [08D02]
a)
b)
c)
d)
73. AGTBout in 74 X 85 is equal to [08M01]
a)
b)
c)
d)
74. AEQB out in 74 X 85 is equal to [08M02]
a)
b)
c)
d)
75. ALTB out in 74 X 85 is equal to [08M03]
a)
b)
c)
d)
76. A block of flats has four floors and it is arranged that the lights for the stair well can be
switched on or off at any floor level.When the switch on, that level is operated. If
switches on the four levels A, B ,C, & D and lights L ,the Boolean expression for L is
[08M04]
a) A oplu; B oplus C oplus D
b) A oplus B oplus C D
c) A oplus B C oplus D
d) A B oplus C oplus D
77. _ _ _ _ _ _ _ _ used to check the parity bit when a code word is received. [08S01]
a) 74 X 280
b) 74 X 86
c) 74 X 138
d) 74 X 153
78. _ _ _ _ _ _ _ _ is 4 bit comparator. [08S02]
a) 74 X 85
b) 74 X 280
c) 74 X 138
d) 74 X 153
79. _ _ _ _ _ _ _ _ has cascading inputs for combining multiple '85s to create comparator for
more than four bits. [08S03]
a) 74 X 85
b) 74 X 280

ORKUT COMMUNITY

WARRIOR-JNTU
c) 74 X 138
d) 74 X 153
80. _ _ _ _ _ _ _ _ is 8 bit comparator and has no cascading inputs. [08S04]
a) 74 X 682
b) 74 X 85
c) 74 X 138
d) 74 X 153
81. The square of three bit binary number
is represented as PQRSTU. Then Boolean
expression for S is [09D01]
a)
b)
c)
)
d)
)
82. If the five bit number is ABCDE, the Boolean expression for majority logic function M is
( M = 1, when the majority of digits in a five bit number are 1) [09D02]
a) A( B+ E) (C + D) + BE ( A+ C+ D) + CD ( A+ B+ E)
b) A( B+ E) (C + D) + BE ( A+ C+ D) + ( A+ B+ E)
c) ( B+ E) (C + D) + E ( A+ C+ D) + CD ( A+ B+ E)
d) A( B+ E) (C + D) + B ( A+ C+ D) + C ( A+ B+ E)
83. If A, B, Bin are inputs and D & Bout are outputs of full sub tractor, then B out is
[09M01]
a)
b)
c)
d)
84. Parity checking function for even parity is [09M02]
a)
b)
c)
d)
85. Parity checking function F0 for odd parity is [09M03]
a) [D_2 oplus D_1 oplus D_0 oplus P_0]1
b)
c)
d)
86. If
and D0 are three bit input to parity generator, then Pe is even parity bit. Boolean
expression for Pe in terms of
is [09S01]
a)
b)
c)
d)
87. If
and D0 are three bit input to parity generator, then Po is odd parity bit. Boolean
expression for Po in terms of
is [09S02]
a) (D_2 oplus D_1 oplus D_0)1
b)
c)

ORKUT COMMUNITY

WARRIOR-JNTU
d) (D_2 oplus D_1 + D_0 )1
88. if then else VHDL statement used within [09S03]
a) process
b) WHILE
c) select
d) assert
89. If the input & output signal voltage levels(L & H) are indicated in truth table, then it is
also known as [09S04]
a) function table
b) excitation table
c) state table
d) state diagram
90. _ _ _ _ _ _ _ _ _ _ _ is quadruple 2 input XOR gate. [09S05]
a) 74 X 86
b) 74 X 280
c) 74 X 138
d) 74 X 153
91. Total worst case delay in ripple adder
is [10D01]
a)
b)
c)
d)
92. For carry look ahead adder
inputs), then
is [10M01]
a)
b)
c)
d)
93. In 74 X 283, carry
is [10M02]
a)
b)
c)
d)
94. The VHDL code for difference bit in full sub tractor is [10S01]
a) diff <= x XOR Y XOR ;
b)
;
c)
;
d)
;
95. Borrow out in full sub tractor VHDL code is [10S02]
a) bout < = ( not X and
or ( not X and Y) or ( and Y);
b) bout < = ( not X n and ) or ( not X and y) nor ( and Y);
c) bout < = ( not X and ) nor ( not X nand y) or ( and Y);
d) bout < = ( not X and ) nor ( not X and y) or ( nand Y);
96. For more flexible comparisions & arithmetic operations IEEE 1076-3 created a package.
it is [10S03]
a) std logic arith
b) std logic ulogic

ORKUT COMMUNITY

WARRIOR-JNTU
c) std logic 1164
d) std logic unsigned
97. _ _ _ _ _ _ _ _ _ is a 4 bit binary adder. [10S04]
a) 74 X 283
b) 74 X 280
c) 74 X 138
d) 74 X 153
98. Total propagation delay from C0 to
in 16 bit group ripple adder using 74 X 283 is
[10S05]
a) same as that of eight inverting gates.
b) twice the eight inverting gates
c) same as that of six inverting gates
d) same as that of four inverting gates
99. _ _ _ _ _ _ _ _ is 4 bit ALU. [10S06]
a) 74 X 181
b) 74 X 280
c) 74 X 138
d) 74 X 153
100.
In
, if S3 S2 S1 S0 = 0011, M = 1, then F is [10S07]
a) A
b)
c)
d)
101.
For 74 x 182,
is [11D01]
a)
b)
c)
d)
102.
For 74 x 382, if S2 S1 S0 =110, then F is [11M01]
a)
b)
c)
d)
103.
In 24 bit comparator circuit PGTQ is [11M02]
a) GT2+EQ2 . GT1 + EQ2. EQ1 . GT0
b)
c)
d)
104.
In 74 x 181, if S3 S2 S1 S0 = 1100, M = 1, then F is [11S01]
a) 0000
b) 1010
c) 1111
d) 1001
105.
_ _ _ _ _ _ _ provide group carry look ahead outputs. [11S02]
a) 74 381
b) 74 280

ORKUT COMMUNITY

WARRIOR-JNTU
c) 74 138
d) 74 153
106.
For _ _ _ _ _ _ _ _ , if S2 S1 S0 = 100 then function output ,F is
[11S03]
a) 74 381
b) 74 280
c) 74 138
d) 74 153
107.
_ _ _ _ _ _ _ _ _ multiplier use a single adder & a register to accumulate the
partial products. [11S04]
a) sequential
b) Carry save
c) group ripple
d) Parity
108.
_ _ _ _ _ _ _ _ specify the direction of shift, type of shift and amount of shift.
[11S05]
a) Barrel shifter
b) Carry save shifter
c) sequential shifter
d) group ripple shifter
109.
If barrel shifter uses _ _ _ _ _ _ _ ,the data delay will be 1. [11S06]
a) 74 251
b) 74 280
c) 74 138
d) 74 182
110.
First and second highest priority encoder circuit uses [12D01]
a) two 74LS148, one 74LS138, 74LS04, 74LS00
b) four 74LS148, four 74LS138, two74LS04,74LS00
c) three 74LS148, one 74LS138, four74LS04, two74LS00
d) one 74LS148, one 74LS138,two74LS04, three74LS00
111.
24 bit comparator uses [12D02]
a) three 74 682, two 74 27, three 74 02
b) two 74 682, two 74 29, two 74 03
c) four 74 684, three74 27, three 74 02
d) three 74 682, one 74 27, two 74 02
112.
One of the following VHDL statement is used for for Dual parity encoder
[12D03]
a) if R(i) = `1' and Avalid = `0', then
A <= conv _ std _ logic _ vector (i, 3); Avalid < = `1 ';
elsif R(i) = `1' and Bvalid = `0', then
B < = conv _ std _ logic _ vector (i,3); Bvalid < = `1';
end if;
b) if R(i) = `1' and Avalid =0, then
A <= conv _ std _ logic _ vector (i, 3); Avalid < = `1'; end if;
c) if R(i) = `1' and Bvalid = `0', then
B < = conv _ std _ logic _ vector (i,3); Bvalid < = `1';
end if;

ORKUT COMMUNITY

WARRIOR-JNTU
d) if R(i) = `1' and Avalid =1, then
A < = conv _ std _ logic _ vector (i, 3); Avalid < = `0';
Elsif R(i) = `0' and Bvalid = `0', then
B < = conv _ std _ logic _ vector (i,3); Bvalid < = 0; end if;
113.
If B is 11 bit unsigned binary integer & M,E are 4 bits and 3 bits ( 7 point floating
Point number), T is truncation error, then B is [12M01]
a)
b)
c)
d)
114.
In 24 bit comparator circuit, PEQQ is [12M02]
a) EQ2.EQ1.EQ0
b)
c)
d)
115.
Mode dependent comparator circuit uses [12M03]
a) one 74LS682, one74 86 and two 74 157.
b) two 74LS689, one74 86 and one74 157.
c) three 74LS682, one74 86 and two 74 159.
d) one 74LS682, two74 89 and FOUR 74 157.
116.
One of the following VHDL statement is used for left rotate in 6 function barrel
shifter [12M04]
a)
b)
c)
d)
117.
A combinational fixed point to floating point encoder consists of [12S01]
a) one 74 148, three 74 154
b) one 74 148, two 74 154, 74 251
c) two 74 154, 74 251
d) 74 280,two 74 138
118.
One of the following VHDL statement is used for Fixed point to floating point
conversion [12S02]
a) if BV < 16 ,then M < = B (3down to 0); E < = ``000``;
b) if BV < 15 ,then M < = B (3down to 1); E < = ``001``;
c) if BV < 14 ,then M < = B (2down to 0); E < = ``010``;
d) if BV < 10 ,then M < = B (3down to 2); E < = ``100``;
119.
74x682 does not provide [12S03]
a) less than output
b) greater than output
c) equal output
d) output
120.
74LS109 has the following characteristic equation. [13D01]
a)
b)
c)

ORKUT COMMUNITY

WARRIOR-JNTU
121.

d)

74LS74 characteristic equation is [13M01]

a)
b)
c)
d)
122.
In JK master slave FF, because of the gating on master latches S & R inputs, FF
output change to1 even though K and not J is asserted at the end of the Triggering
pulse.This behaviour known as [13M02]
a) 1's latching
b) 0s latching
c) don't care latching
d) Z latching
123.
_ _ _ _ _ _ _ _ _ is the minimum delay between negative S & R( in S - R latch)
for them to be considered non simultaneous. [13S01]
a) Recovery time
b) propagation time
c) delay time
d) access time
124.
Commercial TTL positive edge triggered D flipflop do not use [13S02]
a) master slave latch design
b) master latch design
c) synchronous latch design
d) asynchronous latch design
125.
_ _ _ _ _ _ _ _ _ _ is positive edge triggering D FlipFlop. [13S03]
a) 74LS74
b) 74LS109
c) 74LS79
d) 74LS70
126.
Important Flip Flop function for ASIC testing is [13S04]
a) scan capability
b) input capability
c) output capability
d) switching capability
127.
Figure (a) represents

Figure(a)

ORKUT COMMUNITY

WARRIOR-JNTU
[13S05]
a)
b)
c)
d)

positive edge triggered D Flip Flop with scan.

positive edge triggered D Flip Flop
negative edge triggered D Flip Flop with scan.
negative edge triggered D Flip Flop
128.
Flip Flops with postponed output indicator (Master - slave S R FF) are called
[13S06]
a) pulse triggered Flip Flop
b) positive edge triggered D Flip Flop with scan
c) negative edge triggered T Flip Flop with scan.
d) negative edge triggered JK Flip Flop with scan.
129.
_ _ _ _ _ _ _ _ is a TTL positive edge trigger JKFF with active low K input.
[13S07]
a) 74 X 109
b) 74LS74
c) 74 X 190
d) 74 X 10
130.
Set up time margin is [14D01]
a)
b)
c)
d)
131.
Hold time margin is [14D02]
a)
b)
c)
d)
132.
For proper circuit operation [14D03]
a)
b)
c)
d)
133.
If _ _ _ _ _ _ _ _ _ _ _ is negative, the circuit don't work. [14M01]
a) set up time margin
b) Hold time margin
c)
d)
134.
The sum of minimum values of
and
must be [14M02]
a) greater than
b) greater than
c) less than
d) less than Set up time margin
135.
S - R latch characteristic equation is [14S01]
a)
b)

ORKUT COMMUNITY

WARRIOR-JNTU
c)
d)
136.

137.

D FF with enable characteristic equation is [14S02]

a)
b)
c)
d)

T FF with enable characteristic equation is [14S03]

a)
b)
c)
d)
138.

VHDL statement for positive edge triggered D FF is [14S04]

Q < = D when clk' event and clk =`1' else Q;
Q < = D when clk' event and clk = `0' else not Q ;
Q < = not D when clk' event and clk = `1' else Q;
Q > = D when clk' event and clk =`0' else not Q;
139.
_ _ _ _ _ _ _ _ contain four D latches. [14S05]
a) 74 X 375
b) 74 X 74
c) 74 X 112
d) 74 X 175
140.
In 74 X175, _ _ _ _ _ _ _ _ _ _ _ are buffered. [15D01]
a) clock and CLR _ L
b) clock, D
c) CLR, Q
d) 1Q
141.
consider Bus holder circuit in 3.3V CMOS LVC. Specify a maximum over ride
cutoff [15M01]
a) 500 A
b) 100 mA
c) 300micro A
d) 200 micro A
142.
If no output is driving the bus, it will float. So an active _ _ _ _ _ _ _ _ _ _ is used
to pull a floating bus to a valid high logic level [15M02]
a) Bus holder circuit
b) SSRAM
c) SDRAM
d) miller circuit
143.
_ _ _ _ _ _ _ _ _ _ is JKFF with active low clock input. [15S01]
a) 74 112
b) 74 74
c) 74 375
d) 74 175
144.
_ _ _ _ _ _ _ _ _ _ contains 4 bit register with a common clock and asynchronous
clear input. [15S02]
a)
b)
c)
d)

ORKUT COMMUNITY

WARRIOR-JNTU
a)
b)
c)
d)
145.
a)
b)
c)
d)
146.
a)
b)
c)
d)
147.
a)
b)
c)
d)
148.
a)
b)
c)
d)
149.
a)
b)
c)
d)
150.
a)
b)
c)
d)
151.
a)
b)
c)
d)
152.
a)
b)
c)
d)
153.
a)

74 175
74 375
74 370
74 112
_ _ _ _ _ _ _ _ _ _ is 6 bit register. [15S03]
74 174
74 375
74 75
74 112
_ _ _ _ _ _ _ _ _ _ is ( octal edge trigger D FF) 8 bit register. [15S04]
74 374
74 174
74 74
74 112
_ _ _ _ _ _ _ _ _ _ uses D latches. [15S05]
74 373
74 174
74 74
74 112
_ _ _ _ _ _ _ _ _ _ _ _ uses pin 1 for asynchronous clear input. [15S06]
74 273
74 174
74 74
74 112
_ _ _ _ _ _ _ _ _ _ _ _ uses pin1 for active low clock enable input. [15S07]
74 377
74 174
74 74
74 112
GAL22V10 has
= [16M01]
13 or 2.5
10 or 1.5
5 or 20
12 or 3.5
Little rectangular symbols inside the buffer symbols indicate [16S01]
Hysterisis
inverter
amplification
inductance
_ _ _ _ _ _ _ _ _ _ _ _ is first generation sequential PLD. [16S02]
PAL16R8
PAL20L8
PAL20L10
GAL16V8R
_ _ _ _ _ _ _ _ _ has `0' registered outputs. [16S03]
PAL20L8

ORKUT COMMUNITY

WARRIOR-JNTU
b) PAL16R8
c) GAL16V8R
d) GAL22V10
154.
_ _ _ _ _ _ _ _ _ _ _ _ is electrically erasable PLD. [16S04]
a) GAL16V8
b) PAL16R8
c) PAL20L8
d) GA2V10
155.
In _ _ _ _ _ _ _ _ _ _ ,output logic macro cell individually configured to bypass
flip flop [16S05]
a) GAL16V8R
b) PAL20L8
c) PAL16R8
d) GAL22V10
156.
The macro cells in PAL16V8R can be [16S06]
a) registered and combinational
b) sequential and combinational
c) registered and sequential
d) sequential and buffered, inverted
157.
_ _ _ _ _ _ _ _ _ _ _ in PLD represents the propagation delay from rising edge of
clock to primary output. [16S07]
a)
b)
c)
d) tH
158.
_ _ _ _ _ _ _ _ _ _ _ _ _ is a synchronous 4 bit binary counter with active low load
and clear input. [16S08]
a) 74 163
b) 74 160
c) 74 74
d) 74 112
159.
_ _ _ _ _ _ _ _ _ _ is a modulo 10 counter. [16S09]
a) 74 160
b) 74 166
c) 74 74
d) 74 112
160.
In 74 X 299, bits shifted right if [17M01]
a) S1 =0 , SD =1
b) S1 =0 , SD =0
c) S1 =1 , SD =1
d) S1 =1, SD =0
161.
In serial to parallel conversion using parallel out shift register, the following ICs
are used. [17M02]
a) two 74 X163, one 74 X 164, two 74 X 04, one 74 X 27, one 74 X 377
b) threee 74 X 163, one 74 X 164, two 74 X 04, two74 X 27, one 74 X 377.
c) two 74 X 163, one 74 X 164, three 74 X 04, one 74 X 27, two74 X 377.

ORKUT COMMUNITY

WARRIOR-JNTU
162.

163.

164.

165.

166.

167.

168.

169.

170.

d) two 74 X 163, four74 X 164, three 74 X 04, one 74 X 27, one 74 X 377.
LFSR also known as [17M03]
a) maximum length sequence generator
b) minimum length sequence generator
c) shift circular register
d) Johnson counter
_ _ _ _ _ _ _ _ _ _ _ is up/down counter. [17S01]
a) 74 X 169
b) 74 X 166
c) 74 X 74
d) 74 X 112
one of the follwing VHDL statement used for upcounter is [17S02]
a)
b)
c)
d)
_ _ _ _ _ _ _ _ _ _ _ is 8 bit serial in parallel out shift register. [17S03]
a) 74 X 164
b) GAL22V10
c) 74 X 74
d) 74 X 112
_ _ _ _ _ _ _ _ _ _ _ is 8 bit parallel in serial out shift register. [17S04]
a) 74166
b) GAL22V10
c) 74 X 74
d) 74 X 112
_ _ _ _ _ _ _ _ _ _ _ is universal shift register. [17S05]
a) 74 X 194
b) 74 X 166
c) 74 X 74
d) 74 X 112
In ring counter using 74 X 194, LIN serial input connected to [17S06]
a) QA
b) QA1
c) CLR L
d) TE
In Johnson counter using 74 X 194 , LIN serial input connected to [17S07]
a) QA1
b) QA
c) CLR L
d) TE
For proper synchronous operation, one of the following is considered [18D01]
a)
b)
c)
d)

ORKUT COMMUNITY

WARRIOR-JNTU
171.

172.

Metastability resolution time, t r is [18D02]

a)
b)
c)
d)

MTBF (tr) is [18G03]

a)
b)
c) [erfc( t_r / ) ] / [ T_0 .f .a
d)
173.
To get a flip - flop out of metastable state [18M01]
a) force the flip - flop into a valid logic state using input signals
b) force the flip - flop into a weak high logic state using input signals
c) force the flip - flop into a weak low logic state using input signals
d) force the flip - flop into a unknown logic state using input signals
174.
one of the following VHDL statement used for shift circular register circuit
[18S01]
a)
( 7 down to 1);
b)
( 6 down to 1);
c)
( 6 down to 0);
d)
( 5 down to 1);
175.
For reliable synchronous design, one of the following is valid. [18S02]
a) ensure FF have positive set up & hold time margins
b) synchronizers should have medium probability of failure
c) maximize amount of clock skew
d) ensure FF have negative set up & hold time margins
176.
_ _ _ _ _ _ _ _ _ _ _ structure eliminate clock skew in ASIC. [18S03]
a) clock tree
b) synchronizers
c) equalizers
d) clock latency
177.
A method of gating the clock that generates only minimal clock skew is [18S04]
a) gates in same IC package is used to generate un gated clock and gated clocks
from same master clock signal.
b) gates in different IC package is used to generate ungated clock and gated clocks
from same master clock signal.
c) gates in same IC package is used to generate ungated clock and gated clocks from
different master clock signal.
d) using of equalizers and digital delay lines
178.
For reliable synchronous design , one of the following is valid. [18S05]
a) minimize amount of clock skew
b) synchronizers should have medium probability of failure
c) ensure FF have negative set up & hold time marging
d) maximize amount of clock skew
179.
For reliable synchronous design , one of the following is valid. [18S06]
a) synchronizers should have low probability of failure.

ORKUT COMMUNITY

WARRIOR-JNTU

180.

181.

182.

183.

184.

185.

186.

187.

188.

b) synchronizers should have medium probability of failure.

c) ensure FF have negative set up & hold time marging
d) maximize amount of clock skew
EPROM (CMOS Technology) Write cycle is [19D01]
a) 10 - 50 s/byte
b) 50 - 100 s /byte
c) 70 - 500 s /byte
d) 100 - 500 s /byte
Two dimensional decoding allows a 128 X 1 ROM to be built with [19M01]
a) 3 to 8 decoder and 16 input multiplexer
b) 2 to 4 decoder and 10 input multiplexer
c) 3 to 10 decoder and 20 input multiplexer
d) 10 to 1024 decoder and 1024 input multiplexer
A 1M X 1 ROM could be built with [19M02]
a) 10 to 1024 decoder and 1024 input multiplexer
b) 3 to 8 decoder and 16 input multiplexer
c) floating source MOS
d) 3 to 10 decoder and 20 input multiplexer
For 74HC04, low level is [19S01]
a)
b) = 1.35 V
c)
d)
_ _ _ _ _ _ _ _ _ _ _ is used to reduce the decoder size in ROM [19S02]
a) Two dimensional decoding
b) one dimensional decoding
c) five dimensional decoding
d) four dimensional decoding
PROM (Bipolar technology) Read cycle is [19S03]
a)
b) 200ns
c)
d) 50 ms
EEPROM ( NMOS Technology) Read cycle is [19S04]
a) 50 - 200 ns
b) 250 -1 200ms
c) 250 - 300ns
d) 500 - 1500ns
EPROMs will have [19S05]
a) floating gate MOS
b) floating source MOS
c) floating drain MOS
d) floating body MOS
_ _ _ _ _ _ _ _ _ _ is 8K X 8 EPROM. [19S06]
a) 2764
b) HM6264

ORKUT COMMUNITY

WARRIOR-JNTU
c) 74 X 74
d) 74 X 112
189.
_ _ _ _ _ _ _ _ _ _ _ input must be asserted to enable outputs in EPROM. [19S07]
a) output enable(OE)
b) CLR L
c) WE L
d) CS
190.
In SRAMs output buffer is automatically disabled whenever _ _ _ _ _ _ _ _ is
asserted ,even if OE _ L is asserted. [20D01]
a) WE L
b) WE H
c) CLR L
d) CLR H
191.
Shown in figure (a) represents

Figure(a)
[20D02]
a)
b)
c)
d)
192.

storage cell for one bit in a DRAM

storage cell for one byte in a EPROM
storage cell for two bit in a SSRAM
storage cell for two bit in a EEPROM
Shown in figure (a) represents

Figure(a)

ORKUT COMMUNITY

WARRIOR-JNTU
[20G01]
a)
b)
c)
d)
193.
a)
b)
c)
d)
194.
a)
b)
c)
d)
195.
a)
b)
c)
d)
196.
a)
b)
c)
d)
197.
a)
b)
c)
d)
198.
a)
b)
c)
d)
199.
a)
b)
c)
d)

digital attenuator
modem
codec
PCM transmitter
_ _ _ _ _ _ _ _ _ is the 8 bit companded encoding. [20S01]
law PCM
QAM
DPCM
PWM
_ _ _ _ _ _ _ _ is 8K X 8 SRAM. [20S02]
HM6264
GAL22V10
2764
74HC04
_ _ _ _ _ _ _ _ _ _ _ adds OUTREG to the read data path. [20S03]
A ZBT SSRAM with pipelined outputs
Extended data out DRAM
Late write SSRAM
EEPROM
Late write SSRAM suffer with _ _ _ _ _ _ _ _ [20S04]
turn around penalty
burst mode
multi rate
recovery time
_ _ _ _ _ _ _ _ _ _ _ _ supports burst mode. [20S05]
late write SSRAM with flow through outputs
Extended data out DRAM
SRAMs output buffer
ZBT SSRAM with pipelined outputs
_ _ _ _ _ _ _ _ _ contains separate OE L control input. [20S06]
Extended data out DRAM
SDRAM
SSRAM
LATE WRITE SSRAM
RAS to CAS delay is known as [20S07]
CAS latency
RAS latency
CAS propagation time
RAS recovery time

ORKUT COMMUNITY