Objectives

Describe structural units of a processor.

p
Explain various types of memory devices and
their uses.
Explain concept of memory map.
Select
S l t th
the appropriate
i t processor, microcontroller,
i
t ll
or DSP.
Organize the chosen processor, memories, and
interfacing circuit.

Processor and
Memory Organization
Asst. Prof. Suree Pumrin, Ph.D.
Semester
Se
este 1/2553
/ 553

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Topics

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Structural Units in a Processor (1)

Structure units of processor

Memory
M
blocks
bl k ffor th
the d
data-structures
t t t
and
d data
d t
set elements
Concept of memory map
g
and addresses of I/O devices
Device registers
Direct memory access
Memories and I/O devices interface circuit

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2142492 Selected Topics in

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Structural Units in a Processor (2)

1)
2)
3)
4)
5)
6)

Internal and external buses interconnect the processor

internal units with system memories, I/O devices and
all o
a
other
e sys
system
e e
elements
e e s
Address, data and control buses
MDR (memory data register) holds the accessed byte
or word
d
MAR (memory address register) holds the address
BIU (Bus Interface Unit)
Program Counter or Instruction Pointer and Stack
Pointer

Figure 2.1 Block Diagram of structural units at a processor

in an embedded system.
system
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2142492 Selected Topics in

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Structural Units in a Processor (3)

Structural Units in a Processor (4)

ARS (Application Register Set): Set of on-chip

registers for use in the application program.
8) Register windowwindow a subset of registers with each
subset storing static variables and status words of a
routine.
9) Changing windows helps in fast context-switching in a
program.
10) ALU and FLPU (Arithmetic and Logic operations Unit
and Floating Points operations Unit). FLPU associates
a FLP register set for operations.
11) Register set is also called file and associates ALU or
FLPU.

12) Instruction, Data and Branch Target Caches and

associated PFCU (Prefetch control unit) for prefetching the instructions
instructions, data and next branch target
instructions, respectively.
13) AOU (Atomic Operations Unit ) An instruction is broken
into number of processor-instructions called atomic
p
((AOs),
), AOU finishes the AOs before an
operations
interrupt of the process occurs - Prevents problems
arising out of incomplete processor-operations on the
shared
h dd
data
t iin th
the programs

7)

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2142492 Selected Topics in

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Processor Performance

Structural Units in a Processor (5)

14) Advanced Processing units (i) MAC, bit reversal and
shifter units, VLIW processing unit in a DSP, (ii) Units
for multistage pipeline processing,
processing multi
multi-line
line
superscalar processing to boost the processing
speeds much higher than one instruction per clock
cycle.

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Processor Selection
in Embedded System (1)
1)
2)
3)
4)
5)
6)
7)
8)

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Processor Selection
in Embedded System (2)
9) On-chip DMA controller
10) Interrupt System
11) Advanced Processing Units
12) Harvard or Princeton Architectures for
memory organization
i ti
13) RISC or CISC or RISC core with CISC like
instruction set
14) On-chip compiler
15) AOs feasibility
16) IO Mapped IO space like 80x86 or Memory
mapped IOs

Instruction Cycle Time

Processing Performance per sec per W
Internal Bus Width
Caches and multi-way caches
On-chip RAM and ROM
Interrupt System
Requirement of Floating Point instructions
Requirement of Bit Manipulations instruction
needs
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1) MIPS Million Instructions Per Second

2) MFLOPS Million Floating Point
Operations Per Second
3) Dhrystone/s
Dh t
/ Number
N b off titimes a
benchmark program called Dhrystone
program can run per second.[1MIPS
d [1MIPS =
1757 Dhrystone/s

11

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Real-Time Control of a Robot

Motor needs signal at the rate of 50 to
y Program
g
size is also
100 ms only.
limited. Low MIPS performance
suffices. Therefore,, Microcontroller
8051, 68HC11, 68HC12 are the best
choice.
[Refer Example 2.2 pp. 63 for details]

Processor Selection Examples:

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14

N t
Network
kS
Switching
it hi S
System
t

Voice Data Compression

Voice signals are 64kbps. High MIPS
performance needed. On-chip
p
p memory
y
does not suffice for the resulting data.
p yp
processor
Therefore,, an exemplary
needed is 80x86 or a DSP
[Refer Example 2.3
2 3 pp.
pp 63-64 for details]

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2142492 Selected Topics in

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Transfer rates of 100 Mbps from a switch

are needed.
needed RISC architecture for high
MIPS needed. Exemplary processors
needed are Power PC or ARM7.
ARM7
[Refer Example 2.4 pp. 64 for details]

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Real Time Video Processing

Software Concept

- Needs fast frame compression

- Use of a DSP with advanced Processing
units MACs needed.
- Multiprocessor system having TMS
DSP, SHARC, TigerSHARC, ARM9 or
PowerPC processors needed. [Refer
Example 2.5
2 5 pp.
pp 64 for details]
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Memory of a Computer System

Von Neumann Architecture

Memory Selection Examples

Harvard Architecture

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A t
Automatic
ti Washing
W hi M
Machine
hi

Data Acquisition System

S

Needs
N
d mass manufacturing
f t i th
therefore
f
masked ROM, needs EEPROM for
current machine status, RAM for
y, A
variables and stack only,
Microcontroller on-chip 256 byte RAM,
4 kB ROM and 128 byte EEPROM
suffice [Refer Example 2.6a pp. 69 for
details]
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Data acquired to be stored at the flash

(for example 128 kB) ; Needs about 8
kB ROM or EPROM for program
memory, 512 B RAM
[Refer Example 2.7a pp. 70 for details]

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22

Di it l camera
Digital

Set-top Box System

1024 color camera images need 64 kB

ROM 32 MB flash
ROM,
flash, and 1 MB RAM.
RAM
- Camera with 1 GB memory stick can
record
d iimage and
d sound
db
both
h ffor
several minutes.

Large ROM as well as large RAM, 16kB

EEPROM for phone and messages
memory

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Functions, Processes
Functions
Processes, Data and
Stacks of Memoryy
Segment wise memory allocation in four
segments; Code, Data, Stack and Extra
(for examples,
examples image
image, String)

Memory Allocation To Program

Segments and Blocks

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Segments and Paging at the

Memory

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Differentt Data
Diff
D t Structures
St t
att the
th
( )
Memoryy Blocks (1)
1)) Stacks Return addresses on the
nested calls, Sets of LIFO (Last In First
Out)) retrievable data,, Saved Contexts of
the tasks as the stacks

Figure 2.2 (a) The segment types and pages in an exemplary

program
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Differentt Data
Diff
D t Structures
St t
att the
th
( )
Memoryy Blocks (2)
2) Arrays One dimensional or
multidimensional
l idi
i
l
3) Queues Sets of FIFO (First In First
Out) retrievable data; Circular Queue
(Example a Printer Buffer); Block
(ExampleQueue (Example- a network stack)

Figure 2.3 An example of

different stack structures at the
memory blocks.

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Differentt Data
Diff
D t Structures
St t
att the
th
( )
Memoryy Blocks (3)

Figure 2.4 An array at

a memory block.
block

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4) Table
5) Look up Table Look-up-table
Look up table row
first column points to another memory
block of a data structure data
6) List: In a list element, a data structure
off an item
it
also
l points
i t tto the
th nextt item
it
7)) Process Control Block [[Refer Chapter
p
8]
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Memory Map
Map to show the program and data
allocation of the addresses to ROM, RAM,
EEPROM or Fl
Flash
h iin th
the system
t

Figure 2.5
2 5 Four memory allocation maps
maps.
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P t d I/O vs Memory
Ported
M
Mapped
M
d I/O

D i Add
Device
Addresses M
Map
Device control and status addresses
and port address remains constant
and are not re-locatable in a program
as the glue circuit (hardware) to
accesses these is fixed during the
circuit
i it d
design.
i

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M
Memory
Mapped
M
d I/O

P t d I/O
Ported

In memory mapped I/O, for example, in

8051 microcontroller, the devices have
the addresses for processor-accesses
that are not distinct from the memory
and are accessed with same set of
instructions

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In I/O mapped I/O (Ported I/O), for example,

in 80x86 processor, the devices have the
addresses for processor-accesses that
are distinct from the memory and are
accessed by distinct set of instructions
[R f Example
[Refer
E
l 2.16
2 16 for
f a Serial
S i l Li
Line
Device on pp. 87-88]

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38

Interfacing the processor

processor, memory
memory,
and devices

DMA (Di
(Directt M
Memory A
Access))
Controller
External Devices can directlyy write and read
into the blocks of RAM using the DMA
controller when the buses are not in use
controller,
of the processor

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The p
processor,, memory
y and devices are
interfaced (glued) together using a
programmable
p
g
circuit like GAL or FPGA.
The circuit consists of the address
decoders
decode
s as pe
per the
e memory
e oya
and
d de
device
ce
addresses allocated and the needed
latches multiplexers/ demultiplexers

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Exercise
1. What are the common structure units in most
processors?
2. What are the special structural units in processors for
digital camera systems, real-time
real time video processing
systems, speech compression systems, voice
compression systems, and video games?
3. What do you mean by device registers and device
address?

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