Beruflich Dokumente
Kultur Dokumente
Fall 2015
Department of Electrical and Computer Engineering
Rutgers University
September 3, 2015
Class Times: Thursday 6:40 9.40 pm
Class Room: WL-AUD, Busch Campus
Lab Times: M-W-F 1.40 3.00 pm, Friday 6.40 8.00 pm
Labs: EE-105, Busch Campus
Course Web Site: http://sakai.rutgers.edu
Instructor: Dr.Nagi Naganathan (Adjunct Faculty, Department of ECE)
e-mail: nagi@computer.org
Lab Instructor:Swapnil Mhaske
e-mail:smhaske@scarletmail.rutgers.edu
Teaching Assistant:Moliang Zhou
e-mail:mz330@scarletmail.rutgers.edu
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The course will present a systematic approach to digital implementation in the labs using
SystemVerilog using Altera FPGA boards. This will provide a valuable skill required for FPGA design
along with embedded software.
Labs:
The course is supported with the labs and Altera FPGA board will be used and students will be building several
circuits using SystemVerilog.
Pre-requisites:
1.
2.
3.
Pre-requisite by Topics:
1.
2.
3.
4.
Boolean algebra
General Computer Skills
K-Map minimization
Combinational, Sequential Circuits
David Harris & Sarah Harris, Digital Design and Computer Architecture, 2nd Edition, Morgan Kaufman
Publishers, ISBN 978-0-12-394424-5
Sarah Harris & David Harris, Digital Design and Computer Architecture, ARM Edition, Morgan Kaufman
Publishers, ISBN 978-0-12-800056-4
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Course Material:
Slides from the Text books, my slides, additional slides from various sources such as web sites etc.,
intended only for academic use
Grading:
Home Works
Labs
Mid Term 1
Mid Term 2
Final Exam (Cumulative)
15%
30%
15%
15%
25%
Total
100%
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1.
2.
Topic
Organizational issues. Information revolution. Basic hardware
concepts.
Number systems, Binary addition, subtraction, Representation of
negative numbers, 2s complement addition/subtraction.
Logic Signals and Gates
Switching algebra, Theorems, Standard representation of logic
functions
Combinational circuits, Truth table, Karnaugh maps, Minimization
techniques
Latches and Flip-Flops
Synchronous Logic Design
Finite State Machine (FSM)
Timing
Hardware Description Language SystemVerilog
Book Chapters
Chapter 1 (From Zero to One)
Chapter 2 (Combinational Logic
Design)
Slides - Lectures #1, #2, #3
Dates
9/3/2015
9/10/2015
9/17/2015
Slides - Lecture #5
Chapter 4 (Hardware Description
Language)
Slides - Lecture #6
Chapter 5 (Digital Building Block)
9/24/2015
10/1/2015
1.
2.
Review
Memory and I/O Subsystesms
ARM Caches
Review
Chapter 6 ( Architecture)
Slides Lecture #9)
10/15/2015
10/22/2015
10/29/215
11/5/2015
11/12/2015
12/3/2015
12/10/2015
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