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NOTES

SUBJECT: INTEGRATED CIRCUITS


SUBJECT CODE: EEC-501

BRANCH: ECE
SEM:5th
SESSION: 2014-15
Evaluation scheme:
Subject
Code

Name of
Subject

EEC501

Integrated
Circuits

Periods

Evaluation Scheme

CT

TA

TOTAL

ESC

30

20

50

100

Subject
Total

Credit

150

Asst.Prof. Uma Sharma


ECE Department
AKGEC,GZB.

INDEX
Unit-1
Analog Integrated circuit Design: an overview
1.1 The current mirror
1.2 Basic mosfet current mirror
1.3 Improved current mirrors
1.4 The wilson current mirror
1.5 Improved wilson current mirror
1.6 Widlar current source
1.7 Cascoded current mirror
The 741 IC Op-Amp
1.8 The 741 ic operational amplifier
1.9 Model for second stage
1.10 The 741 output stage
1.11 Short circuit protection circuitry

Unit-2
Linear Applications of IC op-amps
2.1 Overview of op-amp (ideal and nonideal)
2.2 The inverting operational amplifier
2.3 The non-inverting operational amplifier
2.4 Differential amplifier
2.5 Instrumentation amplifier
2.6 The op-amp differentiator amplifier
2.7 The op-amp integrating amplifier
2.8 The summing amplifier
2.9 Operational amplifiers summary
2.10 V-I and I-V converters
2.11 Generalized impedance converter / simulation of inductor:
2.12 Filters
2.13 State variable filter
2.14 KHN filter
2.15 Tow-thomas biquad filter

Unit-3
Digital Integrated Circuit Design-An Overview
3.1 Basics of digital cmos design
3.2 nmos logic circuits with a mos loads
3.3 Two-input nand gate
3.4 Cmos logic circuits

3.5
3.6
3.7
3.8

Sequential mos logic circuits


SR latch circuit
Clocked latch and flip flop circuits
Cmos d latch and edge-triggered flip flops

Unit-4
Non-Linear applications of IC Op-amps
4.1 Log amplifier
4.2 Antilog amplifier
4.3 Precision rectifier circuits
4.4 Precision peak detector
4.5 Sample and hold circuit
4.6 Analog multiplier
4.7 Op-amp as comparator
4.8 Zero crossing detector using 741 IC
4.9 Op-amp comparator
4.10 Comparator characteristics
4.11 Schmitt trigger
4.12 Astable multivibrator using op-amp
4.13 Mono stable multivibrator using opamp
4.14 Triangular wave generator using op-amp

Unit-5
D/A and A/D converters
5.1 Digital to analog converter (D/A)
5.2 Digital to analog converter with R and 2R resistors
5.3 Analog to digital converters (A/D)
Integrated Circuit Timer
5.4 IC 555 TIMER
5.5 Block Diagram
5.6 Working Principle
5.7 Monostable multivibrator:
5.8 An astable multivibrator
Phase locked loops (PLL)
5.9 Phase Locked Loop(PLL)
5.10 Exclusive OR Phase Detector
5.11 IC 565 PLL

UNIT-1
1.1 THE CURRENT MIRROR:
A current mirror is a circuit block which functions to produce a copy of the current in one active
device by replicating the current in second active device. An important feature of the current
mirror is a relatively high output resistance which helps to keep the output current constant
regardless of load conditions. Another feature of the current mirror is a relatively low input
resistance which helps to keep the input current constant regardless of drive conditions. The
current being 'copied' can be, and often is, a varying signal current. Conceptually, an ideal
current mirror is simply an ideal current amplifier with a gain of -1. The current mirror is often
used to provide bias currents and active loads in amplifier stages. Given a current source as the
input, we convert the current (entering the current mirror) into a voltage and then use this voltage
to control a current sink (the current exiting the mirror); as a result, we obtain a current sink
(figure). Conversely, given a current sink as the input, we convert the input current (exiting the
current mirror) into a voltage and then use this voltage to control a current source (figure ); as a
result, now we obtain a current source. We can generalize this basic current mirror structure in a
first conclusion:
A current mirror consists of a current-to-voltage converter consecutively connected to a voltageto-current converter.

Current Mirror (a) Sink (b) Source


1.2 BASIC MOSFET CURRENT MIRROR
The simple current mirror can, obviously, also be implemented using MOSFET transistors, as
shown in figure We know that transistor M1 is operating in the saturation region because VDS is
greater than or equal to VGS. Transistor M2will also be in saturation so long as the output voltage
is larger than its saturation voltage. In this simple configuration, the output current IOUT is
directly related to IIN.

Simple MOS current mirror


The drain current of a MOSFET ID is a function of both the gate to source voltage and the drain
to gate voltage of the MOSFET given by ID = f (VGS, VDG), a relationship derived from the
functionality of the MOSFET device. In the case of transistor M1 of the mirror, ID = IIN. Input
current IIN is a known current, and can be provided by a resistor as shown in the figure, or by a
threshold-referenced or self-biased current source to ensure that it is constant, independent of
voltage supply variations.
Using VDG=0 for transistor M1, the drain current in M1 is ID = f (VGS,VDG=0), so we find: f (VGS,
0) = IIN, implicitly determining the value of VGS. Thus IIN sets the value of VGS. The circuit in the
diagram forces the same VGS to apply to transistor M2. If M2 also is biased with zero VDG and
provided transistors M1 and M2 have good matching of their properties, such as channel length,
width, threshold voltage etc., the relationship IOUT = f (VGS,VDG=0 ) applies, thus setting IOUT =
IIN; that is, the output current is the same as the input current when VDG=0 for the output
transistor, and both transistors are matched.
The drain-to-source voltage can be expressed as VDS=VDG + VGS. With this substitution, the
Shichman-Hodges model provides an approximate form for function f(VGS,VDG):

Where:
Kp is a technology related constant associated with the transistor, W/L is the width to length
ratio of the transistor, VGS is the gate-source voltage, Vth is the threshold voltage, VDS is the
drain-source voltage is the channel length modulation constant.

Output resistance
Because of channel-length modulation, the mirror has a finite output resistance given by the ro of
the output transistor, namely:

Where:
=channel-length modulation parameter
VDS = drain-to-source bias.
1.3 IMPROVED CURRENT MIRRORS:
Buffered Feedback current mirror
Figure shows a mirror where the simple wire connecting the collector of Q1 to its base is
replaced by an emitter follower buffer. This improvement to the simple current mirror is referred
to as an emitter follower augmented mirror. The current gain (Q3) of the emitter follower buffer
stage (Q3) greatly reduces the gain error caused by the finite base currents of Q1 and Q2.

Figure Buffered Feedback current mirror.


One thing to note that is different in this mirror configuration vs. the simple two transistor mirror
is that the Collector-Base voltage, VCB, of Q1 is no longer zero. It is equal to the VBE of Q3.
Given the effect of the finite output resistance (Early effect ) the output current IOUT in Q2 will
most closely match IIN when the collector voltage of Q2 is the same as that of Q1 which is

2XVBE above the common voltage. Also note that when driven by a resistor, like R1, IIN will now
be (V1-VBE1-VBE2)/R1.
Another consequence of adding the emitter follower buffer is, in general, a loss in the frequency
response of the mirror. Transistor Q3 is potentially operating at a very small current of 2IB. If
there were to be a significant capacitance to ground at the base connection common to Q1 and
Q2 the current available to discharge this current will also be small equal to 2IB. But the current
available to charge this node is potentially equal to Q3IIN which is very much larger than 2IB.
This asymmetry in the charging vs. discharging current available for this node in the current
mirror can lead to very undesirable response to fast changes to IIN.
1.4 THE WILSON CURRENT MIRROR:
A Wilson current mirror or Wilson current source, named after George Wilson, is an improved
mirror circuit configuration designed to provide a more constant current source or sink. It
provides a much more accurate input to output current gain. The structure is shown in figure4

Figure .The Wilson Current Mirror


We will be making the following two assumptions. First, all transistors have the same current
gain . Second, Q1 and Q2are matched, so their collector currents are equal. Therefore, IC1 =
IC2 (= IC) and IB1 = IB2 (= IB) .
The base current of Q3 is given by,

The emitter of Q3 current by,

Looking at figure4, it can be seen that IE3 = IC2 + IB1 + IB2 Substituting for IC2, IB1 and IB2, IE3 =
IC + 2IB
so,

Substituting for IE3

rearranging,

The current through R1 is given by, IR1 = IC1 + IB3


But, IC1 = IC2 = IC

Substituting for IC and since


we get,

Therefore,

And finally,

From the above equation we can see that if

And the output current (assuming the base-emitter voltage of all transistors to be 0.7 V) is
calculated as,

Note that the output current is equal to the input current IR1 which in turn is dependent on V1 and
R1. If V1 is not stable, the output current will not be stable. Thus the circuit does not act as a
regulated constant current source.
In order for it to work as a constant current source, R1 must be replaced with a constant current
source.
Advantages over other configurations
This circuit has the advantage of virtually eliminating the base current mismatch of the
conventional BJT current mirror thereby ensuring that the output current IC3 is almost equal to
the reference or input current IR1. It also has a very high output impedance due to the negative
feedback through Q1 back to the base of Q3.
1.5 IMPROVED WILSON CURRENT MIRROR:
Adding a fourth transistor to the simple Wilson current mirror in figure 5, we have the modified
or improved Wilson mirror. The improved input to output current accuracy is accomplished by
equalizing the collector voltages of Q1 and Q2 at 1 VBE. This leaves the finite and voltage
differences of each of Q1 and Q2 as the remaining unbalancing influences in the mirror.

Figure.The improved Wilson Current Mirror


1.6 WIDLAR CURRENT SOURCE:
A Widlar current source is a modification of the basic two-transistor current mirror that
incorporates an emitter degeneration resistor for only the output transistor, enabling the current
source to generate low currents using only moderate resistor values. This circuit is named for its
inventor, Robert Widlar, and was patented in 1967.
The Widlar circuit may be used with bipolar transistors or MOS transistors. An example
application is in the now famous uA741 operational amplifier, and Widlar used the circuit in
many of his designs.
Analysis

Figure.A version of the Widlar current source using bipolar transistors.

This observation is expressed by using KVL around the base emitter loop of the circuit in
Figure6 as:

Where 2 is the beta of the output transistor, which may not be the same as that of the input
transistor, in part because the currents in the two transistors are very different. The variable IB2 is
the base current of the output transistor, VBE refers to base-emitter voltage. If we neglect the
effect of finite and use the VBE equation we can obtain a useful formula for the output current:

where VT is the thermal voltage, IIN = IC1 and IOUT = IC2.


1.7 CASCODED CURRENT MIRROR:
Figure shows the implementation of the MOS and BJT cascode current sources using current
mirrors.

In the MOS circuit, ID1 = ID3 = IREF. The current mirror formed by M1 and M2 forces the
output current to be approximately equal to the reference current because IO = ID4 = ID2.
Diode-connected transistor M3 provides a dc bias voltage to the gate of M4 and balances VDS 1
and VDS2. If all transistors are matched with the same W/L ratios, then the values of VGS are all
the same, and VDS2 equals VDS 1:
VDS2 = VGS 1 + VGS3 VGS4 = VGS + VGS VGS = VGS = VDS 1
Thus the M1-M2 current mirror is precisely balanced, and IO = IREF. The BJT source in Fig.
operates in the same manner. For F =, IREF = IC3 = IC1 on the reference side of the source.
Q1 and Q2 form a current mirror, which sets IO = IC4 = IC2 = IC1 = IREF. Diode Q3 provides
the bias voltage at the base of Q4 needed to keep Q2 in the active region and balances the
collector-emitter voltages of the current mirror:

VCE2 = VBE1 + VBE3 VBE4 = 2VBE VBE = VBE = VCE1


Output Resistance of the Cascode Sources:
Figure shows the small-signal model for the MOS cascode source; the two-port model has been
used for the current mirror formed of transistors M1 and M2. Because current i represents the
gate current of M4, which is zero, the circuit can be reduced to that on the right in Fig. 16.24,
which should be recognized as a common-source stage with resistor ro2 in its source. Thus, its
output resistance is:
Rout = ro4 (1 + gm4ro2)

Analysis of the output resistance of the BJT source in Fig. is again more complex because of the
finite current gain of the BJT. If the base of Q4 were grounded, then the output resistance would
be just equal to that of the cascode stage, o ro. However, the base current ib of Q4 enters the
current mirror, doubles the output current, and causes the overall output resistance to be reduced
by a factor of 2:
Rout ( o4ro4)/2
1.8 THE 741 IC OPERATIONAL AMPLIFIER:

The now classic Fairchild 741 operational-amplifier design was the first to provide a highly
robust amplifier from the application engineers point of view. The amplifier provides excellent
overall characteristics (high gain, input resistance and CMRR, low output resistance, and good
frequency response) while providing overvoltage protection for the input stage and short-circuit
current limiting of the output stage. The 741 style of amplifier design quickly became the
industry standard and spawned many related designs. By studying the 741 design, we will find a
number of new amplifier circuit design and bias techniques.
Figure is a simplified schematic of the 741 operational amplifier. The three bias sources shown
in symbolic form are discussed in more detail following a description of the overall circuit. The
op amp has two stages of voltage gain followed by a class-AB output stage.

In the first stage, transistors Q1 to Q4 form a differential amplifier with a buffered current mirror
active load, Q5 to Q7. Practical operational amplifiers offer an offset voltage adjustment port,
which is provided in the 741 through the addition of 1-k resistors R1 and R2 and an external
potentiometer REXT.

The second stage consists of emitter follower Q10 driving common-emitter amplifier Q11 with
current source I2 and transistor Q12 as load. Transistors Q13 to Q18 form a short-circuit
protected class-AB push-pull output stage that is buffered from the second gain stage by emitter
follower Q12.
Bias Circuitry:
The three current sources shown symbolically in Figure are generated by the bias circuitry.The
value of the current in the two diode-connected reference transistors Q20 and Q22 is determined
by the power supply voltage and resistor R5:

assuming 15-V supplies. Current I1 is derived from the Widlar source formed of Q20 and Q21.

The output current for this design is

Using the reference current calculated in equation yields I1 = 18.4 A.


The currents in mirror transistors Q23 and Q24 are related to the reference current IREF
.Assuming VO = 0 and VCC = 15 V, and neglecting the voltage drop across R7 and R8,
VEC23 = 15+1.4 = 16.4Vand VEC24 = 150.7 = 14.3V.

DC Analysis of the 741 Input Stage:


The input stage of the741 amplifier is redrawn in the schematic in Fig. As noted earlier, Q1, Q2,
Q3, and Q4 form a differential input stage with an active load consisting of the buffered current
mirror formed by Q5, Q6, and Q7. In this input stage there are four base-emitter junctions
between inputs v1 and v2, two from the npn transistors and, more importantly, two from the pnp
transistors, and (v1 v2) = (VBE1 + VEB3 VEB4 VBE2).
In standard bipolar IC processes, pnp transistors are formed from lateral structures in which both
junctions exhibit breakdown voltages equal to that of the collector-base junction of the npn
transistor. This breakdown voltage typically exceeds 50 V. Because most general-purpose op
amp specifications limit the power supply voltages to less than 22 V, the emitter-base junctions
of Q3 and Q4 provide sufficient breakdown voltage to fully protect the input stage of the
amplifier, even under a worst-case fault condition, such as that depicted in Fig.
Q-Point Analysis
In the 741 input stage in Fig. the current mirror formed by transistors Q8 and Q9 operates with
transistors Q1 to Q4 to establish the bias currents for the input stage. Bias current I1 represents
the output of the Widlar source discussed previously (18 A) and must be equal to the collector

current of Q8 plus the base currents of matched transistors Q3 and Q4:


I1 = IC8 + IB3 + IB4 = IC8 + 2IB4
For high current gain, the base currents are small and IC8= I1.
The collector current of Q8 mirrors the collector currents of Q1 and Q2, which are summed
together in mirror reference transistor Q9. Assuming high current gain and ignoring the collector
voltage mismatch between Q7 and Q8,
IC8 = IC1 + IC2 = 2IC2

because the emitter currents of Q1 and Q3 and Q2 and Q4 must be equal. The collector current
of Q3 establishes a current equal to I1/2 in current mirror transistors Q5 and Q6 as well. Thus,
transistors Q1 to Q6 all operate at a nominal collector current equal to one-half the value of
source I1. Now that we understand the basic ideas behind the input stage bias circuit,

IC2 is related to IB4 through the current gains of Q2 and Q4:

which is equal to the ideal value of I1/2 but reduced by the nonideal current mirror effects
because of finite current gain and Early voltage. The emitter current of Q4 must equal the emitter
current of Q2, and so the collector current of Q4 is

The use of buffer transistor Q7 essentially eliminates the current gain defect in the current
mirror. Note from the full amplifier circuit in Fig.that the base current of transistor Q10, with its
50k emitter resistor R4, is designed to be approximately equal to the base current of Q7, and
VCE6=VCE5 as well. Thus, the current mirror ratio is quite accurate and

If 50k resistor R3 were omitted, then the emitter current of Q7 would be equal only to the sum
of the base currents of transistors Q5 and Q6 and would be quite small. Because of the Q-point
dependence of F , the current gain of Q7 would be poor. R3 increases the operating current of
Q7 to improve its current gain as well as to improve the dc balance and transient response of the
amplifier. The value of R3 is chosen to approximately match IB7 to IB10.
To complete the Q-point analysis, the various collector-emitter voltages must be determined. The
collectors of Q1 and Q2 are 1VEB below the positive power supply, whereas the emitters are
1VBE below ground potential. Hence,
VCE1 = VCE2 = VCC VEB9 + VBE2=VCC
The collector and emitter of Q3 are approximately 2VBE above the negative power supply
voltage and 1VBE below ground, respectively:
VEC3 = VE3 VC3 = 0.7 V (VEE + 1.4 V) = VEE 2.1 V
The buffered current mirror effectively minimizes the error due to the finite current gain of the
transistors, and VCE6 = VCE5 =2VBE = 1.4 V, neglecting the small voltage drop (<10 mV)
across R1 and R2. Finally, the collector of Q8 is 2VBE below zero so that
VEC8 = VCC + 1.4 V
and the emitter of Q7 is 1VBE above VEE:
VCE7 = VEE 0.7 V

AC Analysis of the 741 Input Stage:


The 741 input stage is redrawn in symmetric form in Fig with its active load temporarily
replaced by two resistors. From Fig we see that the collectors of Q1 and Q2 as well as the bases
of Q3 and Q4 lie on the line of symmetry of the amplifier and represent virtual grounds for
differential-mode input signals. The corresponding differential-mode half-circuit shown in Fig is
a common-collector stage followed by a common-base stage, a C-C/C-B cascade. The
characteristics of the C-C/C-B cascade can be determined from Fig and our knowledge of singlestage amplifiers. The emitter current of Q2 is equal to its base current ib multiplied by (o2 + 1),
and the collector current of Q4 is o4 times the emitter current. Thus, the output current can be
written as
io = o4ie = o4(o2 + 1)ib=o2ib
The base current is determined by the input resistance to Q2:

in which Rin4 = r4/(o4 + 1) represents the input resistance of the common-base stage.

input resistance is twice the value of the corresponding C-E stage:

we can see that the output resistance is equivalent to that of a common-base stage with a resistor
of value 1/gm2 in its emitter:

Voltage Gain of the Complete Amplifier:


We now use the results from the previous section to analyze the overall ac performance of the op
amp. We find a Norton equivalent circuit for the input stage and then couple it with a two-port
model for the second stage.
Norton Equivalent of the Input Stage:

the differential-mode input signal establishes equal and opposite currents in the two sides of the
differential amplifier where i = (gm2/4)vid. Current i, exiting the collector of Q3, is mirrored by
the buffered current mirror so that a total signal current equal to 2i flows in the output terminal:

The Thevenin equivalent resistance at the output is found using the circuit in Fig. and is equal to
Rth = Rout6//Rout4
Because only a small dc voltage is developed across R2, the output resistance of Q6 can be
calculated from

1.9 MODEL FOR SECOND STAGE:


Figure shows a two-port representation for the second stage of the amplifier. Q10 is an emitter
follower that provides high input resistance and drives a common-emitter amplifier consisting of
Q11 and its current source load represented by output resistance R2. A y-parameter model is
constructed for this network. From Fig and the bias current analysis, we can see that the collector
current of Q11 is approximately equal to I2 or 666 A. Calculating the collector current of Q10
yields

Parameters y11 and y21 are calculated by applying a voltage v1 to the input port and setting v2 = 0,
as in Fig. 16.62. The input resistance to Q11 is that of a common-emitter stage with a 100
emitter resistor:
Rin11 = r11 + (o11 + 1)100=5630 + (151)100 = 20.7 k
This value is used to simplify the circuit, as in Fig, and the input resistance to Q10 is
[y11]1 = r10 + (o10 + 1)(50 kRin11)
= 189 k + (151)(50 k20.7 k) = 2.40 M
The gain of emitter follower Q10 is:

yielding a forward transconductance of y21 = 6.70 mS Parameters y12 and y22 can be found
from the network in Fig. We assume that the reverse transconductance y12 is negligible. The
output conductance y22 can be determined from Fig.

Using this model, the open-circuit voltage gain for the first two stages of the amplifier is
v2 = 0.00670(89.1 k)v1 = 597v1
v1 = 1.46 104(6.54 M2.40 M)vid = 256vid
v2 = 597(256vid) = 153,000vid

1.10 The 741 Output Stage:


Figure shows simplified models for the 741 output stage. Transistor Q12 is the emitter follower
that buffers the high impedance node at the output of the second stage and drives the push-pull
output stage composed of transistors Q15 and Q16. Class-AB bias is provided by the sum of the
base-emitter voltages of Q13 and Q14, represented as diodes in Fig.The 40-k resistor is used to

increase the value of IC13.Without this resistor, IC13 would only be equal to the base current of
Q14. The short-circuit protection circuitry in Fig is not shown in order to simplify the diagram.

The input and output resistances of the class-AB output stage are actually complicated functions
of the signal voltage because the operating current in Q15 and Q16 changes greatly as the output
voltage changes. However, because only one transistor conducts strongly at any given time in the
class-AB stage, separate circuit models can be used for positive and negative output signals. The
model for positive signal voltages is shown in Fig (The model for negative signal swings is
similar except npn transistor Q15 is replaced by pnp transistor Q16 connected to the emitter of
Q12.)
Using single-stage amplifier theory,
Rin12 = r12 + (o12 + 1)Req1 where
Req1 = rd14 + rd13 + R3Req2 and
Req2 = r15 + (o15 + 1) RL=(o15 + 1)RL
The value of R3 (344 k) was calculated in the bias circuit section. For IC12 = 216 A, and
assuming a representative collector current in Q15 of 2 mA,

Note that the value of Req2 is dominated by the reflected load resistance o15 RL.Resistor r15
represents a small part of Req2, and knowing the exact value of IC15 is not critical.

Similar results are obtained for negative signal voltages. The values are slightly different because
the current gain of the pnp transistor Q16 differs from that of the npn transistor Q15.

Output Resistance:
The output resistance of the amplifier for positive output voltages is determined by transistor
Q15

we can see that the 27 resistor R7, which determines the short-circuit current limit, adds
directly to the overall output resistance of the amplifier so that actual op-amp output resistance is

1.11 SHORT CIRCUIT PROTECTION CIRCUITRY:


For simplicity, the output short-circuit protection circuitry was not shown .Referring back to the
complete op amp schematic, we see that short-circuit protection is provided by resistors R7 and
R8 and transistors Q17 and Q18.Transistors Q17 and Q18 are normally off, but if the current in
resistor R7 becomes too high, then transistor Q17 turns on and steals the base current from Q15.
Likewise, if the current in resistor R8 becomes too large, then transistor Q18 turns on and
removes the base current from Q16. The positive and negative short-circuit current levels will be
limited to approximately VBE17/R7 and VEB18/R8, respectively. As already mentioned,
resistors R7 and R8 increase the output resistance of the amplifier since they appear directly in
series with the output terminal.

UNIT-2
2.1 OVERVIEW OF OP-AMP (IDEAL AND NONIDEAL):
Operational Amplifier Basics:
As well as resistors and capacitors, Operational Amplifiers, or Op-amps as they are more
commonly called, are one of the basic building blocks of Analogue Electronic Circuits.
Operational amplifiers are linear devices that have all the properties required for nearly ideal DC
amplification and are therefore used extensively in signal conditioning, filtering or to perform
mathematical operations such as add, subtract, integration and differentiation.
An ideal Operational Amplifier is basically a three-terminal device which consists of two high
impedance inputs, one called the Inverting Input, marked with a negative or minus sign, ( - )
and the other one called the Non-inverting Input, marked with a positive or plus sign ( + ).
The third terminal represents the Operational Amplifiers output port which can both sink and
source either a voltage or a current. In a linear operational amplifier, the output signal is the
amplification factor, known as the amplifiers gain ( A ) multiplied by the value of the input
signal and depending on the nature of these input and output signals, there can be four different
classifications of operational amplifier gain.

Voltage Voltage in and Voltage out

Current Current in and Current out

Transconductance Voltage in and Current out

Transresistance Current in and Voltage out

Since most of the circuits with operational amplifiers are voltage amplifiers, we will limit the
tutorials in this section to voltage amplifiers only, (Vin and Vout).
The amplified output signal of an Operational Amplifier is the difference between the two
signals being applid to the two inputs. In other words the output signal is a differential signal
between the two inputs and the input stage of an Operational Amplifier is in fact a differential
amplifier as shown below.
Differential Amplifier:
The circuit below shows a generalized form of a differential amplifier with two inputs
marked V1 andV2. The two identical transistors TR1 and TR2 are both biased at the same
operating point with their emitters connected together and returned to the common rail, -Vee by
way of resistor Re.

Differential Amplifier
The circuit operates from a dual supply +Vcc and-Vee which ensures a constant supply. The
voltage that appears at the output, Vout of the amplifier is the difference between the two input
signals as the two base inputs are in anti-phasewith each other.
So as the forward bias of transistor, TR1 is increased, the forward bias of transistor TR2 is
reduced and vice versa. Then if the two transistors are perfectly matched, the current flowing
through the common emitter resistor,Re will remain constant.
Like the input signal, the output signal is also balanced and since the collector voltages either
swing in opposite directions (anti-phase) or in the same direction (in-phase) the output voltage
signal, taken from between the two collectors is, assuming a perfectly balanced circuit the zero
difference between the two collector voltages.
This is known as the Common Mode of Operation with the common mode gain of the amplifier
being the output gain when the input is zero.
Ideal Operational Amplifiers also have one output (although there are ones with an additional
differential output) of low impedance that is referenced to a common ground terminal and it
should ignore any common mode signals that is, if an identical signal is applied to both the
inverting and non-inverting inputs there should no change to the output.
However, in real amplifiers there is always some variation and the ratio of the change to the
output voltage with regards to the change in the common mode input voltage is called
the Common Mode Rejection Ratio or CMRR.
Operational Amplifiers on their own have a very high open loop DC gain and by applying some
form of Negative Feedback we can produce an operational amplifier circuit that has a very
precise gain characteristic that is dependant only on the feedback used.
An operational amplifier only responds to the difference between the voltages on its two input
terminals, known commonly as the Differential Input Voltage and not to their common

potential. Then if the same voltage potential is applied to both terminals the resultant output will
be zero. An Operational Amplifiers gain is commonly known as the Open Loop Differential
Gain, and is given the symbol (Ao).
Equivalent Circuit for Ideal Operational Amplifiers

Op-amp Parameter and Idealized Characteristic

Open Loop Gain, (Avo)


o

Infinite The main function of an operational amplifier is to amplify the input signal
and the more open loop gain it has the better. Open-loop gain is the gain of the opamp without positive or negative feedback and for an ideal amplifier the gain will be
infinite but typical real values range from about 20,000 to 200,000.

Input impedance, (Zin)


o

Infinite Input impedance is the ratio of input voltage to input current and is
assumed to be infinite to prevent any current flowing from the source supply into the
amplifiers input circuitry ( Iin = 0 ). Real op-amps have input leakage currents from
a few pico-amps to a few milli-amps.

Output impedance, (Zout)

Bandwidth, (BW)
o

Zero The output impedance of the ideal operational amplifier is assumed to be zero
acting as a perfect internal voltage source with no internal resistance so that it can
supply as much current as necessary to the load. This internal resistance is
effectively in series with the load thereby reducing the output voltage available to
the load. Real op-amps have output-impedance in the 100-20 range.

Infinite An ideal operational amplifier has an infinite frequency response and can
amplify any frequency signal from DC to the highest AC frequencies so it is
therefore assumed to have an infinite bandwidth. With real op-amps, the bandwidth
is limited by the Gain-Bandwidth product (GB), which is equal to the frequency
where the amplifiers gain becomes unity.

Offset Voltage, (Vio)


o

Zero The amplifiers output will be zero when the voltage difference between the
inverting and the non-inverting inputs is zero, the same or when both inputs are
grounded. Real op-amps have some amount of output offset voltage.

From these idealized characteristics above, we can see that the input resistance is infinite,
so no current flows into either input terminal (the current rule) and that the differential input
offset voltage is zero (the voltage rule). It is important to remember these two properties as
they will help us understand the workings of the Operational Amplifier with regards to the
analysis and design of op-amp circuits.
However, real Operational Amplifiers such as the commonly available uA741, for example do
not have infinite gain or bandwidth but have a typical Open Loop Gain which is defined as the
amplifiers output amplification without any external feedback signals connected to it and for a
typical operational amplifier is about 100dB at DC (zero Hz). This output gain decreases linearly
with frequency down to Unity Gain or 1, at about 1MHz and this is shown in the following
open loop gain response curve.

Open-loop Frequency Response Curve

From this frequency response curve we can see that the product of the gain against frequency is
constant at any point along the curve. Also that the unity gain (0dB) frequency also determines
the gain of the amplifier at any point along the curve. This constant is generally known as
the Gain Bandwidth Product or GBP. Therefore:
GBP = Gain x Bandwidth or A x BW.
For example, from the graph above the gain of the amplifier at 100kHz is given as 20dB or 10,
then the gain bandwidth product is calculated as:
GBP = A x BW = 10 x 100,000Hz = 1,000,000.
Similarly, the operational amplifiers gain at 1kHz = 60dB or 1000, therefore the GBP is given as:
GBP = A x BW = 1,000 x 1,000Hz = 1,000,000. The same!.
The Voltage Gain (AV) of the operational amplifier can be found using the following formula:

and in Decibels or (dB) is given as:

An Operational Amplifiers Bandwidth


The operational amplifiers bandwidth is the frequency range over which the voltage gain of the
amplifier is above 70.7% or -3dB (where 0dB is the maximum) of its maximum output value as
shown below.

Here we have used the 40dB line as an example. The -3dB or 70.7% of Vmax down point from
the frequency response curve is given as 37dB. Taking a line across until it intersects with the
main GBP curve gives us a frequency point just above the 10kHz line at about 12 to 15kHz. We
can now calculate this more accurately as we already know the GBP of the amplifier, in this
particular case 1MHz.
Operational Amplifier Example No1.
Using the formula 20 log (A), we can calculate the bandwidth of the amplifier as:
37 = 20 log A therefore, A = anti-log (37 20) = 70.8
GBP A = Bandwidth, therefore, 1,000,000 70.8 = 14,124Hz, or 14kHz
Then the bandwidth of the amplifier at a gain of 40dB is given as 14kHz as previously predicted
from the graph.
Operational Amplifier Example No2.
If the gain of the operational amplifier was reduced by half to say 20dB in the above frequency
response curve, the -3dB point would now be at 17dB. This would then give the operational
amplifier an overall gain of 7.08, therefore A = 7.08.
If we use the same formula as above, this new gain would give us a bandwidth of
approximately141.2kHz, ten times more than the frequency given at the 40dB point. It can

therefore be seen that by reducing the overall open loop gain of an operational amplifier its
bandwidth is increased and visa versa.
In other words, an operational amplifiers bandwidth is proportional to its gain, ( A BW ). Also,
this -3dB point is generally known as the half power point, as the output power of the amplifier
is at half its maximum value at this value.
Operational Amplifiers Definition:
We know now that an Operational amplifiers is a very high gain DC differential amplifier that
uses one or more external feedback networks to control its response and characteristics. We can
connect external resistors or capacitors to the op-amp in a number of different ways to form basic
building Block circuits such as, Inverting, Non-Inverting, Voltage Follower, Summing,
Differential, Integrator and Differentiator type amplifiers.

Op-amp Symbol
An ideal or perfect Operational Amplifier is a device with certain special characteristics such
as infinite open-loop gain Ao, infinite input resistance Rin, zero output resistance Rout, infinite
bandwidth 0 to and zero offset (the output is exactly zero when the input is zero).
There are a very large number of operational amplifier ICs available to suit every possible
application from standard bipolar, precision, high-speed, low-noise, high-voltage, etc, in either
standard configuration or with internal Junction FET transistors.
Operational amplifiers are available in IC packages of either single, dual or quad op-amps within
one single device. The most commonly available and used of all operational amplifiers in basic
electronic kits and projects is the industry standard A-741.

2.2 The Inverting Operational Amplifier


We saw in the last tutorial that the Open Loop Gain, ( Avo ) of an ideal operational amplifier can
be very high, as much as 1,000,000 (120dB) or more. However, this very high gain is of no real
use to us as it makes the amplifier both unstable and hard to control as the smallest of input
signals, just a few micro-volts, (V) would be enough to cause the output voltage to saturate and
swing towards one or the other of the voltage supply rails losing complete control of the output.
As the open loop DC gain of an Operational Amplifiers is extremely high we can therefore
afford to lose some of this high gain by connecting a suitable resistor across the amplifier from
the output terminal back to the inverting input terminal to both reduce and control the overall
gain of the amplifier. This then produces and effect known commonly as Negative Feedback, and
thus produces a very stable Operational Amplifier based system.
Negative Feedback is the process of feeding back a fraction of the output signal back to the
input, but to make the feedback negative, we must feed it back to the negative or inverting
input terminal of the op-amp using an external Feedback Resistor called R. This feedback
connection between the output and the inverting input terminal forces the differential input
voltage towards zero.
This effect produces a closed loop circuit to the amplifier resulting in the gain of the amplifier
now being called its Closed-loop Gain. Then a closed-loop inverting amplifier uses negative
feedback to accurately control the overall gain of the amplifier, but at a cost in the reduction of
the amplifiers gain.
This negative feedback results in the inverting input terminal having a different signal on it than
the actual input voltage as it will be the sum of the input voltage plus the negative feedback
voltage giving it the label or term of a Summing Point. We must therefore separate the real input
signal from the inverting input by using an Input Resistor, Rin.
As we are not using the positive non-inverting input this is connected to a common ground or
zero voltage terminal as shown below, but the effect of this closed loop feedback circuit results
in the voltage potential at the inverting input being equal to that at the non-inverting input
producing aVirtual Earth summing point because it will be at the same potential as the grounded
reference input. In other words, the op-amp becomes a differential amplifier.

Inverting Operational Amplifier Configuration

In this Inverting Amplifier circuit the operational amplifier is connected with feedback to
produce a closed loop operation. When dealing with operational amplifiers there are two very
important rules to remember about ideal inverting amplifiers, these are: No current flows into
the input terminal and that V1 always equals V2. However, in real world op-amp circuits both
of these rules are slightly broken.
This is because the junction of the input and feedback signal ( X ) is at the same potential as the
positive ( + ) input which is at zero volts or ground then, the junction is a Virtual Earth.
Because of this virtual earth node the input resistance of the amplifier is equal to the value of the
input resistor,Rin and the closed loop gain of the inverting amplifier can be set by the ratio of the
two external resistors.
We said above that there are two very important rules to remember about Inverting Amplifiers or
any operational amplifier for that matter and these are.

1. No Current Flows into the Input Terminals

2. The Differential Input Voltage is Zero as V1 = V2 = 0 (Virtual Earth)


Then by using these two rules we can derive the equation for calculating the closed-loop gain of
an inverting amplifier, using first principles.

Current ( i ) flows through the resistor network as shown.

Then, the Closed-Loop Voltage Gain of an Inverting Amplifier is given as.

and this can be transposed to give Vout as:

Linear Output
The negative sign in the equation indicates an inversion of the output signal with respect to the
input as it is 180o out of phase. This is due to the feedback being negative in value.
The equation for the output voltage Vout also shows that the circuit is linear in nature for a fixed
amplifier gain as Vout = Vin x Gain. This property can be very useful for converting a smaller
sensor signal to a much larger voltage.
Another useful application of an inverting amplifier is that of a transresistance amplifier
circuit. A Transresistance Amplifier also known as a transimpedance amplifier, is basically a

current-to-voltage converter (Current in and Voltage out). They can be used in low-power
applications to convert a very small current generated by a photo-diode or photo-detecting device
etc, into a usable output voltage which is proportional to the input current as shown.
Transresistance Amplifier Circuit

The simple light-activated circuit above, converts a current generated by the photo-diode into a
voltage. The feedback resistor R sets the operating voltage point at the inverting input and
controls the amount of output. The output voltage is given as Vout = Is x R. Therefore, the
output voltage is proportional to the amount of input current generated by the photo-diode.
Inverting Op-amp Example No. 1
Find the closed loop gain of the following inverting amplifier circuit.

Using the previously found formula for the gain of the circuit

we can now substitute the values of the resistors in the circuit as follows,
Rin = 10k and R = 100k.
and the gain of the circuit is calculated as

-R/Rin = 100k/10k = -10.

therefore, the closed loop gain of the inverting amplifier circuit above is given 10 or 20dB (20log(10)).
Inverting Op-amp Example No2
The gain of the original circuit is to be increased to 40 (32dB), find the new values of the
resistors required.
Assume that the input resistor is to remain at the same value of 10K, then by re-arranging the
closed loop voltage gain formula we can find the new value required for the feedback
resistor R.
Gain = -R/Rin
therefore, R = Gain x Rin
R = 40 x 10,000
R = 400,000 or 400K
The new values of resistors required for the circuit to have a gain of 40 would be,
Rin = 10K and R = 400K.
The formula could also be rearranged to give a new value of Rin, keeping the same value of R.
One final point to note about the Inverting Amplifier configuration for an operational amplifier,
if the two resistors are of equal value, Rin = R then the gain of the amplifier will be 1 producing a complementary form of the input voltage at its output as Vout = -Vin. This type of
inverting amplifier configuration is generally called a Unity Gain Inverter of simply an Inverting
Buffer.
2.3 The Non-inverting Operational Amplifier
The second basic configuration of an operational amplifier circuit is that of a Non-inverting
Operational Amplifier. In this configuration, the input voltage signal, ( Vin ) is applied directly
to the non-inverting ( + ) input terminal which means that the output gain of the amplifier
becomes Positive in value in contrast to the Inverting Amplifier circuit we saw in the last
tutorial whose output gain is negative in value. The result of this is that the output signal is inphase with the input signal. Feedback control of the Non-inverting Operational Amplifier is
achieved by applying a small part of the output voltage signal back to the inverting ( - ) input
terminal via a R R2 voltage divider network, again producing negative feedback. This closedloop configuration produces a non-inverting amplifier circuit with very good stability, a very

high input impedance, Rin approaching infinity, as no current flows into the positive input
terminal, (ideal conditions) and a low output impedance, Rout as shown below.
Non-inverting Operational Amplifier Configuration

In the previous Inverting Amplifier tutorial, we said that for an ideal op-amp No current flows
into the input terminal of the amplifier and that V1 always equals V2. This was because the
junction of the input and feedback signal ( V1 ) are at the same potential.
In other words the junction is a virtual earth summing point. Because of this virtual earth node
the resistors, R and R2 form a simple potential divider network across the non-inverting
amplifier with the voltage gain of the circuit being determined by the ratios of R2 and R as
shown below.
Equivalent Potential Divider Network

Then using the formula to calculate the output voltage of a potential divider network, we can
calculate the closed-loop voltage gain ( A V ) of the Non-inverting Amplifier as follows:

Then the closed loop voltage gain of a Non-inverting Operational Amplifier will be given as:

We can see from the equation above, that the overall closed-loop gain of a non-inverting
amplifier will always be greater but never less than one (unity), it is positive in nature and is
determined by the ratio of the values of R and R2.
If the value of the feedback resistor R is zero, the gain of the amplifier will be exactly equal to
one (unity). If resistor R2 is zero the gain will approach infinity, but in practice it will be limited
to the operational amplifiers open-loop differential gain, ( Ao ).
We can easily convert an inverting operational amplifier configuration into a non-inverting
amplifier configuration by simply changing the input connections as shown.

Voltage Follower (Unity Gain Buffer)

If we made the feedback resistor, R equal to zero, (R = 0), and resistor R2 equal to infinity,
(R2 = ), then the circuit would have a fixed gain of 1 as all the output voltage would be
present on the inverting input terminal (negative feedback). This would then produce a special
type of the non-inverting amplifier circuit called a Voltage Follower or also called a unity gain
buffer. As the input signal is connected directly to the non-inverting input of the amplifier the
output signal is not inverted resulting in the output voltage being equal to the input voltage, Vout
= Vin. This then makes the voltage follower circuit ideal as a Unity Gain Buffer circuit because
of its isolation properties.
The advantage of the unity gain voltage follower is that it can be used when impedance matching
or circuit isolation is more important than amplification as it maintains the signal voltage. The
input impedance of the voltage follower circuit is very high, typically above 1M as it is equal
to that of the operational amplifiers input resistance times its gain ( Rin x Ao ). Also its output
impedance is very low since an ideal op-amp condition is assumed.
Non-inverting Voltage Follower

In this non-inverting circuit configuration, the input impedance Rin has increased to infinity and
the feedback impedance R reduced to zero. The output is connected directly back to the
negative inverting input so the feedback is 100% and Vin is exactly equal to Vout giving it a
fixed gain of 1 or unity. As the input voltage Vin is applied to the non-inverting input the gain of
the amplifier is given as:

Since no current flows into the non-inverting input terminal the input impedance is infinite (ideal
op-amp) and also no current flows through the feedback loop so any value of resistance may be
placed in the feedback loop without affecting the characteristics of the circuit as no voltage is
dissipated across it, zero current flows, zero voltage drop, zero power loss.
Since the input current is zero giving zero input power, the voltage follower can provide a large
power gain. However in most real unity gain buffer circuits a low value (typically 1k) resistor

is required to reduce any offset input leakage currents, and also if the operational amplifier is of a
current feedback type.
The voltage follower or unity gain buffer is a special and very useful type of Non-inverting
amplifier circuit that is commonly used in electronics to isolated circuits from each other
especially in High-order state variable or Sallen-Key type active filters to separate one filter
stage from the other. Typical digital buffer ICs available are the 74LS125 Quad 3-state buffer or
the more common 74LS244 Octal buffer.
One final thought, the closed loop voltage gain of a voltage follower circuit is 1 or Unity. The
open loop voltage gain of an ideal operational amplifier with no feedback is Infinite. Then by
carefully selecting the feedback components we can control the amount of gain produced by a
non-inverting operational amplifier anywhere from one to infinity.
2.4 Differential Amplifier
Thus far we have used only one of the operational amplifiers inputs to connect to the amplifier,
using either the inverting or the non-inverting input terminal to amplify a single input signal
with the other input being connected to ground. But we can also connect signals to both of the
inputs at the same time producing another common type of operational amplifier circuit called
a Differential Amplifier.
Basically, as we saw in the first tutorial about Operational Amplifiers, all op-amps are
Differential Amplifiers due to their input configuration. But by connecting one voltage signal
onto one input terminal and another voltage signal onto the other input terminal the resultant
output voltage will be proportional to the Difference between the two input voltage signals
of V1 and V2.
Then differential amplifiers amplify the difference between two voltages making this type of
operational amplifier circuit a Subtractor unlike a summing amplifier which adds or sums
together the input voltages. This type of operational amplifier circuit is commonly known as
a Differential Amplifier configuration and is shown below:
Differential Amplifier

By connecting each input in turn to 0v ground we can use superposition to solve for the output
voltage Vout. Then the transfer function for a Differential Amplifier circuit is given as:

When resistors, R1 = R2 and R3 = R4 the above transfer function for the differential amplifier
can be simplified to the following expression:
Differential Amplifier Equation

If all the resistors are all of the same ohmic value, that is: R1 = R2 = R3 = R4 then the circuit
will become a Unity Gain Differential Amplifier and the voltage gain of the amplifier will be
exactly one or unity. Then the output expression would simply be Vout = V2 - V1. Also note that
if input V1 is higher than input V2 the output voltage sum will be negative, and if V2 is higher
than V1, the output voltage sum will be positive.

The Differential Amplifier circuit is a very useful op-amp circuit and by adding more resistors in
parallel with the input resistors R1 and R3, the resultant circuit can be made to either Add or
Subtract the voltages applied to their respective inputs. One of the most common ways of
doing this is to connect a Resistive Bridge commonly called a Wheatstone Bridge to the input
of the amplifier as shown below.
Wheatstone Bridge Differential Amplifier

The standard Differential Amplifier circuit now becomes a differential voltage comparator by
Comparing one input voltage to the other. For example, by connecting one input to a fixed
voltage reference set up on one leg of the resistive bridge network and the other to either a
Thermistor or a Light Dependant Resistor the amplifier circuit can be used to detect either
low or high levels of temperature or light as the output voltage becomes a linear function of the
changes in the active leg of the resistive bridge and this is demonstrated below.
Light Activated Differential Amplifier

Here the circuit above acts as a light-activated switch which turns the output relay either ON or
OFF as the light level detected by the LDR resistor exceeds or falls below a pre-set value
at V2determined by the position of VR1. A fixed voltage reference is applied to the inverting
input terminal V1 via the R1 R2 voltage divider network and the variable voltage (proportional
to the light level) applied to the non-inverting input terminal V2. It is also possible to detect
temperature using this type of circuit by simply replacing the Light Dependant Resistor (LDR)

with a thermistor. By interchanging the positions of VR1 and the LDR, the circuit can be used to
detect either light or dark, or heat or cold using a thermistor.
One major limitation of this type of amplifier design is that its input impedances are lower
compared to that of other operational amplifier configurations, for example, a non-inverting
(single-ended input) amplifier. Each input voltage source has to drive current through an input
resistance, which has less overall impedance than that of the op-amps input alone. This may be
good for a low impedance source such as the bridge circuit above, but not so good for a high
impedance source.
One way to overcome this problem is to add a Unity Gain Buffer Amplifier such as the voltage
follower seen in the previous tutorial to each input resistor. This then gives us a differential
amplifier circuit with very high input impedance and low output impedance as it consists of two
non-inverting buffers and one differential amplifier. This then forms the basis for most
Instrumentation Amplifiers.
2.5 Instrumentation Amplifier
Instrumentation Amplifiers (in-amps) are very high gain differential amplifiers which have a
high input impedance and a single ended output. Instrumentation amplifiers are mainly used to
amplify very small differential signals from strain gauges, thermocouples or current sensing
devices in motor control systems. Unlike standard operational amplifiers in which their closedloop gain is determined by an external resistive feedback connected between their output
terminal and one input terminal, either positive or negative, instrumentation amplifiers have an
internal feedback resistor that is effectively isolated from its input terminals as the input signal
is applied across two differential inputs, V1 and V2. The instrumentation amplifier also has a
very good common mode rejection ratio, CMRR (zero output when V1 = V2) well in excess of
100dB at DC. A typical example of a three op-amp instrumentation amplifier with a high input
impedance ( Zin ) is given below:
High Input Impedance Instrumentation Amplifier

The two non-inverting amplifiers form a differential input stage acting as buffer amplifiers with a
gain of 1 + 2R2/R1 for differential input signals and unity gain for common mode input signals.
Since amplifiers A1 and A2 are closed loop negative feedback amplifiers, we can expect the
voltage at Va to be equal to the input voltage V1. Likewise, the voltage at Vb to be equal to the
value at V2.
As the op-amps take no current at their input terminals (virtual earth), the same current must
flow through the three resistor network of R2, R1 and R2 connected across the op-amp outputs.
This means then that the voltage on the upper end of R1 will be equal to V1 and the voltage at
the lower end of R1 to be equal to V2.
This produces a voltage drop across resistor R1 which is equal to the voltage difference between
inputs V1 and V2 , the differential input voltage, because the voltage at the summing junction of
each amplifier, Va and Vb is equal to the voltage applied to its positive inputs.
However, if a common-mode voltage is applied to the amplifiers inputs, the voltages on each
side ofR1 will be equal, and no current will flow through this resistor. Since no current flows
through R1 (nor, therefore, through both R2 resistors, amplifiers A1 and A2 will operate as
unity-gain followers (buffers). Since the input voltage at the outputs of
amplifiers A1 and A2 appears differentially across the three resistor network, the differential
gain of the circuit can be varied by just changing the value of R1.
The voltage output from the differential op-amp A3 acting as a subtractor, is simply the
difference between its two inputs ( V2 - V1 ) and which is amplified by the gain of A3 which
may be one, unity, (assuming that R3 = R4). Then we have a general expression for overall
voltage gain of the instrumentation amplifier circuit as:
Instrumentation Amplifier Equation

In the next tutorial about Operational Amplifiers, we will examine the effect of the output
voltage, Vout when the feedback resistor is replaced with a frequency dependant reactance in the
form of a capacitance. The addition of this feedback capacitance produces a non-linear
operational amplifier circuit called an Integrating Amplifier.
2.6 The Op-amp Differentiator Amplifier
The basic Op-amp Differentiator circuit is the exact opposite to that of the Integrator
Amplifier circuit that we looked at in the previous tutorial. Here, the position of the capacitor and
resistor have been reversed and now the reactance, Xc is connected to the input terminal of the
inverting amplifier while the resistor, R forms the negative feedback element across the
operational amplifier as normal.
This Operational Amplifier circuit performs the mathematical operation of Differentiation, that
is it produces a voltage output which is directly proportional to the input voltages rate-ofchange with respect to time. In other words the faster or larger the change to the input voltage

signal, the greater the input current, the greater will be the output voltage change in response,
becoming more of a spike in shape.
As with the integrator circuit, we have a resistor and capacitor forming an RC Network across
the operational amplifier and the reactance ( Xc ) of the capacitor plays a major role in the
performance of a Op-amp Differentiator.
Op-amp Differentiator Circuit

The input signal to the differentiator is applied to the capacitor. The capacitor blocks any DC
content so there is no current flow to the amplifier summing point, X resulting in zero output
voltage. The capacitor only allows AC type input voltage changes to pass through and whose
frequency is dependent on the rate of change of the input signal.
At low frequencies the reactance of the capacitor is High resulting in a low gain ( R/Xc ) and
low output voltage from the op-amp. At higher frequencies the reactance of the capacitor is much
lower resulting in a higher gain and higher output voltage from the differentiator amplifier.
However, at high frequencies an op-amp differentiator circuit becomes unstable and will start to
oscillate. This is due mainly to the first-order effect, which determines the frequency response of
the op-amp circuit causing a second-order response which, at high frequencies gives an output
voltage far higher than what would be expected. To avoid this high frequency gain of the circuit
needs to be reduced by adding an additional small value capacitor across the feedback
resistor R.
Ok, some maths to explain whats going on!. Since the node voltage of the operational amplifier
at its inverting input terminal is zero, the current, i flowing through the capacitor will be given
as:

The charge on the capacitor equals Capacitance x Voltage across the capacitor

The rate of change of this charge is

but dQ/dt is the capacitor current i

from which we have an ideal voltage output for the op-amp differentiator is given as:

Therefore, the output voltage Vout is a constant -R.C times the derivative of the input
voltage Vinwith respect to time. The minus sign indicates a 180o phase shift because the input
signal is connected to the inverting input terminal of the operational amplifier.
One final point to mention, the Op-amp Differentiator circuit in its basic form has two main
disadvantages compared to the previous Operational Amplifier Integrator circuit. One is that it
suffers from instability at high frequencies as mentioned above, and the other is that the
capacitive input makes it very susceptible to random noise signals and any noise or harmonics
present in the source circuit will be amplified more than the input signal itself. This is because
the output is proportional to the slope of the input voltage so some means of limiting the
bandwidth in order to achieve closed-loop stability is required
2.6.1 Op-amp Differentiator Waveforms
If we apply a constantly changing signal such as a Square-wave, Triangular or Sine-wave type
signal to the input of a differentiator amplifier circuit the resultant output signal will be changed
and whose final shape is dependant upon the RC time constant of the Resistor/Capacitor
combination.

Improved Op-amp Differentiator Amplifier (Practical)


The basic single resistor and single capacitor op-amp differentiator circuit is not widely used to
reform the mathematical function of Differentiation because of the two inherent faults mentioned
above, Instability and Noise. So in order to reduce the overall closed-loop gain of the circuit
at high frequencies, an extra resistor, Rin is added to the input as shown below.
Improved Op-amp Differentiator Amplifier

Adding the input resistor Rin limits the differentiators increase in gain at a ratio of R/Rin. The
circuit now acts like a differentiator amplifier at low frequencies and an amplifier with resistive
feedback at high frequencies giving much better noise rejection. Additional attenuation of higher
frequencies is accomplished by connecting a capacitor C in parallel with the differentiator
feedback resistor, R. This then forms the basis of a Active High Pass Filter as we have seen
before in the filters section.
2.7 The Op-amp Integrating Amplifier
In the previous tutorials we have seen circuits which show how an operational amplifier can be
used as part of a positive or negative feedback amplifier or as an adder or subtractor type circuit
using just pure resistances in both the input and the feedback loop. But what if we were to
change the purely resistive ( R ) feedback element of an inverting amplifier to that of a
frequency dependant impedance, ( Z ) type complex element, such as a Capacitor, C. What
would be the effect on the op-amps output voltage over its frequency range.
By replacing this feedback resistance with a capacitor we now have an RC Network connected
across the operational amplifiers feedback path producing another type of operational amplifier
circuit commonly called an Op-amp Integrator circuit as shown below.
Op-amp Integrator Circuit

As its name implies, the Op-amp Integrator is an Operational Amplifier circuit that performs the
mathematical operation of Integration, that is we can cause the output to respond to changes in
the input voltage over time as the op-amp integrator produces an output voltage which is
proportional to the integral of the input voltage.
In other words the magnitude of the output signal is determined by the length of time a voltage is
present at its input as the current through the feedback loop charges or discharges the capacitor
as the required negative feedback occurs through the capacitor.
When a step voltage, Vin is firstly applied to the input of an integrating amplifier, the uncharged
capacitor C has very little resistance and acts a bit like a short circuit allowing maximum current
to flow via the input resistor, Rin as potential difference exists between the two plates. No
current flows into the amplifiers input and point X is a virtual earth resulting in zero output. As
the impedance of the capacitor at this point is very low, the gain ratio of Xc/Rin is also very
small giving an overall voltage gain of less than one, ( voltage follower circuit ).

As the feedback capacitor, C begins to charge up due to the influence of the input voltage, its
impedance Xc slowly increase in proportion to its rate of charge. The capacitor charges up at a
rate determined by the RC time constant, ( ) of the series RC network. Negative feedback
forces the op-amp to produce an output voltage that maintains a virtual earth at the op-amps
inverting input.
Since the capacitor is connected between the op-amps inverting input (which is at earth
potential) and the op-amps output (which is negative), the potential voltage, Vc developed
across the capacitor slowly increases causing the charging current to decrease as the impedance
of the capacitor increases. This results in the ratio of Xc/Rin increasing producing a linearly
increasing ramp output voltage that continues to increase until the capacitor is fully charged.
At this point the capacitor acts as an open circuit, blocking any more flow of DC current. The
ratio of feedback capacitor to input resistor ( Xc/Rin ) is now infinite resulting in infinite gain.
The result of this high gain (similar to the op-amps open-loop gain), is that the output of the
amplifier goes into saturation as shown below. (Saturation occurs when the output voltage of the
amplifier swings heavily to one voltage supply rail or the other with little or no control in
between).

The rate at which the output voltage increases (the rate of change) is determined by the value of
the resistor and the capacitor, RC time constant. By changing this RC time constant value,
either by changing the value of the Capacitor, C or the Resistor, R, the time in which it takes the
output voltage to reach saturation can also be changed for example.

If we apply a constantly changing input signal such as a square wave to the input of an Integrator
Amplifier then the capacitor will charge and discharge in response to changes in the input signal.

This results in the output signal being that of a sawtooth waveform whose frequency is
dependant upon the RC time constant of the resistor/capacitor combination. This type of circuit
is also known as a Ramp Generator and the transfer function is given below.
Op-amp Integrator Ramp Generator

We know from first principals that the voltage on the plates of a capacitor is equal to the charge
on the capacitor divided by its capacitance giving Q/C. Then the voltage across the capacitor is
output Vout therefore: -Vout = Q/C. If the capacitor is charging and discharging, the rate of
charge of voltage across the capacitor is given as:

But dQ/dt is electric current and since the node voltage of the integrating op-amp at its inverting
input terminal is zero, X = 0, the input current I(in) flowing through the input resistor, Rin is
given as:

The current flowing through the feedback capacitor C is given as:

Assuming that the input impedance of the op-amp is infinite (ideal op-amp), no current flows
into the op-amp terminal. Therefore, the nodal equation at the inverting input terminal is given
as:

From which we derive an ideal voltage output for the Op-amp Integrator as:

To simplify the maths a little, this can also be re-written as:

Where = 2 and the output voltage Vout is a constant 1/RC times the integral of the input
voltageVin with respect to time. The minus sign ( - ) indicates a 180o phase shift because the
input signal is connected directly to the inverting input terminal of the op-amp.
The AC or Continuous Op-amp Integrator (Practical)
If we changed the above square wave input signal to that of a sine wave of varying frequency
the Op-amp Integrator performs less like an integrator and begins to behave more like an active
Low Pass Filter, passing low frequency signals while attenuating the high frequencies.
At 0Hz or DC, the capacitor acts like an open circuit blocking any feedback voltage resulting in
very little negative feedback from the output back to the input of the amplifier. Then with just the
feedback capacitor, C, the amplifier effectively is connected as a normal open-loop amplifier
which has very high open-loop gain resulting in the output voltage saturating.
This circuit connects a high value resistance in parallel with a continuously charging and
discharging capacitor. The addition of this feedback resistor, R2 across the capacitor, C gives the
circuit the characteristics of an inverting amplifier with finite closed-loop gain of R2/R1. The
result is at very low frequencies the circuit acts as an standard integrator, while at higher
frequencies the capacitor shorts out the feedback resistor, R2 due to the effects of capacitive
reactance reducing the amplifiers gain.
The AC Op-amp Integrator with DC Gain Control

Unlike the DC integrator amplifier above whose output voltage at any instant will be the integral
of a waveform so that when the input is a square wave, the output waveform will be triangular.
For an AC integrator, a sinusoidal input waveform will produce another sine wave as its output
which will be 90oout-of-phase with the input producing a cosine wave.
Furthermore, when the input is triangular, the output waveform is also sinusoidal. This then
forms the basis of a Active Low Pass Filter as seen before in the filters section tutorials with a
corner frequency given as.

2.8 The Summing Amplifier


The Summing Amplifier is a very flexible circuit based upon the standard Inverting Operational
Amplifier configuration. As its name suggests, the summing amplifier can be used for
combining the voltage present on multiple inputs into a single output voltage.
We saw previously in the Inverting Operational Amplifier that the inverting amplifier has a
single input voltage, ( Vin ) applied to the inverting input terminal. If we add more input resistors
to the input, each equal in value to the original input resistor, Rin we end up with another
operational amplifier circuit called a Summing Amplifier, summing inverter or even a voltage
adder circuit as shown below.

Summing Amplifier Circuit

The output voltage, ( Vout ) now becomes proportional to the sum of the input
voltages, V1, V2, V3etc. Then we can modify the original equation for the inverting amplifier to
take account of these new inputs thus:

However, if all the input impedances, ( Rin ) are equal in value, we can simplify the above
equation to give an output voltage of:
Summing Amplifier Equation

We now have an operational amplifier circuit that will amplify each individual input voltage and
produce an output voltage signal that is proportional to the algebraic SUM of the three
individual input voltages V1, V2 and V3. We can also add more inputs if required as each
individual input sees their respective resistance, Rin as the only input impedance.
This is because the input signals are effectively isolated from each other by the virtual earth
node at the inverting input of the op-amp. A direct voltage addition can also be obtained when all
the resistances are of equal value and R is equal to Rin.
A Scaling Summing Amplifier can be made if the individual input resistors are NOT equal.
Then the equation would have to be modified to:

To make the maths a little easier, we can rearrange the above formula to make the feedback
resistorRF the subject of the equation giving the output voltage as:

This allows the output voltage to be easily calculated if more input resistors are connected to the
amplifiers inverting input terminal. The input impedance of each individual channel is the value
of their respective input resistors, ie, R1, R2, R3 etc.
The Summing Amplifier is a very flexible circuit indeed, enabling us to effectively Add or
Sum (hence its name) together several individual input signals. If the inputs
resistors, R1, R2, R3 etc, are all equal a unity gain inverting adder can be made. However, if the
input resistors are of different values a scaling summing amplifier is produced which gives a
weighted sum of the input signals.

Summing Amplifier Example No. 1


Find the output voltage of the following Summing Amplifier circuit.
Summing Amplifier

Using the previously found formula for the gain of the circuit

we can now substitute the values of the resistors in the circuit as follows,

we know that the output voltage is the sum of the two amplified input signals and is calculated
as:

then the output voltage of the Summing Amplifier circuit above is given as -45 mV and is
negative as its an inverting amplifier.
Summing Amplifier Applications
So what can we use summing amplifiers for?. If the input resistances of a summing amplifier are
connected to potentiometers the individual input signals can be mixed together by varying
amounts. For example, measuring temperature, you could add a negative offset voltage to make
the output voltage or display read 0 at the freezing point or produce an audio mixer for adding
or mixing together individual waveforms (sounds) from different source channels (vocals,
instruments, etc) before sending them combined to an audio amplifier.
Summing Amplifier Audio Mixer

Another useful application of a Summing Amplifier is as a weighted sum digital-to-analogue


converter. If the input resistors, Rin of the summing amplifier double in value for each input, for
example, 1k, 2k, 4k, 8k, 16k, etc, then a digital logical voltage, either a logic level 0
or a logic level 1 on these inputs will produce an output which is the weighted sum of the
digital inputs. Consider the circuit below.\

Digital to Analogue Converter

Of course this is a simple example. In this DAC summing amplifier circuit, the number of
individual bits that make up the input data word, and in this example 4-bits, will ultimately
determine the output step voltage as a percentage of the full-scale analogue output voltage.
Also, the accuracy of this full-scale analogue output depends on voltage levels of the input bits
being consistently 0V for 0 and consistently 5V for 1 as well as the accuracy of the
resistance values used for the input resistors, Rin.
Fortunately to overcome these errors, at least on our part, commercially available Digital-to
Analogue and Analogue-to Digital devices are readily available with highly accurate resistor
ladder networks already built-in.

2.9 Operational Amplifiers Summary


We can conclude our section and look at Operational Amplifiers with the following summary of
the different types of Op-amp circuits and their different configurations discussed throughout this
op-amp tutorial section.
Operational Amplifier General Conditions

The Operational Amplifier, or Op-amp as it is most commonly called, is an ideal


amplifier with infinite Gain and Bandwidth when used in the Open-loop mode with typical
DC gains of well over 100,000, or 100dB.

The basic Op-amp construction is of a 3-terminal device, 2-inputs and 1-output,


(excluding power connections).

An Operational Amplifier operates from either a dual positive ( +V ) and an corresponding


negative ( -V ) supply, or they can operate from a single DC supply voltage.

The two main laws associated with the operational amplifier are that it has an infinite input
impedance, ( Z ) resulting in No current flowing into either of its two inputs and zero
input offset voltage V1 = V2.

An operational amplifier also has zero output impedance, ( Z = 0 ).


Op-amps sense the difference between the voltage signals applied to their two input
terminals and then multiply it by some pre-determined Gain, ( A ).

This Gain, ( A ) is often referred to as the amplifiers Open-loop Gain.


Closing the open loop by connecting a resistive or reactive component between the output
and one input terminal of the op-amp greatly reduces and controls this open-loop gain.

Op-amps can be connected into two basic configurations, Inverting and Non-inverting.

The Two Basic Operational Amplifier Circuits

For negative feedback, were the fed-back voltage is in anti-phase to the input the overall
gain of the amplifier is reduced.

For positive feedback, were the fed-back voltage is in Phase with the input the overall
gain of the amplifier is increased.

By connecting the output directly back to the negative input terminal, 100% feedback is
achieved resulting in a Voltage Follower (buffer) circuit with a constant gain of 1 (Unity).

Changing the fixed feedback resistor ( R ) for a Potentiometer, the circuit will have
Adjustable Gain.
Operational Amplifier Gain

The Open-loop gain called the Gain Bandwidth Product, or (GBP) can be very high and is
a measure of how good an amplifier is.

Very high GBP makes an operational amplifier circuit unstable as a micro volt input signal
causes the output voltage to swing into saturation.

By the use of a suitable feedback resistor, ( R ) the overall gain of the amplifier can be
accurately controlled.
Differential and Summing Amplifiers

By adding more input resistors to either the inverting or non-inverting inputs Voltage
Adders or Summers can be made.

Voltage follower op-amps can be added to the inputs of Differential amplifiers to produce
high impedance Instrumentation amplifiers.

The Differential Amplifier produces an output that is proportional to the difference


between the 2 input voltages.
Differentiator and Integrator Operational Amplifier Circuits

The Integrator Amplifier produces an output that is the mathematical operation of


integration.

The Differentiator Amplifier produces an output that is the mathematical operation of


differentiation.

Both the Integrator and Differentiator Amplifiers have a resistor and capacitor connected
across the op-amp and are affected by its RC time constant.

In their basic form, Differentiator Amplifiers suffer from instability and noise but
additional components can be added to reduce the overall closed-loop gain.

2.10 V-I and I-V CONVERTERS


Voltage to Current converter
A voltage to current (V-I) converter accepts as an input a voltage Vin and gives an output current
of a certain value. In general the relationship between the input voltage and the output current

Where S is the sensitivity or gain of the V-I converter.


Figure below shows a voltage to current converter using an op-amp and a transistor. The op-amp
forces its positive and negative inputs to be equal; hence, the voltage at the negative input of the

op-amp is equal to Vin. The current through the load resistor, RL, the transistor and R is
consequently equal to Vin/R. We put a transistor at the output of the op-amp since the transistor
is a high current gain stage (often a typical op-amp has a fairly small output current limit).

V-I Converter Circuit


In this cricuit below, the load is not grounded but takes the place of the feedback resistor. Since
the inverting input is virtual ground

V-I Converter with Floating Load

Current to voltage converters


A variety of transducers produce electrical current in response to an environmental condition.
Photodiodes and photomultipliers are such transducers which respond to electromagnetic
radiation at various frequencies ranging from the infrared to visible to -rays.
A current to voltage converter is an op amp circuit which accepts an input current and gives an
output voltage that is proportional to the input current. The basic current to voltage converter is
shown on figure below. This circuit arrangement is also called the transresistance amplifier.

I-V Converter Circuit


Iin represents the current generated by a certain transducer. If we assume that the op amp is ideal,
KCL at node N1 gives

The gain of this amplifier is given by R. This gain is also called the sensitivity of the converter.
Note that if high sensitivity is required for example 1V/V then the resistance R should be 1
M. For higher sensitivities unrealistically large resistances are required.
A current to voltage converter with high sensitivity may be constructed by employing the T
feedback network topology shown on figure below. In this case the relationship between Vout
and Il is

I-V Converter with T Network


2.11 GENERALIZED IMPEDANCE CONVERTER / SIMULATION OF INDUCTOR:
The Negative Impedance Converter
Although it is not an amplifier, the negative impedance converter is an application of the noninverting configuration. For the circuit in Fig. (a), the resistor R bridges the input and output
terminals of a non-inverting amplifier. We can write the solution for rin

Thus the circuit has a negative input resistance.

Negative impedance converters. (a) Negative input resistance. (b) Negative input capacitance
A resistor in parallel with another resistor equal to its negative is an open circuit. It follows that
the output resistance of a non-ideal current source. i.e. one having a non-infinite output
resistance, can be made infinite by adding a negative resistance in parallel with the current
source. Negative resistors do not absorb power from a circuit. Instead, they supply power. For
example, if a capacitor with an initial voltage on it is connected in parallel with a negative
resistor, the voltage on the capacitor will increase with time. Relaxation oscillators are waveform
generator circuits which use a negative resistance in parallel with a capacitor to generate ac
waveforms.
The resistor is replaced with a capacitor in Fig. (b). In this case, the input impedance is

It follows that the input impedance is that of a frequency dependent inductor given by

Simulation of Inductor
SECOND-ORDER ACTIVE FILTERS BASED ON INDUCTOR REPLACEMENT
In this section, we study a family of op amp-RC circuits that realize the various second-order
filter functions. The circuits are based on an op a m p - RC resonator obtained by replacing the
inductor L in the LCR resonator with an op amp-RC circuit that has an inductive input
impedance.
The Antoniou Inductance-Simulation Circuit: Over the years, many op amp-RC circuits have
been proposed for simulating the operation of an inductor. Of these, one circuit invented by A.
Antoniou5 [see Antoniou (1969)] has proved to b e the "best." By "best" we mean that the
operation of the circuit is very tolerant of the nonideal properties of the op amps, in particular
their finite gain and bandwidth. Figure shows the Antoniou inductance-simulation circuit. If the

circuit is fed at its input (node 1) with a voltage source Vx and the input current is denoted Iu
then for ideal.

op amps the input impedance can be shown to be

which is that of an inductance L given by

Figure (b) shows the analysis of the circuit assuming that the op amps are ideal and thus that a
virtual short circuit appears between the two input terminals of each op amp, and assuming also
that the input currents of the op amps are zero. The analysis begins at node 1, which is assumed
to be fed by a voltage source Vh and proceeds step by step, with the order of the steps indicated
by the circled numbers. The result of the analysis is the expression shown for the input current Iin
from which Zin is found. The design of this circuit is usually based on selecting Rx= R2- R3 = R5
= R and C 4 = C, which leads to L = CR2. Convenient values are then selected for C and R to
yield the desired inductance value L.

Inductor Simulation using Gyrator


A gyrator can be used to transform a load capacitance into an inductance. At low frequencies and
low powers, the behavior of the gyrator can be reproduced by a small op-amp circuit. This
supplies a means of providing an inductive element in a small electronic circuit or integrated
circuit. Before the invention of the transistor, coils of wire with large inductance might be used
in electronic filters. An inductor can be replaced by a much smaller assembly containing a

capacitor, operational amplifiers or transistors, and resistors. This is especially useful in


integrated circuit technology.
Operation: In the circuit shown, one port of the gyrator is between the input terminal and
ground, while the other port is terminated with the capacitor. The circuit works by inverting and
multiplying the effect of the capacitor in an RC differentiating circuit where the voltage across
the resistor behaves through time in the same manner as the voltage across an inductor. The opamp follower buffers this voltage and applies it back to the input through the resistor RL. The
desired effect is an impedance of the form of an ideal inductor L with a series resistance RL:

From the diagram, the input impedance of the op-amp circuit is:

With RLRC = L, it can be seen that the impedance of the simulated inductor is the desired
impedance in parallel with the impedance of the RC circuit. In typical designs, R is chosen to be
sufficiently large such that the first term dominates; thus, the RC circuit's impact on input
impedance is negligible.

This is the same as a resistance RL in series with an inductance L = RLRC. There is a practical
limit on the minimum value that RL can take, determined by the current output capability of the
op amp.

An example of a gyrator simulating inductance, with an approximate equivalent circuit below.


The two Zin have similar values in typical applications
Comparison with actual inductors: Simulated elements only imitate actual elements as in fact
they are dynamic voltage sources. They cannot replace them in all the possible applications as
they do not possess all their unique properties. So, the simulated inductor only mimics some
properties of the real inductor.
Magnitudes: In typical applications, both the inductance and the resistance of the gyrator are
much greater than that of a physical inductor. Gyrators can be used to create inductors from the
micro henry range up to the mega henry range. Physical inductors are typically limited to tens of
henries, and have parasitic series resistances from hundreds of micro ohms through the low kilo
ohm range. The parasitic resistance of a gyrator depends on the topology, but with the topology
shown, series resistances will typically range from tens of ohms through hundreds of kilo ohms.
Quality: Physical capacitors are often much closer to "ideal capacitors" than physical inductors
are to "ideal inductors". Because of this, a synthesized inductor realized with a gyrator and a
capacitor may, for certain applications, be closer to an "ideal inductor" than any (practical)
physical inductor can be. Thus, use of capacitors and gyrators may improve the quality of filter
networks that would otherwise be built using inductors. Also, the Q factor of a synthesized
inductor can be selected with ease. The Q of an LC filter can be either lower or higher than that
of an actual LC filter for the same frequency, the inductance is much higher, the capacitance
much lower, but the resistance also higher. Gyrator inductors typically have higher accuracy than
physical inductors, due to the lower cost of precision capacitors than inductors.
Energy storage: Simulated inductors do not have the inherent energy storing properties of the
real inductors and this limits the possible power applications. The circuit cannot respond like a
real inductor to sudden input changes (it does not produce a high-voltage back EMF); its voltage
response is limited by the power supply. Since gyrators use active circuits, they only function as
a gyrator within the power supply range of the active element. Hence gyrators are usually not
very useful for situations requiring simulation of the 'flyback' property of inductors, where a
large voltage spike is caused when current is interrupted. A gyrator's transient response is limited
by the bandwidth of the active device in the circuit and by the power supply.
Externalities: Simulated inductors do not react to external magnetic fields and permeable
materials the same way that real inductors do. They also don't create magnetic fields (and induce
currents in external conductors) the same way that real inductors do. This limits their use in
applications such as sensors, detectors and transducers.
Grounding: The fact that one side of the simulated inductor is grounded restricts the possible
applications (real inductors are floating). This limitation may preclude its use in some low-pass
and notch filters.[9] However the gyrator can be used in a floating configuration with another
gyrator so long as the floating "grounds" are tied together. This allows for a floating gyrator, but
the inductance simulated across the input terminals of the gyrator pair must be cut in half for
each gyrator to ensure that the desired inductance is met (the impedance of inductors in series
adds together). This is not typically done as it requires even more components than in a standard

configuration and the resulting inductance is a result of two simulated inductors, each with half
of the desired inductance.
Applications: The primary application for a gyrator is to reduce the size and cost of a system by
removing the need for bulky, heavy and expensive inductors. For example, RLC band pass filter
characteristics can be realized with capacitors, resistors and operational amplifiers without using
inductors. Thus graphic equalizers can be achieved with capacitors, resistors and operational
amplifiers without using inductors because of the invention of the gyrator.
Gyrator circuits are extensively used in telephony devices that connect to a POTS system. This
has allowed telephones to be much smaller, as the gyrator circuit carries the DC part of the line
loop current, allowing the transformer carrying the AC voice signal to be much smaller due to
the elimination of DC current through it. Gyrators are used in most DAAs (data access
arrangements). Circuitry in telephone exchanges has also been affected with gyrators being used
in line cards. Gyrators are also widely used in hi-fi for graphic equalizers, parametric equalizers,
discrete band stop and band pass filters such as rumble filters), and FM pilot tone filters.
There are many applications where it is not possible to use a gyrator to replace an inductor:

High voltage systems utilizing fly back (beyond working voltage of


transistors/amplifiers)
RF systems commonly use real inductors as they are quite small at these frequencies and
integrated circuits to build an active gyrator are either expensive or non-existent.
However, passive gyrators are possible.
Power conversion, where a coil is used as energy storage.

2.12 FILTERS
ACTIVE FILTERS: The main disadvantage of Passive Filters is that the amplitude of the
output signal is less than that of the input signal, i.e., the gain is never greater than unity and that
the load impedance affects the filters characteristics.
With passive filter circuits containing multiple stages, this loss in signal amplitude called
Attenuation can become quiet severe. One way of restoring or controlling this loss of signal is
by using amplification through the use of Active Filters.As their name implies, Active
Filters contain active components such as operational amplifiers, transistors or FETs within
their circuit design. They draw their power from an external power source and use it to boost or
amplify the output signal.Filter amplification can also be used to either shape or alter the
frequency response of the filter circuit by producing a more selective output response, making
the output bandwidth of the filter narrower or even wider. Then the main difference between a
passive filter and an active filter is amplification.An active filter generally uses an
operational amplifier (op-amp) within its design and an Op-amp has a high input impedance, a
low output impedance and a voltage gain determined by the resistor network within its feedback
loop.
Unlike a passive high pass filter which has in theory an infinite high frequency response, the
maximum frequency response of an active filter is limited to the Gain/Bandwidth product (or

open loop gain) of the operational amplifier being used. Still, active filters are generally easier to
design than passive filters; they produce good performance characteristics, very good accuracy
with a steep roll-off and low noise when used with a good circuit design.
(a) ACTIVE LOW PASS FILTER
The most common and easily understood active filter is the Active Low Pass Filter. Its principle
of operation and frequency response is exactly the same as those for the previously seen passive
filter; the only difference this time is that it uses an op-amp for amplification and gain control.
The simplest form of a low pass active filter is to connect an inverting or non-inverting amplifier
to the basic RC low pass filter circuit as shown.
First Order Active Low Pass Filter

This first-order low pass active filter, consists simply of a passive RC filter stage providing a low
frequency path to the input of a non-inverting operational amplifier. The amplifier is configured
as a voltage-follower (Buffer) giving it a DC gain of one, Av = +1 or unity gain as opposed to
the previous passive RC filter which has a DC gain of less than unity.
The advantage of this configuration is that the op-amps high input impedance prevents excessive
loading on the filters output while its low output impedance prevents the filters cut-off frequency
point from being affected by changes in the impedance of the load.
While this configuration provides good stability to the filter, its main disadvantage is that it has
no voltage gain above one. However, although the voltage gain is unity the power gain is very
high as its output impedance is much lower than its input impedance. If a voltage gain greater
than one is required we can use the following filter circuit.

Active Low Pass Filter with Amplification

The frequency response of the circuit will be the same as that for the passive RC filter, except
that the amplitude of the output is increased by the pass band gain, AF of the amplifier. For a
non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a
function of the feedback resistor ( R2 ) divided by its corresponding input resistor ( R1 ) value
and is given as:

Therefore, the gain of an active low pass filter as a function of frequency will be:
Gain of a first-order low pass filter

Where:

AF = the pass band gain of the filter, (1 + R2/R1)

= the frequency of the input signal in Hertz, (Hz)

c = the cut-off frequency in Hertz, (Hz)


Thus, the operation of a low pass active filter can be verified from the frequency gain equation
above as:

1. At very low frequencies, < c

2. At the cut-off frequency, = c

3. At very high frequencies, > c

Thus, the Active Low Pass Filter has a constant gain AF from 0Hz to the high frequency cut-off
point,C. At C the gain is 0.707AF, and after C it decreases at a constant rate as the frequency
increases. That is, when the frequency is increased tenfold (one decade), the voltage gain is
divided by 10.
In other words, the gain decreases 20dB (= 20log 10) each time the frequency is increased by 10.
When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally
expressed indecibels or dB as a function of the voltage gain, and this is defined as:
Magnitude of Voltage Gain in (dB)

Active Low Pass Filter Example No. 1


Design a non-inverting active low pass filter circuit that has a gain of ten at low frequencies, a
high frequency cut-off or corner frequency of 159Hz and an input impedance of 10K.
The voltage gain of a non-inverting operational amplifier is given as:

Assume a value for resistor R1 of 1k rearranging the formula above gives a value for R2 of

Then, for a voltage gain of 10, R1 = 1k and R2 = 9k. However, a 9k resistor does not exist
so the next preferred value of 9k1 is used instead.
Converting this voltage gain to a decibel dB value gives:

The cut-off or corner frequency (c) is given as being 159Hz with an input impedance of 10k.
This cut-off frequency can be found by using the formula:
where c = 159Hz and R = 10k.
then, by rearranging the above formula we can find the value for capacitor C as:

Then the final circuit along with its frequency response is given below as:
Low Pass Filter Circuit.

Frequency Response Curve

If the external impedance connected to the input of the circuit changes, this change will also
affect the corner frequency of the filter (components connected in series or parallel). One way of
avoiding this is to place the capacitor in parallel with the feedback resistor R2.
The value of the capacitor will change slightly from being 100nF to 110nF to take account of
the 9k1resistor and the formula used to calculate the cut-off corner frequency is the same as
that used for the RC passive low pass filter.

An example of the new Active Low Pass Filter circuit is given as.
Simplified non-inverting amplifier filter circuit

Equivalent inverting amplifier filter circuit

Applications of Active Low Pass Filters are in audio amplifiers, equalizers or speaker systems
to direct the lower frequency bass signals to the larger bass speakers or to reduce any high
frequency noise or hiss type distortion. When used like this in audio applications the active
low pass filter is sometimes called a Bass Boost filter.
Second-order Low Pass Active Filter
As with the passive filter, a first-order Low Pass Active Filter can be converted into a secondorder low pass filter simply by using an additional RC network in the input path. The frequency
response of the second-order low pass filter is identical to that of the first-order type except that

the stop band roll-off will be twice the first-order filters at 40dB/decade (12dB/octave).
Therefore, the design steps required of the second-order active low pass filter are the same.
Second-order Active Low Pass Filter Circuit

When cascading together filter circuits to form higher-order filters, the overall gain of the filter is
equal to the product of each stage. For example, the gain of one stage may be 10 and the gain of
the second stage may be 32 and the gain of a third stage may be 100. Then the overall gain will
be 32,000, (10 x 32 x 100) as shown below.
Cascading Voltage Gain

Second-order (two-pole) active filters are important because higher-order filters can be designed
using them. By cascading together first and second-order filters, filters with an order value,
either odd or even up to any value can be constructed. Active High Pass Filters, can be
constructed by reversing the positions of the resistor and capacitor in the circuit.

(b) ACTIVE HIGH PASS FILTERS


The basic electrical operation of an Active High Pass Filter (HPF) is exactly the same as we saw
for its equivalent RC passive high pass filter circuit, except this time the circuit has an
operational amplifier or op-amp included within its filter design providing amplification and gain
control.
Like the previous active low pass filter circuit, the simplest form of an active high pass filter is to
connect a standard inverting or non-inverting operational amplifier to the basic RC high pass
passive filter circuit as shown.
First Order Active High Pass Filter

Technically, there is no such thing as an active high pass filter. Unlike Passive High Pass
Filters which have an infinite frequency response, the maximum pass band frequency
response of an Active High Pass Filter is limited by the open-loop characteristics or bandwidth
of the operational amplifier being used, making them appear as if they are band pass filters with
a high frequency cut-off determined by the selection of op-amp and gain.
In the Operational Amplifier we know that the maximum frequency response of an op-amp is
limited to the Gain/Bandwidth product or open loop voltage gain ( A V ) of the operational
amplifier being used giving it a bandwidth limitation, where the closed loop response of the op
amp intersects the open loop response.
A commonly available operational amplifier such as the uA741 has a typical open-loop
(without any feedback) DC voltage gain of about 100dB maximum reducing at a roll off rate of 20dB/Decade (-6db/Octave) as the input frequency increases. The gain of the uA741 reduces
until it reaches unity gain, (0dB) or its transition frequency ( t ) which is about 1MHz. This
causes the op-amp to have a frequency response curve very similar to that of a first-order low
pass filter and this is shown below.

Frequency response curve of a typical Operational Amplifier.

Then the performance of a high pass filter at high frequencies is limited by this unity gain
crossover frequency which determines the overall bandwidth of the open-loop amplifier. The
gain-bandwidth product of the op-amp starts from around 100 kHz for small signal amplifiers up
to about 1GHz for high-speed digital video amplifiers and op-amp based active filters can
achieve very good accuracy and performance provided that low tolerance resistors and capacitors
are used.
Under normal circumstances the maximum pass band required for a closed loop active high pass
or band pass filter is well below that of the maximum open-loop transition frequency. However,
when designing active filter circuits it is important to choose the correct op-amp for the circuit as
the loss of high frequency signals may result in signal distortion.
First Order Active High Pass Filter
A first-order (single-pole) Active High Pass Filter as its name implies, attenuates low
frequencies and passes high frequency signals. It consists simply of a passive filter section
followed by a non-inverting operational amplifier. The frequency response of the circuit is the
same as that of the passive filter, except that the amplitude of the signal is increased by the gain
of the amplifier and for a non-inverting amplifier the value of the pass band voltage gain is given
as 1 + R2/R1, the same as for the low pass filter circuit.

Active High Pass Filter with Amplification

This first-order high pass filter consists simply of a passive filter followed by a non-inverting
amplifier. The frequency response of the circuit is the same as that of the passive filter, except
that the amplitude of the signal is increased by the gain of the amplifier.
For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a
function of the feedback resistor (R2) divided by its corresponding input resistor (R1) value and
is given as:
Gain for an Active High Pass Filter

Where:

AF = the Pass band Gain of the filter, ( 1 + R2/R1 )

= the Frequency of the Input Signal in Hertz, (Hz)

c = the Cut-off Frequency in Hertz, (Hz)


Just like the low pass filter, the operation of a high pass active filter can be verified from the
frequency gain equation above as:

1. At very low frequencies, < c

2. At the cut-off frequency, = c

3. At very high frequencies, > c

Then, the Active High Pass Filter has a gain AF that increases from 0Hz to the low frequency
cut-off point, C at 20dB/decade as the frequency increases. At C the gain is 0.707AF, and
after C all frequencies are pass band frequencies so the filter has a constant gain AF with the
highest frequency being determined by the closed loop bandwidth of the op-amp.
When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally
expressed in decibels or dB as a function of the voltage gain, and this is defined as:
Magnitude of Voltage Gain in (dB)

For a first-order filter the frequency response curve of the filter increases by 20dB/decade or
6dB/octave up to the determined cut-off frequency point which is always at -3dB below the
maximum gain value. As with the previous filter circuits, the lower cut-off or corner frequency
( c ) can be found by using the same formula:

The corresponding phase angle or phase shift of the output signal is the same as that given for the
passive RC filter and leads that of the input signal. It is equal to +45o at the cut-off
frequency c value and is given as:

A simple first-order active high pass filter can also be made using an inverting operational
amplifier configuration as well, and an example of this circuit design is given along with its
corresponding frequency response curve. A gain of 40dB has been assumed for the circuit.

Inverting Operational Amplifier Circuit

Frequency Response Curve

Active High Pass Filter Example No. 1


A first order active high pass filter has a pass band gain of two and a cut-off corner frequency of
1 kHz. If the input capacitor has a value of 10nF, calculate the value of the cut-off frequency
determining resistor and the gain resistors in the feedback network. Also, plot the expected
frequency response of the filter.
With a cut-off corner frequency given as 1 kHz and a capacitor of 10nF, the value of R will
therefore be:

or 16 ks to the nearest preferred value.


The pass band gain of the filter, AF is given as being, 2.

As the value of resistor, R2 divided by resistor, R1 gives a value of one. Then, resistor R1 must be
equal to resistor R2, since the pass band gain, AF = 2. We can therefore select a suitable value for
the two resistors of say, 10ks each for both feedback resistors.
So for a high pass filter with a cut-off corner frequency of 1kHz, the values of R and C will
be, 10ksand 10nF respectively. The values of the two feedback resistors to produce a pass
band gain of two are given as: R1 = R2 = 10ks
The data for the frequency response bode plot can be obtained by substituting the values
obtained above over a frequency range from 100Hz to 100 kHz into the equation for voltage
gain:

This then will give us the following table of data.


Frequency,

Voltage Gain

Gain, (dB)

( Hz )

( Vo / Vin )

20log( Vo / Vin )

100

0.20

-14.02

200

0.39

-8.13

500

0.89

-0.97

800

1.25

1.93

1,000

1.41

3.01

3,000

1.90

5.56

5,000

1.96

5.85

10,000

1.99

5.98

50,000

2.00

6.02

100,000

2.00

6.02

The frequency response data from the table above can now be plotted as shown below. In the
stop band (from 100Hz to 1 kHz), the gain increases at a rate of 20dB/decade. However, in the
pass band after the cut-off frequency, C = 1 kHz, the gain remains constant at 6.02dB. The
upper-frequency limit of the pass band is determined by the open loop bandwidth of the
operational amplifier used as we discussed earlier. Then the bode plot of the filter circuit will
look like this.
The Frequency Response Bode-plot for our example.

Applications of Active High Pass Filters are in audio amplifiers, equalizers or speaker systems
to direct the high frequency signals to the smaller tweeter speakers or to reduce any low
frequency noise or rumble type distortion. When used like this in audio applications the active
high pass filter is sometimes called a Treble Boost filter.
Second-order High Pass Active Filter
As with the passive filter, a first-order high pass active filter can be converted into a secondorder high pass filter simply by using an additional RC network in the input path. The frequency
response of the second-order high pass filter is identical to that of the first-order type except that
the stop band roll-off will be twice the first-order filters at 40dB/decade (12dB/octave).
Therefore, the design steps required of the second-order active high pass filter are the same.

Second-order Active High Pass Filter Circuit

Higher-order High Pass Active Filters, such as third, fourth, fifth, etc is formed simply by
cascading together first and second-order filters. For example, a third order high pass filter is
formed by cascading in series first and second order filters, a fourth-order high pass filter by
cascading two second-order filters together and so on.
Then an Active High Pass Filter with an even order number will consist of only second-order
filters, while an odd order number will start with a first-order filter at the beginning as shown.
Cascading Active High Pass Filters

Although there is no limit to the order of a filter that can be formed, as the order of the filter
increases so to does its size. Also, its accuracy declines that are the difference between the actual
stop band response and the theoretical stop band response also increases.
If the frequency determining resistors are all equal, R1 = R2 = R3 etc, and the frequency
determining capacitors are all equal, C1 = C2 = C3 etc, then the cut-off frequency for any order

of filter will be exactly the same. However, the overall gain of the higher-order filter is fixed
because all the frequency determining components are equal.
(c) ACTIVE BAND PASS FILTER
As we know previously in the Passive Band Pass Filter, the principal characteristic of a Band
Pass Filter or any filter for that matter, is its ability to pass frequencies relatively unattenuated
over a specified band or spread of frequencies called the Pass Band.
For a low pass filter this pass band starts from 0Hz or DC and continues up to the specified cutoff frequency point at -3dB down from the maximum pass band gain. Equally, for a high pass
filter the pass band starts from this -3dB cut-off frequency and continues up to infinity or the
maximum open loop gain for an Active Filter.
However, the Active Band Pass Filter is slightly different in that it is a frequency selective filter
circuit used in electronic systems to separate a signal at one particular frequency, or a range of
signals that lie within a certain band of frequencies from signals at all other frequencies. This
band or range of frequencies is set between two cut-off or corner frequency points labelled the
lower frequency ( L ) and the higher frequency ( H ) while attenuating any signals outside
of these two points.
Simple Active Band Pass Filter can be easily made by cascading together a single Low Pass
Filter with a single High Pass Filter as shown.

The cut-off or corner frequency of the low pass filter (LPF) is higher than the cut-off frequency
of the high pass filter (HPF) and the difference between the frequencies at the -3dB point will
determine the bandwidth of the band pass filter while attenuating any signals outside of these
points. One way of making a very simple Active Band Pass Filter is to connect the basic
passive high and low pass filters we look at previously to an amplifying op-amp circuit as
shown.

Active Band Pass Filter Circuit

This cascading together of the individual low and high pass passive filters produces a low Qfactor type filter circuit which has a wide pass band. The first stage of the filter will be the high
pass stage that uses the capacitor to block any DC biasing from the source. This design has the
advantage of producing a relatively flat asymmetrical pass band frequency response with one
half representing the low pass response and the other half representing high pass response as
shown.

The higher corner point ( H ) as well as the lower corner frequency cut-off point ( L ) are
calculated the same as before in the standard first-order low and high pass filter circuits.
Obviously, a reasonable separation is required between the two cut-off points to prevent any
interaction between the low pass and high pass stages. The amplifier also provides isolation
between the two stages and defines the overall voltage gain of the circuit.
The bandwidth of the filter is therefore the difference between these upper and lower -3dB
points. For example, if the -3dB cut-off points are at 200Hz and 600Hz then the bandwidth of the
filter would be given as: Bandwidth (BW) = 600 200 = 400Hz. The normalised frequency
response and phase shift for an active band pass filter will be as follows.

Active Band Pass Frequency Response

While the above passive tuned filter circuit will work as a band pass filter, the pass band
(bandwidth) can be quite wide and this may be a problem if we want to isolate a small band of
frequencies. Active band pass filter can also be made using inverting operational amplifier. So by
rearranging the positions of the resistors and capacitors within the filter we can produce a much
better filter circuit as shown below. For an active band pass filter, the lower cut-off -3dB point is
given by C2 while the upper cut-off -3dB point is given by C1.

This type of band pass filter is designed to have a much narrower pass band. The centre
frequency and bandwidth of the filter is related to the values of R1, R2, C1 and C2. The output of
the filter is again taken from the output of the op-amp.
Multiple Feedback Band Pass Active Filters
We can improve the band pass response of the above circuit by rearranging the components
again to produce an infinite-gain multiple-feedback (IGMF) band pass filter. This type of active
band pass design produces a tuned circuit based around a negative feedback active filter giving
it a high Q-factor (up to 25) amplitude response and steep roll-off on either side of its centre
frequency. Because the frequency response of the circuit is similar to a resonance circuit, this
center frequency is referred to as the resonant frequency, (r). Consider the circuit below.

Infinite Gain Multiple Feedback Active Filter

This active band pass filter circuit uses the full gain of the operational amplifier, with multiple
negative feedbacks applied via resistor, R2 and capacitor C2. Then we can define the
characteristics of the IGMF filter as follows:

We can see then that the relationship between resistors, R1 and R2 determines the band pass Qfactor and the frequency at which the maximum amplitude occurs, the gain of the circuit will be
equal to -2Q2. Then as the gain increases so to does the selectivity. In other words, high gain
high selectivity.
Active Band Pass Filter Example No. 1
An active band pass filter that has a gain Av of one and a resonant frequency, r of 1 kHz is
constructed using an infinite gain multiple feedback filter circuit. Calculate the values of the
components required to implement the circuit.
Firstly, we can determine the values of the two resistors, R1 and R2 required for the active filter
using the gain of the circuit to find Q as follows.

Then we can see that a value of Q = 0.7071 gives a relationship of resistor, R2 being twice the
value of resistor R1. Then we can choose any suitable value of resistances to give the required
ratio of two. Then resistor R1 = 10k and R2 = 20k.
The center or resonant frequency is given as 1 kHz. Using the new resistor values obtained, we
can determine the value of the capacitors required assuming that C = C1 = C2.

The closest standard value is 10nF.


Resonant Frequency Point: The actual shape of the frequency response curve for any passive or
active band pass filter will depend upon the characteristics of the filter circuit with the curve
above being defined as an ideal band pass response. An active band pass filter is a 2nd

Order type filter because it has two reactive components (two capacitors) within its circuit
design.
As a result of these two reactive components, the filter will have a peak response or Resonant
Frequency ( r ) at its center frequency, c. The center frequency is generally calculated as
being the geometric mean of the two -3dB frequencies between the upper and the lower cut-off
points with the resonant frequency (point of oscillation) being given as:

Where:

r is the resonant or Center Frequency

L is the lower -3dB cut-off frequency point

H is the upper -3db cut-off frequency point


and in our simple example above the resonant center frequency of the active band pass filter is
given as:

The Q or Quality Factor


In a Band Pass Filter circuit, the overall width of the actual pass band between the upper and
lower -3dB corner points of the filter determines the Quality Factor or Q-point of the circuit.
This Q Factor is a measure of how Selective or Un-selective the band pass filter is towards
a given spread of frequencies. The lower the value of the Q factor the wider is the bandwidth of
the filter and consequently the higher the Q factors the narrower and more selective is the
filter.
The Quality Factor, Q of the filter is sometimes given the Greek symbol of Alpha, ( ) and is
known as the alpha-peak frequency where:

As the quality factor of an active band pass filter (Second-order System) relates to the
sharpness of the filters response around its centre resonant frequency ( r ) it can also be
thought of as the Damping Factor or Damping Coefficient because the more damping the
filter has the flatter is its response and likewise, the less damping the filter has the sharper is its
response. The damping ratio is given the Greek symbol of Xi, ( ) where:

The Q of a band pass filter is the ratio of the Resonant Frequency, ( r ) to the Bandwidth,
( BW ) between the upper and lower -3dB frequencies and is given as:

Then for our simple example above the quality factor Q of the band pass filter is given as:
346Hz / 400Hz = 0.865.

Note that Q is a ratio and has no units.

When analysing Active Filters, generally a normalised circuit is considered which produces an
ideal frequency response having a rectangular shape, and a transition between the pass band
and the stop band that has an abrupt or very steep roll-off slope. However, these ideal responses
are not possible in the real world so we use approximations to give us the best frequency
response possible for the type of filter we are trying to design.
Probably the best known filter approximation for doing this is the Butterworth or maximally-flat
response filter.
(d) ACTIVE BAND STOP FILTER
The band pass filter passes one set of frequencies while rejecting all others. The band-stop filter
does just the opposite. It rejects a band of frequencies, while passing all others. This is also
called a band-reject or band-elimination filter. Like band pass filters, band-stop filters may also
be classified as (i) wide-band and (ii) narrow band reject filters.
The narrow band reject filter is also called a notch filter. Because of its higher Q, which exceeds
10, the bandwidth of the narrow band reject filter is much smaller than that of a wide band reject
filter.

Wide Band Reject Filters


A wide band-stop filter using a low-pass filter, a high-pass filter and a summing amplifier
is shown in figure. For a proper band reject response, the low cut-off frequency fL of high-pass
filter must be larger than the high cut-off frequency fH of the low-pass filter. In addition, the pass
band gain of both the high-pass and low-pass sections must be equal.
Narrow Band Stop Filter

Twin T Active Notch Filter

This is also called a notch filter. It is commonly used for attenuation of a single frequency such
as 60 Hz power line frequency hum. The most widely used notch filter is the twin-T network
illustrated in fig. (a). This is a passive filter composed of two T-shaped networks. One T-network
is made up of two resistors and a capacitor, while the other is made of two capacitors and a
resistor. One drawback of above notch filter (passive twin-T network) is that it has relatively low
figure of merit Q. However, Q of the network can be increased significantly if it is used with the
voltage follower, as illustrated in fig. (a). Here the output of the voltage follower is supplied back
to the junction of R/2 and 2 C. The frequency response of the active notch filter is shown:

Notch filters are most commonly used in communications and biomedical instruments for
eliminating the undesired frequencies.

A mathematical analysis of this circuit shows that it acts as a lead-lag circuit with a phase angle,
shown in fig. (b). Again, there is a frequency fc at which the phase shift is equal to 0. In fig. the

voltage gain is equal to 1 at low and high frequencies. In between, there is a frequency fc at
which voltage gain drops to zero. Thus such a filter notches out, or blocks frequencies near fc.
The frequency at which maximum attenuation occurs is called the notch-out frequency given by
fn = Fc = 2RC
Notice that two upper capacitors are C while the capacitor in the centre of the network is 2 C.
Similarly, the two lower resistors are R but the resistor in the centre of the network is 1/2 R. This
relationship must always be maintained.
(e) ACTIVE ALL PASS FILTER
In most cases, the amplitude response of a filter is of primary concern. Another type of filter that
leaves the amplitude of the signal intact, but introduces phase shift is called an all pass filter.
The purpose of this filter is to add phase shift (delay) to the response of the circuit. The
amplitude of an all pass is unity for all frequencies. The phase response, however, changes from
0 to 360 (for a 2-pole filter) as the frequency is swept from 0 to infinity. One use of an all pass
filter is to provide phase equalization, typically in pulse circuits. It also has application in single
side band, suppressed carrier (SSB-SC) modulation circuits.
The transfer function of an all pass filter is

Note that an all pass transfer function can be synthesized as

First Order All Pass


The general form of a first-order all pass filter is shown in Fig. If the function is a simple RC
high pass (Fig. A), the circuit has a phase shift that goes from 180 at 0 Hz. and 0at high
frequency. It is 90 at = 1/RC. The resistor may be made variable to allow adjustment of the
delay at a particular frequency.
If the function is changed to a low-pass function (Fig. B), the filter is still a first-order all pass
and the delay equations still hold, but the signal is inverted, changing from 0 at dc to 180 at
high frequency.

First Order All Pass Filter


Design Equations:

(C)

(D)
Fig. C and D are same except for the sign of phase changes.
Second Order All Pass
A second-order all pass circuit shown in Fig. was first described by Delyiannis. The main
attraction of this circuit is that it only requires one op amp. Remember also that an all pass filter
can also be realized as 1 2 BP.

Second Order All Pass Filter


One may use any of the band-pass realizations discussed in this series of mini tutorials to build
the filter, but be aware of whether the BP inverts the phase or not. In addition, be aware that the
gain of the BP section must be 2. To this end, the dual amplifier band-pass filter (DABP)
structure is particularly useful, since its gain is fixed at 2. To select an op amp, we primarily need
to concern ourselves with the bandwidth. The rule of thumb is that the open-loop gain of the amp
at the resonant frequency should be at least 20 dB. Also, since there is a capacitor in the feedback
network, a current feedback amplifier is probably not appropriate.
In all cases, H, o, Q, and are given, taken from the design tables.
Design Equations:

2.13 STATE VARIABLE FILTER


With the advancement in IC technology, a number of manufacturers now offer universal filters
having simultaneous low-pass, high-pass, and band-pass output responses. Notch and all-pass
functions are also available by combining these output responses in the uncommitted op-amp.
Because of its versatility, this filter is called the universal filter. It provides the user with easy
control of the gain and Q-factor. It is also called a state-variable filter.
The filters we have discussed so far are relatively simple single op-amp circuits or several single
op-amp circuits cascaded. The state-variable filter, however, makes use of three or four op-amps
and two feedback paths. Though a bit more complicated, the state variable configuration offers
several features not available with the other simpler filters. First, all three filter types (low-pass,
band-pass, and high-pass) are available simultaneously. By properly summing these outputs
some very interesting responses can be made. Bandpass filters with high Q can be built. The
damping and/or critical frequency could be electronically tuned.

State Variable Active Filter


A schematic of a three op-amp, unity gain state variable filter is depicted in figure. Op-amps A2
and A3 are integrators while op-amp .A1 sums the input with the low-pass output and a portion of
the band pass output. The circuit is actually a small analog computer designed to solve the
differential equation (transfer function) for each filter type.
For proper operation Rj = R2 = R3 = R; R4 = R5 = R,; and Cx = C2 = C.
The critical frequencies of each of the three filters are equal and is as given as
The damping is set by R6 and R7. This determines the types of low-pass and high-pass responses
(Bessel, Butterworth, or Chebyshev)
= 3 [R7 / R6+R7]
It also sets the Q and the gain of the band pass filter
Q = 1/ and A band. pass = Q
The state variable filter produces the standard second-order low-pass band-pass, and high-pass
responses. The critical frequencies of each are equal, and the damping is set by the feedback
from the band pass output. For all three outputs this damping has precisely the same effect (at the
same numerical values) as it did for the single op-amp filters. For low-pass and high-pass, the
damping coefficient of 1.414 provides a Butterworth response. Damping of 1.732 provides
Bessel response, and = 0.766 causes 3 db peaks (Chebyshev). The high-pass 3 db frequencies
are similarly shifted by the high-pass correction factor khp = 1/klp
For the band-pass section, changing the damping coefficient inversely alters the Q and gain (at
critical frequency).

But the critical frequency is set by Rf and C. It is not altered by changes in the damping
coefficient. This means that changes in damping only (and directly) affect the BW. So tuning of
band pass filter is very convenient. Resistor R adjusts the centre frequency only. Resistors RA
and RB adjusts the BW only.
At this point, it is critical that we realize that optimum performance from all three outputs cannot
be obtained simultaneously. For instance if we want maximum flatness in the pass bands of lowpass and high-pass outputs, we must select a Butterworth response with = 1.414. But a
damping coefficient of 1.414 gives a Q and Af of 0.707 each. The band pass filter will not be
very selective and will attenuate even the centre frequency by 30%.
On the other hand, if Q is selected to be 20 to achieve reasonable selectivity and centrefrequency gain, the low-pass and high-pass outputs will have a damping coefficient of 0.05. This
will cause a pass band peak of over 25 db. We can either optimize the band pass output or the
low-pass and high-pass outputs.
2.14 KHN FILTER
KHN Filter means Kerwin-Huelsman-Newcomb (KHN) Biquad Filter
A state variable filter is a type of active filter. It consists of one or more integrators, connected
in some feedback configuration. Any LTI system can be described as a state-space model, with n
state variables for an nth-order system. A state variable filter realizes the state-space model
directly. The instantaneous output voltage of one of the integrators corresponds to one of the
state-space model's state variables. KHN filter is a state variable type filter.
ACTIVE FILTER BASED ON TWO-LOOP INTEGRATOR (THE BIQUAD)
This is an op-amp RC circuit that realizes second order filter functions based on the use of two
integrators connected in cascade in an overall feedback loop.
Consider a second order HPF,

where K is the high frequency gain. Rearranging the equation gives:

The signal,

can be obtained by passing VHP through an integrator with a time constant equal to 1/w0.

Passing the resulting signal through another identical integrator generate:

Then the output signal VHP can be generated as the feedback configuration as shown below:

The two-integrator loop biquad realizes three basic second order filter functions LP, BP and
HP simultaneously. This circuit is very popular and is commonly called the universal active filter
(the Kirwin-Huelsman-Newcomb = KHN biquad).

KHN Filter

By summing the LP, BP and HP outputs, the overall transfer function of the KHN biquad
and the summer in figure (b) is:

Although the two-integrator loop biquads are versatile and easy to design, their performance
is adversely affected by the finite bandwidth of the op-amps.
Another KHN Filter Example

The example given below is the KHN Filter which can produce simultaneous low pass, high pass
and band pass outputs from a single input. This is a second-order (biquad) filter. Its derivation
comes from rearranging a high-pass filter's transfer function, which is the ratio of two quadratic
functions. The rearrangement reveals that one signal is the sum of integrated copies of another.
That is, the rearrangement reveals a state variable filter structure. By using different states as
outputs, different kinds of filters can be produced. In more general state variable filter examples,
additional filter order is possible with more integrators (i.e., more states).

KHN Filter
The signal input is marked Vin; the LP, HP and BP outputs give the low pass, high pass and
band pass filtered signals respectively.
For simplicity, we set:

Then:

The pass-band gain for the LP and HP outputs is given by:

It can be seen that the frequency of operation and the Q factor can be varied independently. This
and the ability to switch between different filter responses make the state-variable filter widely
used in analogue synthesizers.
Values for a resonance frequency of 1 kHz are Rf1=Rf2=10k, C1=C2=15nF and R1=R2=10k.
2.15 TOW-THOMAS BIQUAD FILTER
A biquad filter is a type of linear filter that implements a transfer function that is the ratio of two
quadratic functions. The name biquad is short for biquadratic. It is also sometimes called the
'ring of 3' circuit.
Biquad filters are typically active and implemented with a single-amplifier biquad (SAB) or twointegrator-loop topology.

The SAB topology uses feedback to generate complex poles and possibly complex zeros.
In particular, the feedback moves the real poles of an RC circuit in order to generate the
proper filter characteristics.
The two-integrator-loop topology is derived from rearranging a biquadratic transfer
function. The rearrangement will equate one signal with the sum of another signal, its
integral, and the integral's integral. In other words, the rearrangement reveals a state
variable filter structure. By using different states as outputs, any kind of second-order
filter can be implemented.
The SAB topology is sensitive to component choice and can be more difficult to adjust.
Hence, usually the term biquad refers to the two-integrator-loop state variable filter
topology.

Tow-Thomas Biquad Example


For example, the basic configuration in below figure can be used as either a low-pass or band
pass filter depending on where the output signal is taken from.

The common Tow-Thomas biquad filter topology


The second-order low-pass transfer function is given by

where low-pass gain

. The second-order band pass transfer function is given by

.
with band pass gain

Natural frequency is

Quality factor is

. In both cases, the


.
.

The bandwidth is approximated by


, and Q is sometimes expressed as a damping
constant
. If a non inverting low-pass filter is required, the output can be taken at
the output of the second operational amplifier. If a non inverting band pass filter is required, the
order of the second integrator and the inverter can be switched, and the output taken at the output
of the inverter's operational amplifier.

UNIT-3
3.1 BASICS OF DIGITAL CMOS DESIGN:
The Combinational logic circuits, or gates, perform Boolean operations on multiple input
variables and determine the outputs as Boolean functions of the inputs. Logic circuits can be
represented as a multiple-input, single-output system is shown in figure.

Figure: Generic combinational logic circuit.


The Combinational logic circuits are the basic building blocks of all digital systems. All input
variables are represented by node voltages, referenced to the ground potential. The output node is
loaded with a capacitance C load which represents the combined parasitic device capacitance in
the circuit and the interconnect capacitance components.
3.2 nMOS LOGIC CIRCUITS WITH A MOS LOADS :
Two-Input NOR Gate
The circuit diagram, the logic symbol, and the corresponding truth table of the two-input
depletion-load NOR gate is shown in figure.

Generalized NOR Structure with Multiple Inputs:


An n-input NOR with nMOS depletion load logic and equivalent circuit are shown in figure. The
combined current ID in the circuit is supplied by the driver transistors which are turned on.

The source terminals of all enhancement-type nMOS driver transistors are connected to ground,
and the drivers do not experience any substrate-bias effect. The depletion-type nMOS load
transistor is subjected to substrate-bias effect.
3.3 Two-Input NAND Gate :
The circuit diagram, the logic symbol, and the corresponding truth table of the two-input
depletion-load NAND gate are shown in figure. The Boolean AND operation is performed by the
series connection of the two enhancement-type nMOS driver transistors. If the input voltage VA

and VB is equal to logic-high level, there is a conducting path between the output node and the
ground, the output voltages becomes low.

In all other cases either one or both of the driver transistors will be off, and the output voltage
will be pulled to a logic-high level by depletion-type nMOS load transistor.
Generalized NAND Structure with Multiple Inputs:
An n-input NAND with nMOS depletion load logic and equivalent inverter circuits are shown in
figure.

The series structure consisting of n driver transistors has an equivalent (W/L) ratio of (W/L)
driver when all inputs are logic-high. For two-input NAND gate, each driver transistor must have
a (W/L) ratio twice that of equivalent inverter driver.
3.4 CMOS LOGIC CIRCUITS :
CMOS Two-Input NOR Gate :

The design and analysis of CMOS logic circuits are based on the principles developed for the
nMOS depletion-load logic circuits. Figure shows the circuit diagram of a two-input
CMOS NOR gate.

Operation: when either one or both inputs are high, there is a conducting path between the output
node and the ground created by n-net and the p-net is cut-off. If both the input voltages are low,
the n-net is cut-off, then the p-net creates a conducting path between the output node and supply
voltage VDD. Thus the dual the circuit structure allows that for any given input combination, the
output is either to VDD or ground via a low-resistance path.
The DC current path is not established between VDD and ground for any input combinations. A
CMOS NOR2 gate and its inverter equivalent circuits are shown:

CMOS Two-Input NAND Gate :


A CMOS NAND2 gate and its inverter equivalent circuits are shown in figure. The operating
principle of this circuit is the exact dual of CMOS NOR2 operation explained above.

CMOS inverter equivalent have nMOS pull-down device of gain factor kn/2 and a pMOS pull-up
device of 2kp to achieve equivalent delay and rise/fall times. Assume both nMOS devices have
the same W/L (and the same for both pMOS).
3.5 SEQUENTIAL MOS LOGIC CIRCUITS :
The sequential logic circuits contain one or more combinational logic blocks along with memory
in a feedback loop with the logic: The next state of the machine depends on the present state and
the inputs. The output depends on the present state of the machine and perhaps also on the
inputs.
Mealy machine: output depends only on the state of the machine
Moore machine: output depends on both the present state and the inputs

Sequential Circuit Types :


Bistable circuits have two stable operating points and will remain in either state unless
perturbed to the opposite state Memory cells, latches, flip-flops, and registers.
Monostable circuits have only one stable operating point, and even if they are temporarily
perturbed to the opposite state, they will return in time to their stable operating point.

Astable circuits have no stable operating point and oscillate between several states Ring
oscillator
3.6 SR LATCH CIRCUIT :
CMOS SR Latch: NOR Gate Version:
The NOR-based SR Latch contains the basic memory cell (back-to-back inverters) built into two
NOR gates to allow setting the state of the latch. The gate-level symbol and CMOS NOR-based
SR latch are shown in figure.

Operation of NOR-based SR Latch: If Set goes high, M1 is turned on, forcing Q low which, in
turn, pulls Q high. If Reset goes high, M4 is turned on, Q is pulled low, and Q is pulled high. If
both Set and Reset are low, both M1 and M4 are off, and the latch holds its existing state
indefinitely. If both Set and Reset go high, both Q and Q are pulled low, giving an indefinite
state. Therefore, R=S=1 is not allowed

Depletion Load nMOS SR Latch: NOR Version:


A depletion load version of the NOR-based SR latch is shown figure. Functionally it is the same
as CMOS version. The latch is a ratio circuit. Low side conducts dc current, causing higher
standby power than CMOS version

CMOS SR Latch: NAND Gate Version:


The NAND-based SR Latch contains the basic memory cell (back-to-back inverters) built into
two NAND gates to allow setting the state of the latch. The gate-level symbol and CMOS
NAND-based SR latch are shown in figure.

Operation of NAND-based SR Latch: The circuit responds to active low S and R inputs: If S
goes to 0 (while R = 1), Q goes high, pulling Q low and the latch enters Set state. If R goes to 0
(while S = 1), Q goes high, pulling Q low and the latch is Reset. Hold state requires both S and
R to be high. S = R = 0 if not allowed, it would result in an indeterminate state.

Depletion Load nMOS SR Latch: NAND Version :

A depletion load version of the NAND-based SR latch is shown figure. Functionally it is the
same as the CMOS version.

3.7 CLOCKED LATCH AND FLIP FLOP CIRCUITS:


Clocked SR Latch: NOR Version:
The clocked NOR-based SR latch, contains the basic memory cell built into two NOR gates to
allow setting the state of the latch with a clock added as shown in figure. The latch is responsive
to inputs S and R only when CK is high. When CK is low, the latch retains in its current state.

CMOS AOI implementation of clocked NOR-based SR latch is shown in figure. Only 12


transistors required. When CK is low, two series legs in N tree are open and two parallel
transistors in P tree are ON, thus retaining state in the memory cell. When CK is high, the circuit
becomes simply a NOR-based CMOS latch which will respond to inputs S and R.

3.8 CMOS D LATCH AND EDGE-TRIGGERED FLIP FLOPS:


CMOS D-Latch Implementation:
A D-latch is implemented, at the gate level, by simply utilizing a NOR-based S-R latch,
connecting D to input S, and connecting D to input R with an inverter as shown in figure. When
CK goes high, D is transmitted to output Q (and D to Q). When CK goes low,the latch retains
its previous state.

The D latch implemented with TG switches is shown in figure. The input TG is activated with
CK while the latch feedback loop TG is activated with CK. Input D is accepted when CK is
high. When CK goes low, the input is open-circuited and the latch is set with the prior data D

A schematic view of the D-Latch can be obtained using simple switches in place of the TGs as
shown in figure. When CK = 1, the input switch is closed allowing new input data into the latch.
When CK = 0, the input switch is opened and the feedback loop switch is closed, setting the
latch.
CMOS D Flip-Flop Figure shows a D Flip-Flop, constructed by cascading two D-Latch circuits
from the previous slide: Master latch is positive level sensitive (receives data when CK = 1).
Slave latch is negative level sensitive (receives data Qm when CK = 0), the circuit is negativeedge triggered. Master latch receives input D until the CK falls from 1 to 0, at which point it sets
that data in the master latch and sends it through to the output Qs.

UNIT-4
4.1 LOG AMPLIFIER:
Log amplifier is a linear circuit in which the output voltage will be a constant times the natural
logarithm of the input. The basic output equation of a log amplifier is v Vout = K ln (Vin/Vref);
where Vref is the constant of normalization, and K is the scale factor. Log amplifier finds a lot of
application in electronic fields like multiplication or division (they can be performed by the
addition and subtraction of the logs of the operand), signal processing, computerised process
control, compression, decompression, RMS value detection etc. Basically there are two log amp
configurations: Opamp-diode log amplifier and Opamp-transistor log.
Opamp-diode log amplifier:

The schematic of a simple Op-amp diode log amplifier is shown above. This is nothing but an
op-amp wired in closed loop inverting configuration with a diode in the feedback path. The
voltage across the diode will be always proportional to the log of the current through it and when
a diode is placed in the feedback path of an op-amp in inverting mode, the output voltage will be
proportional to the negative log of the input current. Since the input current is proportional to the
input voltage, we can say that the output voltage will be proportional to the negative log of the
input voltage.
According to the PN junction diode equation, the relationship between current and voltage for a
diode is
Id=Is(e(Vd/Vt)-1)(1)

Where Id is the diode current, Is is the saturation current, Vd is the voltage across the diode and
Vt is the thermal voltage.
Since Vd the voltage across the diode is positive here and Vt the thermal voltage is a small
quantity, the equation (1) can be approximated as
Id = Is e(Vd/Vt)(2)
Since an ideal opamp has infinite input resistance, the input current Ir has only one path, that is
through the diode. That means the input current is equal to the diode current Id.
=> Ir = Id .(3)
Since the inverting input pin of the opamp is virtually grounded, we can say that
Ir = Vin/R
Since Ir = Id (from equation (3))
Vin/R = Id ..(4)
Comparing equation (4) and (2) we have
Vin/R = Is e(Vd/Vt)
i.e. Vin = Is R e(Vd/Vt)(5)
Considering that the negative of the voltage across diode is the output voltage Vout (see the
circuit diagram (fig1)), we can rearrange the equation (5) to get
Vout = -Vt In(Vin/IsR)
4.2 ANTILOG AMPLIFIER:
Definition
Anti log amplifier is one which provides output proportional to the antilog i.e. exponential to the
input voltage. If Vi is the input signal applied to a Anti log amplifier then the output is
Vo=K*exp(a*Vi)
where K is proportionality constant, a is constant.
Anti log amplifier operation
A simple Anti log amplifier is shown below

It is obvious from the circuit shown above that negative feedback is provided from output to
inverting terminal. Using the concept of virtual short between the input terminals of an op-amp
the voltage at inverting terminal will be zero volts.(Since the non inverting terminal of opamp is
at ground potential). The anti log amplifier can be redrawn as follows :
The current equation of diode is given as Id = Ido*(exp (V/Vt)-1) where Ido is reverse saturation
current is voltage applied across diode; Vt is the voltage equivalent of temperature
Applying KCL at inverting node of op-amp we get
Id = (0-Vo)/R = Io*(exp(Vin/Vt)) (assumed Vin /Vt >> 1)
Hence Vo = -Io*R*(exp (Vin/Vt)).
Gain of Anti log amplifier
Gain of Anti log amplifier K= -Io*R:
4.3 PRECISION RECTIFIER CIRCUITS:
Rectifier circuits are used in the design of power supply circuits. In such applications, the voltage
being rectified are usually much greater than the diode voltage drop, rendering the exact value of
the diode drop unimportant to the proper operation of the rectifier. Other applications exists,
however, where this is not the case. For example, in instrumentation applications, the signal to be
rectified can be of very small amplitude, say 0.1 V, making it impossible to employ the
conventional rectifier circuits. Also the need arises for very precise transfer characteristics

Precision Half-Wave Rectifier- The Superdiode


There are many applications for precision rectifiers, and most are suitable for use in audio
circuits. A half wave precision rectifier is implemented using an op amp, and includes the diode
in the feedback loop. This effectively cancels the forward voltage drop of the diode, so very low
level signals (well below the diode's forward voltage) can still be rectified with minimal error.

Limitations:
The circuit has some serious limitations. The main one is speed. It will not work well with high
frequency signals.
For a low frequency positive input signal, 100% negative feedback is applied when the diode
conducts. The forward voltage is effectively removed by the feedback, and the inverting input
follows the positive half of the input signal almost perfectly.
When the input signal becomes negative, the op amp has no feedback at all, so the output pin of
the op amp swings negative as far as it can.
When the input signal becomes positive again, the op amp's output voltage will take a finite
time to swing back to zero, then to forward bias the diode and produce an output. This time is
determined by the op amp's slew rate, and even a very fast op amp will be limited to low
frequencies.
Another Circuit:
The circuit below accepts an incomimng waveform and as usual with op amps, inverts it.
However, only the positive-going portions of the output waveform, which correspond to the
negative-going portions of the input signal, actually reach the output. The direct feedback diode
shunts any negative-going output back to the "-" input directly, preventing it from being
reproduced. The slight voltage drop across the diode itself is blocked from the output by the
second diode. D1 allows positive-going output voltage to reach the output.

A Basic Circuit for Precision Full-Wave Rectifier:


Replace DA with a super diode and the diode DB and the inverting amplifier with the inverting
precision half-wave rectifier to get the precision full wave rectifier in the following page.

4.4 A PRECISION PEAK DETECTOR:


The capacitor retains a voltage equal to the positive peak of the input.

When the peak detector required to hold the value of the peak for a long time, the capacitor
should be buffered. An op amp A2, which should have high input impedance and low input bias
current, is connected as a voltage follower. The rest of the circuit is similar to the half-wave
rectifier.
4.5 SAMPLE AND HOLD CIRCUIT:
In electronics, a sample and hold (S/H, also "follow-and-hold") circuit is an analog device that
samples (captures, grabs) the voltage of a continuously varying analog signal and holds (locks,
freezes) its value at a constant level for a specified minimum period of time. Sample and hold
circuits and related peak detectors are the elementary analog memory devices. They are typically
used in analog-to-digital converters to eliminate variations in input signal that can corrupt the
conversion process.
A typical sample and hold circuit stores electric charge in a capacitor and contains at least one
fast FET (field effect transistor) switch and at least one amplifier. To sample the input signal the
switch connects the capacitor to the output of a buffer amplifier. The buffer amplifier charges or
discharges the capacitor so that the voltage across the capacitor is practically equal, or
proportional to, input voltage. In hold mode the switch disconnects the capacitor from the buffer.
The capacitor is invariably discharged by its own leakage currents and useful load currents,
which makes the circuit inherently volatile, but the loss of voltage (voltage drop) within a
specified hold time remains within an acceptable error margin. To keep the input voltage as
stable as possible, it is essential that the capacitor have very low leakage, and that it not be
loaded to any significant degree which calls for a very high input impedance.

Figure. Sample and Hold circuit

Figure.Sample time

Figure.Sample and Hold


Sample and hold circuits are used in linear systems. In some kinds of analog-to-digital
converters, the input is compared to a voltage generated internally from a digital-to-analog
converter (DAC). The circuit tries a series of values and stops converting once the voltages are
equal, within some defined error margin. If the input value was permitted to change during this
comparison process, the resulting conversion would be inaccurate and possibly completely
unrelated to the true input value. Such successive approximation converters will often
incorporate internal sample and hold circuitry. In addition, sample and hold circuits are often
used when multiple samples need to be measured at the same time. Each value is sampled and
held, using a common sample clock.
4.6 ANALOG MULTIPLIER
In electronics, an analog multiplier is a device which takes two analog signals and produces an
output which is their product. Such circuits can be used to implement related functions such as
squares (apply same signal to both inputs), and square roots. An electronic analog multiplier can
be called by several names, depending on the function it is used to serve (see analog multiplier
applications).

An analog multiplier is a circuit with an output that is proportional to the product of two inputs:

Where K is a constant value whose dimension is the inverse of a voltage. In general we might
expect that the two inputs can be both positive and negative, and so can be the output. Anyway,
most of the implementations work only if both inputs are strictly positive: this is not such a limit
because we can shift the input and the output in order to have a core working only with positive
signals but external interfaces working with any polarity (within certain limits according to the
particular configuration).Although analog multiplier circuits are very similar to operational
amplifiers, they are far more susceptible to noise and offset voltage-related problems as these
errors may become multiplied. When dealing with high frequency signals, phase-related
problems may be quite complex. For this reason, manufacturing wide-range general-purpose
analog multipliers is far more difficult than ordinary operational amplifiers, and such devices are
typically produced using specialist technologies and laser trimming, as are those used for highperformance amplifiers such as instrumentation amplifiers. This means they have a relatively
high cost and so they are generally used only for circuits where they are indispensable. Analog
multiplication can be accomplished by using the Hall Effect. The Gilbert cell is a circuit whose
output current is a 4 quadrant multiplication of its two differential inputs.
An analog multiplier is a device having two input ports and an output port. The signal at the
output is the product of the two input signals. If both input and output signals are voltages, the
transfer characteristic is the product of the two voltages divided by a scaling factor, K, which has
the dimension of voltage as shown in figure:

Basic Analog Multiplier and Definition of Multiplier Quadrants


From a mathematical point of view, multiplication is a "four quadrant" operationthat is to say that
both inputs may be either positive or negative, as may be the output. Some of the circuits used to
produce electronic multipliers, however, are limited to signals of one polarity. If both signals must be
unipolar, we have a "single quadrant" multiplier, and the output will also be unipolar. If one of the

signals is unipolar, but the other may have either polarity, the multiplier is a "two quadrant"
multiplier, and the output may have either polarity (and is "bipolar"). The circuitry used to produce
one- and two-quadrant multipliers may be simpler than that required for four quadrant multipliers,
and since there are many applications where full four quadrant multiplication is not required, it is
common to find accurate devices which work only in one or two quadrants. An example is the
AD539, a wideband dual two-quadrant multiplier which has a single unipolar Vy input with a
relatively limited bandwidth of 5 MHz, and two bipolar Vx inputs, one per multiplier, with
bandwidths of 60 MHz A block diagram of the AD539 is shown in below figure:

AD539 Analog Multiplier Block Diagram


The simplest electronic multipliers use logarithmic amplifiers. The computation relies on the fact that
the antilog of the sum of the logs of two numbers is the product of those numbers as shown in figure
below:

Multiplication Using Log Amps

Analog Multiplier Applications


Integrated circuits analog multipliers are incorporated into many applications, such as a true
RMS converter, but a number of general purpose analog multiplier building blocks are available
such as the Linear Four Quadrant Multiplier. General-purpose devices will usually include
attenuators or amplifiers on the inputs or outputs in order to allow the signal to be scaled within
the voltage limits of the circuit.
Some more application examples of Analog Multiplier are:

Variable-gain amplifier
Ring modulator
Product detector
Frequency mixer
Companding
Squelch
Analog computer
Analog signal processing
Automatic gain control
True RMS converter
Analog filters (especially voltage-controlled filters)
PAM-pulse amplitude modulation

4.7 OP-AMP AS COMPARATOR:


An operational amplifier (op-amp) has a well-balanced difference input and a very high gain.
This parallels the characteristics of comparators and can be substituted in applications with lowperformance requirements.
In theory, a standard op-amp operating in open-loop configuration (without negative feedback)
may be used as a low-performance comparator. When the non-inverting input (V+) is at a higher
voltage than the inverting input (V-), the high gain of the op-amp causes the output to saturate at
the highest positive voltage it can output. When the non-inverting input (V+) drops below the
inverting input (V-), the output saturates at the most negative voltage it can output. The op-amp's
output voltage is limited by the supply voltage. An op-amp operating in a linear mode with
negative feedback, using a balanced, split-voltage power supply, (powered by VS) has its
transfer function typically written as:
. However, this equation may not
be applicable to a comparator circuit which is non-linear and operates open-loop (no negative
feedback)

In practice, using an operational amplifier as a comparator presents several disadvantages as


compared to using a dedicated comparator:
1. Op-amps are designed to operate in the linear mode with negative feedback. Hence, an
op-amp typically has a lengthy recovery time from saturation. Almost all op-amps have
an internal compensation capacitor which imposes slew rate limitations for high
frequency signals. Consequently an op-amp makes a sloppy comparator with propagation
delays that can be as slow as tens of microseconds.
2. Since op-amps do not have any internal hysteresis, an external hysteresis network is
always necessary for slow moving input signals.
3. The quiescent current specification of an op-amp is valid only when the feedback is
active. Some op-amps show an increased quiescent current when the inputs are not equal.
4. A comparator is designed to produce well limited output voltages that easily interface
with digital logic. Compatibility with digital logic must be verified while using an opamp as a comparator.
5. Some multiple-section op-amps may exhibit extreme channel-channel interaction when
used as comparators.
6. Many op-amps have back to back diodes between their inputs. Op-amp inputs usually
follow each other so this is fine. But comparator inputs are not usually the same. The
diodes can cause unexpected current through inputs.

4.8 ZERO CROSSING DETECTOR USING 741 IC:


The zero crossing detector circuit is an important application of the op-amp comparator
circuit. It can also be called as the sine to square wave converter. Anyone of the inverting or
non-inverting comparators can be used as a zero-crossing detector. The only change to be
brought in is the reference voltage with which the input voltage is to be compared, must be
made zero (Vref = 0V). An input sine wave is given as Vin. These are shown in the circuit
diagram and input and output waveforms of an inverting comparator with a 0V reference
voltage.

As shown in the waveform, for a reference voltage 0V, when the input sine wave passes through
zero and goes in positive direction, the output voltage Vout is driven into negative saturation.
Similarly, when the input voltage passes through zero and goes in the negative direction, the
output voltage is driven to positive saturation. The diodes D1 and D2 are also called clamp
diodes. They are used to protect the op-amp from damage due to increase in input voltage. They
clamp the differential input voltages to either +0.7V or -0.7V.
In certain applications, the input voltage may be a low frequency waveform. This means that the
waveform only changes slowly. This causes a delay in time for the input voltage to cross the
zero-level. This causes further delay for the output voltage to switch between the upper and
lower saturation levels. At the same time, the input noises in the op-amp may cause the output
voltage to switch between the saturation levels. Thus zero crossing are detected for noise
voltages in addition to the input voltage. These difficulties can be removed by using
a regenerative feedback circuit with a positive feedback that causes the output voltage to change
faster thereby eliminating the possibility of any false zero crossing due to noise voltages at the
op-amp input.

4.9 OP-AMP COMPARATOR:

A comparator finds its importance in circuits where two voltage signals are to be compared and
to be distinguished on which is stronger. A comparator is also an important circuit in the design
of non-sinusoidal waveform generators as relaxation oscillators.
In an op-amp with an open loop configuration with a differential or single input signal has a
value greater than 0, the high gain which goes to infinity drives the output of the op-amp into
saturation. Thus, an op-amp operating in open loop configuration will have an output that goes to
positive saturation or negative saturation level or switch between positive and negative saturation
levels and thus clips the output above these levels. This principle is used in a comparator circuit
with two inputs and an output. The 2 inputs, out of which one is a reference voltage (Vref) is
compared with each other.

Non-inverting 741 IC Op-amp Comparator Circuit:


A non-inverting 741 IC op-amp comparator circuit is shown in the figure below. It is called a
non-inverting comparator circuit as the sinusoidal input signal Vin is applied to the non-inverting
terminal. The fixed reference voltage Vref is given to the inverting terminal (-) of the op-amp.

When the value of the input voltage Vin is greater than the reference voltage Vref the output
voltage Vo goes to positive saturation. This is because the voltage at the non-inverting input is
greater than the voltage at the inverting input.

When the value of the input voltage Vin is lesser than the reference voltage Vref, the output
voltage Vo goes to negative saturation. This is because the voltage at the non-inverting input is
smaller than the voltage at the inverting input. Thus, output voltage Vo changes from positive
saturation point to negative saturation point whenever the difference between Vin and Vref
changes. This is shown in the waveform below. The comparator can be called a voltage level
detector, as for a fixed value of Vref, the voltage level of Vin can be detected.
The circuit diagram shows the diodes D1and D2. These two diodes are used to protect the opamp from damage due to increase in input voltage. These diodes are called clamp diodes as they
clamp the differential input voltages to either 0.7V or -0.7V. Most op-amps do not need clamp
diodes as most of them already have built in protection. Resistance R1 is connected in series with
input voltage Vin and R is connected between the inverting input and reference voltage Vref. R1
limits the current through the clamp diodes and R reduces the offset problem.

Inverting 741 IC Op-amp Comparator Circuit:


An inverting 741 IC op-amp comparator circuit is shown in the figure below. It is called a
inverting comparator circuit as the sinusoidal input signal Vin is applied to the inverting
terminal. The fixed reference voltage Vref is given to the non-inverting terminal (+) of the opamp. A potentiometer is used as a voltage divider circuit to obtain the reference voltage in the
non-inverting input terminal. Bothe ends of the POT are connected to the dc supply voltage
+VCC and -VEE. The wiper is connected to the non-inverting input terminal. When the wiper is
rotated to a value near +VCC, Vref becomes more positive, and when the wiper is rotated
towards -VEE, the value of Vref becomes more negative. The waveforms are shown below.

4.10 COMPARATOR CHARACTERISTICS:


1. Operation Speed According to change of conditions in the input, a comparator circuit
switches at a good speed beween the saturation levels and the response is instantaneous.
2. Accuracy Accuracy of the comparator circuit causes the following characteristics:(a) High Voltage Gain The comparator circuit is said to have a high voltage gain characteristic
that results in the requirement of smaller hysteresis voltage. As a result the comparator output
voltage switches between the upper and lower saturation levels.
(b) High Common Mode Rejection Ratio (CMRR) The common mode input voltage
parameters such a noise is rejcted with the help of a high CMRR.
(c) Very Small Input Offset Current and Input Offset Voltage A negligible amount of Input
Offset Current and Input Offset Voltage causes a lesser amount of offset problems. To reduce
further offset problems, offset voltage compensating networks and offset minimizing resistors
can be used.
4.11 SCHMITT TRIGGER:
A Schmitt trigger circuit is also called a regenerative comparator circuit. The circuit is designed
with a positive feedback and hence will have a regenerative action which will make the output
switch levels. Also, the use of positive voltage feedback instead of a negative feedback, aids the
feedback voltage to the input voltage, instead of opposing it. The use of a regenerative circuit is
to remove the difficulties in a zero-crossing detector circuit due to low frequency signals and
input noise voltages. Shown below is the circuit diagram of a Schmitt trigger. It is basically an
inverting comparator circuit with a positive feedback. The purpose of the Schmitt trigger is to

convert any regular or irregular shaped input waveform into a square wave output voltage or
pulse. Thus, it can also be called a squaring circuit.

As shown in the circuit diagram, a voltage divider with resistors Rdiv1 and Rdiv2 is set in the
positive feedback of the 741 IC op-amp. The same values of Rdiv1 and Rdiv2 are used to get the
resistance value Rpar = Rdiv1||Rdiv2 which is connected in series with the input voltage. Rpar is
used to minimize the offset problems. The voltage across R1 is fedback to the non-inverting
input. The input voltage Vi triggers or changes the state of output Vout every time it exceeds its
voltage levels above a certain threshold value called Upper Threshold Voltage (Vupt) and Lower
Threshold Voltage (Vlpt).
Let us assume that the inverting input voltage has a slight positive value. This will cause a
negative value in the output. This negative voltage is fedback to the non-inverting terminal (+) of
the op-amp through the voltage divider. Thus, the value of the negative voltage that is fedback to
the positive terminal becomes higher. The value of the negative voltage becomes again higher
until the circuit is driven into negative saturation (-Vsat). Now, let us assume that the inverting
input voltage has a slight negative value. This will cause a positive value in the output. This
positive voltage is fedback to the non-inverting terminal (+) of the op-amp through the voltage
divider. Thus, the value of the positive voltage that is fedback to the positive terminal becomes
higher. The value of the positive voltage becomes again higher until the circuit is driven into
positive saturation (+Vsat). This is why the circuit is also named a regenerative comparator
circuit.

When Vout = +Vsat, the voltage across Rdiv1 is called Upper Threshold Voltage (Vupt). The
input voltage, Vin must be slightly more positive than Vupt inorder to cause the output Vo to
switch from +Vsat to -Vsat. When the input voltage is less than Vupt, the output voltage Vout is
at +Vsat.
Upper Threshold Voltage, Vupt = +Vsat (Rdiv1/[Rdiv1+Rdiv2])
When Vout = -Vsat, the voltage across Rdiv1 is called Lower Threshold Voltage (Vlpt). The
input voltage, Vin must be slightly more negaitive than Vlpt inorder to cause the output Vo to
switch from -Vsat to +Vsat. When the input voltage is less than Vlpt, the output voltage Vout is
at -Vsat.
Lower Threshold Voltage, Vlpt = -Vsat (Rdiv1/[Rdiv1+Rdiv2])
If the value of Vupt and Vlpt are higher than the input noise voltage, the positive feedback will
eliminate the false output transitions. With the help of positive feedback and its regenerative
behaviour, the output voltage will switch fast between the positive and negative saturation
voltages.

Hysteresis Characteristics:
Since a comparator circuit with a positive feedback is used, a dead band condition hysteresis can
occur in the output. When the input of the comparator has a value higher than Vupt, its output
switches from +Vsat to -Vsat and reverts back to its original state, +Vsat, when the input value
goes below Vlpt. This is shown in the figure below. The hysteresis voltage can be calculated as
the difference between the upper and lower threshold voltages.
Vhysteresis = Vupt Vlpt
Subsituting the values of Vupt and Vlpt from the above equations:
Vhysteresis = +Vsat (Rdiv1/Rdiv1+Rdiv2) {-Vsat (Rdiv1/Rdiv1+Rdiv2)}
Vhysteresis = (Rdiv1/Rdiv1+Rdiv2) {+Vsat (-Vsat)

Applications of Schmitt Trigger:


Schmitt trigger is mostly used to convert a very slowly varying input voltage into an output
having abruptly varying waveform occurring precisely at certain predetermined value of input
voltage. Schmitt trigger may be used for all applications for which a general comparator is used.
Any type of input voltage can be converted into its corresponding square signal wave. The only
condition is that the input signal must have large enough excursion to carry the input voltage
beyond the limits of the hysteresis range. The amplitude of the square wave is independent of the
peak-to-peak value of the input waveform.
4.12 ASTABLE MULTIVIBRATOR USING OP-AMP:
The Op-amp Multivibrator is an astable oscillator circuit that generates a rectangular output
waveform using an RC timing network connected to the inverting input of the operational
amplifier and a voltage divider network connected to the other non-inverting input.

Unlike the monostable or bistable, the astable multivibrator has two states, neither of which are
stable as it is constantly switching between these two states with the time spent in each state
controlled by the charging or discharging of the capacitor through a resistor.
In the op-amp multivibrator circuit the op-amp works as an analogue comparator. An op-amp
comparator compares the voltages on its two inputs and gives a positive or negative output
depending on whether the input is greater or less than some reference value, Vref.
However, because the open-loop op-amp comparator is very sensitive to the voltage changes on
its inputs, the output can switch uncontrollably between its positive, +V(sat) and negative, V(sat) supply rails whenever the input voltage being measured is near to the reference
voltage, Vref.

Firstly lets assume that the capacitor is fully discharged and the output of the op-amp is
saturated at the positive supply rail. The capacitor, C starts to charge up from the output
voltage, Vout through resistor, R at a rate determined by their RC time constant.
We know that the capacitor wants to charge up fully to the value of Vout (which is +V(sat))
within five time constants. However, as soon as the capacitors charging voltage at the op-amps
inverting (-) terminal is equal to or greater than the voltage at the non-inverting terminal (the opamps output voltage fraction divided between resistors R1 and R2), the output will change state
and be driven to the opposing negative supply rail.
But the capacitor, which has been happily charging towards the positive supply rail (+V(sat)),
now sees a negative voltage, -V(sat) across its plates. This sudden reversal of the output voltage
causes the capacitor to discharge toward the new value of Vout at a rate dictated again by
their RC time constant.

Op-amp Multivibrator Voltages

Once the op-amps inverting terminal reaches the new negative reference voltage, -Vref at the
non-inverting terminal, the op-amp once again changes state and the output is driven to the
opposing supply rail voltage, +V(sat). The capacitor now sees a positive voltage across its plates
and the charging cycle begins again. Thus, the capacitor is constantly charging and discharging
creating an astable op-amp multivibrator output.
The period of the output waveform is determined by the RC time constant of the two timing
components and the feedback ratio established by the R1, R2 voltage divider network which sets
the reference voltage level. If the positive and negative values of the amplifiers saturation
voltage have the same magnitude, then t1 = t2 and the expression to give the period of oscillation
becomes:

Then we can see from the above equation that the frequency of oscillation for an Op-amp
Multivibrator circuit not only depends upon the RC time constant but also upon the feedback
fraction. However, if we used resistor values that gave a feedback fraction of 0.462, ( = 0.462),
then the frequency of oscillation of the circuit would be equal to just 1/2RC as shown because
the linear log term becomes equal to one.

Variable Op-amp Multivibrator

By adjusting the central potentiometer between 1 and 2 the output frequency will change by
the following amounts. Potentiometer wiper at 1

Potentiometer wiper at 2

Then in this simple example we can produce an Operational Amplifier Multivibrator circuit that
can produce a variable output rectangular waveform from 100Hz to 1.2 kHz, or any frequency
range we require just by changing the RC component values.
We have seen above that an Op-amp Multivibrator circuit can be constructed using a standard
operational amplifier, such as the 741, and a few additional components. These voltage
controlled non-sinusoidal relaxation oscillators are generally limited to a few hundred kilo-hertz
(kHz) because the op-amp does not have the required bandwidth, but nevertheless they still make
excellent oscillators.
4.13 MONO STABLE MULTIVIBRATOR USING OPAMP:
The circuit shown in figure shows a deferential input operational amplifier acting as monostable
multivibrator. In the permanently state of this circuit the amplifier output is at positive saturation,
terminal B is clamped to earth by diode D1 and terminal A is positive with respect to earth by an
amount of V10 (sat),

where = (R2 /(R1 + R2))


It is assumed that the resistor Rs is much greater than R1 so that its loading effect may be
neglected. If the potential at the point A is brought down to earth by the application of a
sufficiently large negative pulse the circuit switches regeneratively to its temporarily stable state
in which the amplifier output is negative saturation. Terminal A is then negative with respect to
earth by an amount -V02 (sat) and the potential negative at B falls exponentially as C charges
down through R, diode D1 is reverse biased. The circuit switches back to its permanently stale
state when the potential at B reaches the value -V02 (sat).
Uses of Monostable Multivibrator

1. The falling part of the output pulse from MMV is often used to trigger another pulse
generator circuit thus producing a pulse delayed by a time T with respect to the input
pulse.
2. MMV is used for regenerating old and worn out pulses. Various pulses used in computers
and telecommunication systems become somewhat distorted during use. An MMV can be
used to generate new, clean and sharp pulses from these distorted and used ones.
Monostable Triggering
To change the monostable multivibrator state from the stable to quasi-state the external trigger
pulses are to be applied. In general the negative triggering has greater sensitivity, because here
the negative pulse amplitude should be enough, so as to bring the operating point from saturation
to active region. Secondly when the base emitter voltage of a junction changes from forward bias
to reverse bias, its input impedance is continuously rising, which avoids the loading of the
triggering source. It should be further noted that the monostable period is affected by this
method.
The positive pulse triggering has sensitivity, because to turn of the transistor from the OFF state,
it is necessary to feed the excess stored charge in the base such that the amplitude of triggering
pulse is enough and is derived from a low impedance source, which can supply a peak demand
current to turn on.
4.14 TRIANGULAR WAVE GENERATOR USING OP-AMP:
This article is about a triangular wave generator using opamp IC. Triangular wave is a periodic,
non-sinusoidal waveform with a triangular shape. People often get confused between triangle
and sawtooth waves. The most important feature of a triangular wave is that it has equal rise and
fall times while a saw tooth wave has un-equal rise and fall times. The applications of triangular
wave include sampling circuits, thyristor firing circuits, frequency generator circuits, tone
generator circuits etc. There are many methods for generating triangular waves but here we focus
on method using opamps. This circuit is based on the fact that a square wave on integration gives
a triangular wave.

The circuit uses an op amp based square wave generator for producing the square wave and an
op amp based integrator for integrating the square wave. The circuit diagram is shown in the
figure below.

The square wave generator section and the integrator section of the circuit are explained in detail
below.
Square wave generator:
The square wave generator is based on a uA741 op amp (IC1). Resistor R1 and capacitor C1
determines the frequency of the square wave. Resistor R2 and R3 forms a voltage divider setup
which feedbacks a fixed fraction of the output to the non-inverting input of the IC.
Initially, when power is not applied the voltage across the capacitor C1 is 0. When the power
supply is switched ON, the C1 starts charging through the resistor R1 and the output of the op
amp will be high (+Vcc). A fraction of this high voltage is fed back to the non- inverting pin by
the resistor network R2, R3. When the voltage across the charging capacitor is increased to a
point the the voltage at the inverting pin is higher than the non-inverting pin, the output of the op
amp swings to negative saturation (-Vcc). The capacitor quickly discharges through R1 and starts
charging in the negative direction again through R1. Now a fraction of the negative high output
(-Vcc) is fed back to the non-inverting pin by the feedback network R2, R3. When the voltage
across the capacitor has become so negative that the voltage at the inverting pin is less than the
voltage at the non-inverting pin, the output of the op amp swings back to the positive saturation.
Now the capacitor discharges trough R1 and starts charging in positive direction. This cycle is
repeated over time and the result is a square wave swinging between +Vcc and -Vcc at the output
of the opamp.
If the values of R2 and R3 are made equal, then the frequency of the square wave can be
expressed using the following equation:
F=1 / (2.1976 R1C1)
Integrator:
Next part of the triangular wave generator is the op amp integrator. Instead of using a simple
passive RC integrator, an active integrator based on op amp is used here. The op amp IC used in
this stage is also uA741 (IC2). Resistor R5 in conjunction with R4 sets the gain of the integrator
and resistor R5 in conjunction with C2 sets the bandwidth. The square wave signal is applied to

the inverting input of the op amp through the input resistor R4. The op amp integrator part of the
circuit is shown in the figure below.

Lets assume the positive side of the square wave is first applied to the integrator. By virtue
capacitor C2 offers very low resistance to this sudden shoot in the input and C2 behaves
something like a short circuit. The feedback resistor R5 connected in parallel to C2 can be put
aside because R5 has almost zero resistance at the moment. A serious amount of current flows
through the input resistor R4 and the capacitor C2 bypasses all these current. As a result the
inverting input terminal (tagged A) of the op amp behaves like a virtual ground because all the
current flowing into it is drained by the capacitor C2. The gain of the entire circuit (Xc2/R4) will
be very low and the entire voltage gain of the circuit will be close the zero.
After this initial kick the capacitor starts charging and it creates an opposition to the input
current flowing through the input resistor R4. The negative feedback compels the op amp to
produce a voltage at its out so that it maintains the virtual ground at the inverting input. Since the
capacitor is charging its impedance Xc keeps increasing and the gain Xc2/R4 also keeps
increasing. This results in a ramp at the output of the op amp that increases in a rate proportional
to the RC time constant (T=R4C2) and this ramp increases in amplitude until the capacitor is
fully charged.
When the input to the integrator (square wave) falls to the negative peak the capacitor quickly
discharges through the input resistor R4 and starts charging in the opposite polarity. Now the
conditions are reversed and the output of the op amp will be a ramp that is going to the negative
side at a rate proportional to the R4R2 time constant. This cycle is repeated and the result will be
a triangular waveform at the output of the op amp integrator.

UNIT-5
5.1 DIGITAL TO ANALOG CONVERTER (D/A)
A D/A Converter is used when the binary output from a digital system is to be converted into its
equivalent analog voltage or current. The binary output will be a sequence of 1s and 0s. Thus
they may be difficult to follow. But, a D/A converter help the user to interpret easily.
Digital to Analog Converter using Binary-Weighted Resistors:
A D/A converter using binary-weighted resistors is shown in the figure below. In the circuit, the
op-amp is connected in the inverting mode. The op-amp can also be connected in the noninverting mode. The circuit diagram represents a 4-digit converter. Thus, the number of binary
inputs is four.

We know that, a 4-bit converter will have 24 = 16 combinations of output. Thus, a corresponding
16 outputs of analog will also be present for the binary inputs.
Four switches from b0 to b3 are available to simulate the binary inputs: in practice, a 4-bit
binary counter such as a 7493 can also be used.

Working
The circuit is basically working as a current to voltage converter.
b0 is closed
It will be connected directly to the +5V.
Thus, voltage across R = 5V
Current through R = 5V/10kohm = 0.5mA
Current through feedback resistor, Rf = 0.5mA (Since, Input bias current, IB is negligible)
Thus, output voltage = -(1kohm)*(0.5mA) = -0.5V
b1 is closed, b0 is open
R/2 will be connected to the positive supply of the +5V.
Current through R will become twice the value of current (1mA) to flow through Rf.
Thus, output voltage also doubles.
b0 and b1 are closed
Current through Rf = 1.5mA
Output voltage = -(1kohm)*(1.5mA) = -1.5V
Thus, according to the position (ON/OFF) of the switches (bo-b3), the corresponding binaryweighted currents will be obtained in the input resistor. The current through Rf will be the sum
of these currents. This overall current is then converted to its proportional output voltage.
Naturally, the output will be maximum if the switches (b0-b3) are closed.
V0 = -Rf *([b0/R][b1/(R/2)][b2/(R/4)][b3/(R/8)]) where each of the inputs b3, b2, b1, and b0
may either be HIGH (+5V) or LOW (0V).
The graph with the analog outputs versus possible combinations of inputs is shown below.

Digital-to-Analog Converter Circuit - Binary-Weighted Resistors Method Graph


The output is a negative going staircase waveform with 15 steps of -).5V each. In practice, due to
the variations in the logic HIGH voltage levels, all the steps will not have the same size. The

value of the feedback resistor Rf changes the size of the steps. Thus, a desired size for a step can
be obtained by connecting the appropriate feedback resistor. The only condition to look out for is
that the maximum output voltage should not exceed the saturation levels of the op-amp. Metalfilm resistors are more preferred for obtaining accurate outputs.
Disadvantages
If the number of inputs (>4) or combinations (>16) is more, the binary-weighted resistors may
not be readily available. This is why; R and 2R method is more preferred as it requires only two
sets of precision resistance values.
5.2 Digital to Analog Converter with R and 2R Resistors
A D/A converter with R and 2R resistors is shown in the figure below. As in the binary-weighted
resistors method, the binary inputs are simulated by the switches (b0-b3), and the output is
proportional to the binary inputs. Binary inputs can be either in the HIGH (+5V) or LOW (0V)
state. Let b3 be the most significant bit and thus is connected to the +5V and all the other switchs
are connected to the ground.

Thus, according to Thevenins equivalent resistance, RTH,


RTH = [{[(2RII2R + R)} II2R] + R}II2R] + R = 2R = 20kOhms.
The resultant circuit is shown below.

Graph is given below.

Digital to Analog Converter with R and 2R Resistors - Graph


In the figure shown above, the negative input is at virtual ground, therefore the current through
RTH=0.
Current through 2R connected to +5V = 5V/20kohm = 0.25 mA
The current will be the same as that in Rf.
Vo = -(20kohm)*(0.25mA) = -5V
Output voltage equation is given below.
V0 = -Rf (b3/2R+b2/4R+b1/8R+b0/16R)
5.3 Analog to Digital Converters (A/D)
This type of converter is used to convert analog voltage to its corresponding digital output. The
function of the analog to digital converter is exactly opposite to that of a DIGITAL TO
ANALOG CONVERTER. Like a D/A converter, an A/D converter is also specified as 8, 10, 12

or 16 bit. Though there are many types of A/D converters, we will be discussing only about the
successive approximation type.
Successive Approximation Type Analog to Digital Converter
A successive approximation A/D converter consists of a comparator, a successive approximation
register (SAR), output latches, and a D/A converter. The circuit diagram is shown below.

Successive Approximation Type Analog to Digital Converter


The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A converter.
The analog output Va of the D/A converter is then compared to an analog signal Vin by the
comparator. The output of the comparator is a serial data input to the SAR. Till the digital output
(8 bits) of the SAR is equivalent to the analog input Vin, the SAR adjusts itself. The 8-bit latch at
the end of conversation holds onto the resultant digital data output.
Working:
At the start of a conversion cycle, the SAR is reset by making the start signal (S) high. The MSB
of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is introduced. The

output is given to the D/A converter which produces an analog equivalent of the MSB and is
compared with the analog input Vin.
If comparator output is LOW, D/A output will be greater than Vin and the MSB will be cleared
by the SAR.If comparator output is HIGH, D/A output will be less than Vin and the MSB will be
set to the next position (Q7 to Q6) by the SAR.
According to the comparator output, the SAR will either keep or reset the Q6 bit. This process
goes on until all the bits are tried. After Q0 is tried, the SAR makes the conversion complete
(CC) signal HIGH to show that the parallel output lines contain valid data. The CC signal in turn
enables the latch, and digital data appear at the output of the latch. As the SAR determines each
bit, digital data is also available serially. As shown in the figure above, the CC signal is
connected to the start conversion input in order to convert the cycle continuously.
The biggest advantage of such a circuit is its high speed. It may be more complex than an A/D
converter, but it offers better resolution.
5.4 IC 555 TIMER:
The 555 timer IC was introduced in the year 1970 by Signetic Corporation and gave the
name SE/NE 555 timer. It is basically a monolithic timing circuit that produces accurate and
highly stable time delays or oscillation. When compared to the applications of an op-amp in the
same areas, the 555IC is also equally reliable and is cheap in cost. Apart from its applications as
a monostable multivibrator and astable multivibrator, a 555 timer can also be used in dc-dc
converters, digital logic probes, waveform generators, analog frequency meters and
tachometers, temperature measurement and control devices,voltage regulators etc. The timer IC
is setup to work in either of the two modes one-shot or monostabl or as a free-running or
astable multivibrator.The SE 555 can be used for temperature ranges between 55C to 125 .
The NE 555 can be used for a temperature range between 0 to 70C.
The important features of the 555 timer are :
It operates from a wide range of power supplies ranging from + 5 Volts to + 18 Volts supply
voltage.
Sinking or sourcing 200 mA of load current.
The external components should be selected properly so that the timing intervals can be made
into several minutes along with the frequencies exceeding several hundred kilo hertz.
The output of a 555 timer can drive a transistor-transistor logic (TTL) due to its high current
output.
It has a temperature stability of 50 parts per million (ppm) per degree Celsius change in
temperature, or equivalently 0.005 %/ C.
The duty cycle of the timer is adjustable.

The maximum power dissipation per package is 600 mW and its trigger and reset inputs has
logic compatibility. More features are listed in the datasheet.

IC Pin Configuration

555 Timer IC Pin Configuration


The 555 Timer IC is available as an 8-pin metal can, an 8-pin mini DIP (dual-in-package) or a
14-pin DIP. The pin configuration is shown in the figures.
This IC consists of 23 transistors, 2 diodes and 16 resistors. The use of each pin in the IC is
explained below. The pin numbers used below refers to the 8-pin DIP and 8-pin metal can
packages. These pins are explained in detail, and you will get a better idea after going through
the entire post.

Pin 1: Grounded Terminal: All the voltages are measured with respect to the Ground terminal.
Pin 2: Trigger Terminal: The trigger pin is used to feed the trigger input hen the 555 IC is set
up as a monostable multivibrator. This pin is an inverting input of a comparator and is
responsible for the transition of flip-flop from set to reset. The output of the timer depends on the
amplitude of the external trigger pulse applied to this pin. A negative pulse with a dc level
greater than Vcc/3 is applied to this terminal. In the negative edge, as the trigger passes through
Vcc/3, the output of the lower comparator becomes high and the complimentary of Q becomes
zero. Thus the 555 IC output gets a high voltage, and thus a quasi stable state.
Pin 3: Output Terminal: Output of the timer is available at this pin. There are two ways in
which a load can be connected to the output terminal. One way is to connect between output pin
(pin 3) and ground pin (pin 1) or between pin 3 and supply pin (pin 8). The load connected
between output and ground supply pin is called the normally on load and that connected
between output and ground pin is called the normally off load.
Pin 4: Reset Terminal: Whenever the timer IC is to be reset or disabled, a negative pulse is
applied to pin 4, and thus is named as reset terminal. The output is reset irrespective of the input
condition. When this pin is not to be used for reset purpose, it should be connected to + VCC to
avoid any possibility of false triggering.
Pin 5: Control Voltage Terminal: The threshold and trigger levels are controlled using this pin.
The pulse width of the output waveform is determined by connecting a POT or bringing in an
external voltage to this pin. The external voltage applied to this pin can also be used to modulate
the output waveform. Thus, the amount of voltage applied in this terminal will decide when the

comparator is to be switched, and thus changes the pulse width of the output. When this pin is
not used, it should be bypassed to ground through a 0.01 micro Farad to avoid any noise
problem.
Pin 6: Threshold Terminal: This is the non-inverting input terminal of comparator 1, which
compares the voltage applied to the terminal with a reference voltage of 2/3 VCC. The amplitude
of voltage applied to this terminal is responsible for the set state of flip-flop. When the voltage
applied in this terminal is greater than 2/3Vcc, the upper comparator switches to +Vsat and the
output gets reset.
Pin 7 : Discharge Terminal: This pin is connected internally to the collector of transistor and
mostly a capacitor is connected between this terminal and ground. It is called discharge terminal
because when transistor saturates, capacitor discharges through the transistor. When the
transistor is cut-off, the capacitor charges at a rate determined by the external resistor and
capacitor.
Pin 8: Supply Terminal: A supply voltage of + 5 V to + 18 V is applied to this terminal with
respect to ground (pin 1).
555 Timer Basics
The 555 timer combines a relaxation oscillator, two comparators, an R-S flip-flop, and a
discharge capacitor.

S-R-Flip Flop
As shown in the figure, two transistors T1 and T2 are cross coupled. The collector of transistor
T1 drives the base of transistor T2 through the resistor Rb2. The collector of transistor T2 drives
the base of transistor T1 through resistor Rb1. When one of the transistor is in the saturated state,
the other transistor will be in the cut-off state. If we consider the transistor T1 to be saturated,
then the collector voltage will be almost zero. Thus there will be a zero base drive for transistor

T2 and will go into cut-off state and its collector voltage approaches +Vcc. This voltage is
applied to the base of T1 and thus will keep it in saturation.

S-R Flip Flop Symbol


Now, if we consider the transistor T1 to be in the cut-off state, then the collector voltage of T1
will be equal to +Vcc. This voltage will drive the base of the transistor T2 to saturation. Thus,
the saturated collector output of transistor T2 will be almost zero. This value when fedback to the
base of the transistor T1 will drive it to cut-off. Thus, the saturation and cut-off value of anyone
of the transistors decides the high and low value of Q and its compliment. By adding more
components to the circuit, an R-S flip-flop is obtained. R-S flip-flop is a circuit that can set the Q
output to high or reset it low. Incidentally, a complementary (opposite) output Q is available
from the collector of the other transistor. The schematic symbol for a S-R flip flop is also shown
above. The circuit latches in either the Q state or its complimentary state. A high value of S input
sets the value of Q to go high. A high value of R input resets the value of Q to low. Output Q
remains in a given state until it is triggered into the opposite state.

555 IC Timing Circuit


Basic Timing Concept
From the figure above, assuming the output of the S-R flip flop, Q to be high. This high value is
passed on to the base of the transistor, and the transistor gets saturated, thus producing a zero
voltage at the collector. The capacitor voltage is clamped at ground, that is, the capacitor C is
shorted and cannot charge.
The inverting input of the comparator is fed with a control voltage, and the non-inverting input is
fed with a threshold voltage. With R-S flip flop set, the saturated transistor holds the threshold
voltage at zero. The control voltage, however, is fixed at 2/3 VCC, that is, at 10 volts, because of
the voltage divider.
Suppose that a high voltage is applied to the R input. This resets the flip-flop R-Output Q goes
low and the transistor is cut-off. Capacitor C is now free to charge. As this capacitor C charges,
the threshold voltage rises. Eventually, the threshold voltage becomes slightly greater than (+ 10
V). The output of the comparator then goes high, forcing the R S flip-flop to set. The high Q
output saturates the transistor, and this quickly discharges the capacitor. An exponential rise is
across the capacitor C, and a positive going pulse appears at the output Q. Thus capacitor voltage
VC is exponential while the output is rectangular. This is shown in the figure above.

5.5 Block Diagram

555 IC Timer Block Diagram


The block diagram of a 555 timer is shown in the above figure. A 555 timer has two
comparators, which are basically 2 op-amps), an R-S flip-flop, two transistors and a resistive
network.
Resistive network consists of three equal resistors and acts as a voltage divider.
Comparator 1 compares threshold voltage with a reference voltage + 2/3 VCC volts.
Comparator 2 compares the trigger voltage with a reference voltage + 1/3 VCC volts.
Output of both the comparators is supplied to the flip-flop. Flip-flop assumes its state according
to the output of the two comparators. One of the two transistors is a discharge transistor of which
collector is connected to pin 7. This transistor saturates or cuts-off according to the output state
of the flip-flop. The saturated transistor provides a discharge path to a capacitor connected
externally. Base of another transistor is connected to a reset terminal. A pulse applied to this
terminal resets the whole timer irrespective of any input.
5.6 Working Principle
Refer Block Diagram of 555 timer IC given above:
The internal resistors act as a voltage divider network, providing (2/3)Vcc at the non-inverting
terminal of the upper comparator and (1/3)Vcc at the inverting terminal of the lower comparator.
In most applications, the control input is not used, so that the control voltage equals +(2/3) VCC.

Upper comparator has a threshold input (pin 6) and a control input (pin 5). Output of the upper
comparator is applied to set (S) input of the flip-flop. Whenever the threshold voltage exceeds
the control voltage, the upper comparator will set the flip-flop and its output is high. A high
output from the flip-flop when given to the base of the discharge transistor saturates it and thus
discharges the transistor that is connected externally to the discharge pin 7. The complementary
signal out of the flip-flop goes to pin 3, the output. The output available at pin 3 is low. These
conditions will prevail until lower comparator triggers the flip-flop. Even if the voltage at the
threshold input falls below (2/3) VCC, that is upper comparator cannot cause the flip-flop to
change again. It means that the upper comparator can only force the flip-flops output high.
To change the output of flip-flop to low, the voltage at the trigger input must fall below + (1/3)
Vcc. When this occurs, lower comparator triggers the flip-flop, forcing its output low. The
low output from the flip-flop turns the discharge transistor off and forces the power amplifier to
output a high. These conditions will continue independent of the voltage on the trigger input.
Lower comparator can only cause the flip-flop to output low.
From the above discussion it is concluded that for the having low output from the timer 555, the
voltage on the threshold input must exceed the control voltage or + (2/3) VCC. This also turns the
discharge transistor on. To force the output from the timer high, the voltage on the trigger input
must drop below +(1/3) VCC. This turns the discharge transistor off.
A voltage may be applied to the control input to change the levels at which the switching occurs.
When not in use, a 0.01 nano Farad capacitor should be connected between pin 5 and ground to
prevent noise coupled onto this pin from causing false triggering.
Connecting the reset (pin 4) to a logic low will place a high on the output of flip-flop. The
discharge transistor will go on and the power amplifier will output a low. This condition will
continue until reset is taken high. This allows synchronization or resetting of the circuits
operation. When not in use, reset should be tied to +VCC.
5.7 MONOSTABLE MULTIVIBRATOR:
A monostable multivibrator (MMV) often called a one-shot multivibrator, is a pulse generator
circuit in which the duration of the pulse is determined by the R-C network,connected externally
to the 555 timer. In such a vibrator, one state of output is stable while the other is quasi-stable
(unstable). For auto-triggering of output from quasi-stable state to stable state energy is stored by
an externally connected capacitor C to a reference level. The time taken in storage determines the
pulse width. The transition of output from stable state to quasi-stable state is accomplished by
external triggering. The schematic of a 555 timer in monostable mode of operation is shown in
figure.

Monostable Multivibrator Circuit details


Pin 1 is grounded. Trigger input is applied to pin 2. In quiescent condition of output this input is
kept at + VCC. To obtain transition of output from stable state to quasi-stable state, a negativegoing pulse of narrow width (a width smaller than expected pulse width of output waveform)
and amplitude of greater than + 2/3 VCC is applied to pin 2. Output is taken from pin 3. Pin 4 is
usually connected to + VCC to avoid accidental reset. Pin 5 is grounded through a 0.01 u F
capacitor to avoid noise problem. Pin 6 (threshold) is shorted to pin 7. A resistor RA is connected
between pins 6 and 8. At pins 7 a discharge capacitor is connected while pin 8 is connected to
supply VCC.

555 IC Monostable Multivibrator Operation:


The operation of the circuit is explained below:

Initially, when the output at pin 3 is low i.e. the circuit is in a stable state, the transistor is on and
capacitor- C is shorted to ground. When a negative pulse is applied to pin 2, the trigger input
falls below +1/3 VCC, the output of comparator goes high which resets the flip-flop and
consequently the transistor turns off and the output at pin 3 goes high. This is the transition of the
output from stable to quasi-stable state, as shown in figure. As the discharge transistor is cutoff,
the capacitor C begins charging toward +VCC through resistance RA with a time constant equal to
RAC. When the increasing capacitor voltage becomes slightly greater than +2/3 VCC, the output
of comparator 1 goes high, which sets the flip-flop. The transistor goes to saturation, thereby
discharging the capacitor C and the output of the timer goes low, as illustrated in figure.
Thus the output returns back to stable state from quasi-stable state.
The output of the Monostable Multivibrator remains low until a trigger pulse is again applied.
Then the cycle repeats. Trigger input, output voltage and capacitor voltage waveforms are shown
in figure.
Monostable Multivibrator Design Using 555 timer IC
The capacitor C has to charge through resistance RA. The larger the time constant RAC, the
longer it takes for the capacitor voltage to reach +2/3VCC.
In other words, the RC time constant controls the width of the output pulse. The time during
which the timer output remains high is given as
tp = 1.0986 RAC
where RA is in ohms and C is in farads. The above relation is derived as below. Voltage across
the capacitor at any instant during charging period is given as
vc = VCC (1- e-t/RAC)
Substituting vc = 2/3 VCC in above equation we get the time taken by the capacitor to charge
from 0 to +2/3VCC.
So +2/3VCC. = VCC. (1 e-t/RAC) or t RAC loge 3 = 1.0986 RAC
So pulse width, tP = 1.0986 RAC s 1.1 RAC
The pulse width of the circuit may range from micro-seconds to many seconds. This circuit is
widely used in industry for many different timing applications.
5.8 AN ASTABLE MULTIVIBRATOR:
An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave
generating circuit. Unlike the monostable multivibrator, this circuit does not require any external
trigger to change the state of the output, hence the name free-running. Before going to make the
circuit, make sure your 555 IC is working. For that go through the article: How to test a 555 IC
for working An astable multivibrator can be produced by adding resistors and a capacitor to the
basic timer IC, as illustrated in figure. The timing during which the output is either high or low is
determined by the externally connected two resistors and a capacitor. The details of the astable
multivibrator circuit are given below.

in 1 is grounded; pins 4 and 8 are shorted and then tied to supply +Vcc, output (VOUT is taken
form pin 3; pin 2 and 6 are shorted and the connected to ground through capacitor C, pin 7 is
connected to supply + VCCthrough a resistor RA; and between pin 6 and 7 a resistor RB is
connected. At pin 5 either a bypass capacitor of 0.01 F is connected or modulation input is
applied.
Astable Multivibrator Operation
For explaining the operation of the timer 555 as an astable multivibrator, necessary internal
circuitry with external connections are shown in figure.
In figure, when Q is low or output VOUT is high, the discharging transistor is cut-off and the
capacitor C begins charging toward VCC through resistances RA and RB. Because of this, the
charging time constant is (RA + RB) C. Eventually, the threshold voltage exceeds +2/3 VCC, the
comparator 1 has a high output and triggers the flip-flop so that its Q is high and the timer output
is low. With Q high, the discharge transistor saturates and pin 7 grounds so that the capacitor C
discharges through resistance RB with a discharging time constant RB C. With the discharging of
capacitor, trigger voltage at inverting input of comparator 2 decreases. When it drops below
1/3VCC, the output of comparator 2 goes high and this reset the flip-flop so that Q is low and the
timer output is high. This proves the auto-transition in output from low to high and then to low
as, illustrated in figures. Thus the cycle repeats.

Astable Multivibrator using 555 IC -Design method


The time during which the capacitor C charges from 1/3 VCC to 2/3 VCC is equal to the time the
output is high and is given as tc or THIGH = 0.693 (RA + RB) C, which is proved below.
Voltage across the capacitor at any instant during charging period is given as,vc=VCC(1-et/RC)
The time taken by the capacitor to charge from 0 to +1/3 VCC

1/3 VCC

t/RC
VCC (1-e
)

The time taken by the capacitor to charge from 0 to +2/3 VCC


or t2 = RC loge 3 = 1.0986 RC
So the time taken by the capacitor to charge from +1/3 VCC to +2/3 VCC
tc = (t2 t1) = (10986 0.405) RC = 0.693 RC
Substituting R = (RA + RB) in above equation we have
THIGH = tc = 0.693 (RA + RB) C
where RA and RB are in ohms and C is in farads.
The time during which the capacitor discharges from +2/3 VCC to +1/3 VCC is equal to
the time the output is low and is given as
td or TL0W = 0.693 RB C where RB is in ohms and C is in farads The above equation is worked
out as follows: Voltage across the capacitor at any instant during discharging period is given as
vc = 2/3 VCC e- td/ RBC
Substituting vc = 1/3 VCC and t = td in above equation we have
+1/3 VCC = +2/3 VCC e- td/ RBC
Or td = 0.693 RBC
Overall period of oscillations, T = THIGH + TLOW = 0.693 (RA+ 2RB) C , The frequency of
oscillations being the reciprocal of the overall period of oscillations T is given as
f = 1/T = 1.44/ (RA+ 2RB)C
Equation indicates that the frequency of oscillation / is independent of the collector supply
voltage +VCC.
Often the term duty cycle is used in conjunction with the astable multivibrator.
The duty cycle, the ratio of the time tc during which the output is high to the total time period
T is given as
% duty cycle, D = tc / T * 100 = (RA + RB) / (RA + 2RB) * 100
From the above equation it is obvious that square wave (50 % duty cycle) output can not be
obtained unless RA is made zero. However, there is a danger in shorting resistance RA to zero.
With RA = 0 ohm, terminal 7 is directly connected to + VCC. During the discharging of capacitor
through RB and transistor, an extra current will be supplied to the transistor from VCC through a
short between pin 7 and +VCC. It may damage the transistor and hence the timer.
However, a symmetrical square wave can be obtained if a diode is connected across resistor RB,
as illustrated in dotted lines in figure. The capacitor C charges through RA and diode D to
approximately + 2/3VCC and discharges through resistor RB and terminal 7 (transistor) until the
capacitor voltage drops to 1/3 VCC. Then the cycle is repeated. To obtain a square wave output,
RA must be a combination of a fixed resistor R and a pot, so that the pot can be adjusted to give
the exact square wave.
Although the timer 555 has been used in a wide variety of often unique applications it is very
hard on its power supply lines, requiring quite a bit of current, and injecting many noise

transients. This noise will often be coupled into adjacent ICs falsely triggering them. The 7555 is
a CMOS version of the 555. Its quiescent current requirements are considerably lower than that
of 555, and the 7555 does not contaminate the power supply lines. It is pin compatible with the
555. So this CMOS version of the 555 should be the first choice when a 555 timer IC is to be
used.
5.9 Phase LOCKED LOOP (PLL)
Introduction to PLL
The concept of Phase Locked Loops (PLL) first emerged in the early 1930s.But the technology
was not developed as it now, the cost factor for developing this technology was very high. Since
the advancement in the field of integrated circuits, PLL has become one of the main building
blocks in the electronics technology. In present, the PLL is available as a single IC in the
SE/NE560 series (560, 561, 562, 564, 565 and 567) to further reduce the buying cost ,the
discrete ICs are used to construct a PLL.
PLL Applications
Frequency Modulation (FM) stereo decoders, FM Demodulation networks for FM operation.
Frequency synthesis that provides multiple of a reference signal frequency.
Used in motorspeed controls, tracking filters.
Used in frequency shift keying (FSK) decodes for demodulation carrier frequencies.
PLL Block Diagram
The block diagram of a basic PLL is shown in the figure below. It is basically a flip flop
consisting of a phase detector, a low pass filter (LPF),and a Voltage Controlled Oscillator
(VCO).

Block Diagram - Phase Locked Loops


The input signal Vi with an input frequency fi is passed through a phase detector. A phase
detector basically a comparator which compares the input frequency fiwith the feedback
frequency fo .The phase detector provides an output error voltage Ver (=fi+fo),which is a DC
voltage. This DC voltage is then passed on to an LPF. The LPF removes the high frequency

noise and produces a steady DC level, Vf (=Fi-Fo). Vf also represents the dynamic
characteristics of the PLL.
The DC level is then passed on to a VCO. The output frequency of the VCO (fo) is directly
proportional to the input signal. Both the input frequency and output frequency are compared and
adjusted through feedback loops until the output frequency equals the input frequency. Thus the
PLL works in these stages free-running, capture and phase lock.
As the name suggests, the free running stage refer to the stage when there is no input voltage
applied. As soon as the input frequency is applied the VCO starts to change and begin producing
an output frequency for comparison this stage is called the capture stage. The frequency
comparison stops as soon as the output frequency is adjusted to become equal to the input
frequency. This stage is called the phase locked state.
Now let us study in detail about the various parts of a PLL The phase detector, Low Pass Filter
and Voltage Controlled Oscillator.
1. Phase Detector
This comparator circuit compares the input frequency and the VCO output frequency and
produces a dc voltage that is proportional to the phase difference between the two frequencies.
The phase detector used in PLL may be of analog or digital type. Even though most of the
monolithic PLL integrated circuits use analog phase detectors, the majority of discrete phase
detectors are of the digital type. One of the most commonly used analog phase detector is the
double balanced mixer circuit. Some of the common digital type phase detectors are
5.10 Exclusive OR Phase Detector
An exclusive OR phase detector is shown in the figure below.

It is obtained as a CMOS IC of type 4070. Both the frequencies are provided as an input to the
EX OR phase detector. Obeying the EX-OR concept the output becomes HIGH only if either of
the inputs fi or fo becomes HIGH. All other conditions will produce a LOW output. Let us
consider a waveform where the input frequency leads the output frequency by degrees. That is,

fi and fo has a phase difference of degrees. The dc output voltage of the comparator will be a
function of the phase difference between its two inputs.
The figure shows the graph of DC output voltage as a function of the phase difference between fi
and fo. The output DC voltage is maximum when the phase detector is 180.This type of phase
detector is used when both fi and fo are square waves.

2. Low Pass Filter (LPF)


A Low Pass Filter (LPF) is used in Phase Locked Loops (PLL) to get rid of the high frequency
components in the output of the phase detector. It also removes the high frequency noise. All
these features make the LPF a critical part in PLL and helps control the dynamic characteristics
of the whole circuit. The dynamic characteristics include capture and lock ranges, bandwidth,
and transient response. The lock range is the tracking range where the range of frequencies of the
PLL system follows the changes in the input frequency. The capture range is the range in which
the Phase Locker Loops attains the Phase Lock.
When the filter bandwidth is reduced, the response time increases .But this reduces the capture
range. But it also helps in reducing noise and in maintaining the locked loop through momentary
losses of signal. Two types of passive filter are used for the LPF circuit in a PLL. An amplifier is
used also with LPF to obtain gain. The active filter used in PLL is shown below.
3. Voltage Controlled Oscillator (VCO)
The main function of the VCO is to generate an output frequency that is directly proportional to
the input voltage. The connection diagram of a SE/NE 566 VCO is shown in the figure below.
The maximum frequency of the VCO is 500 KHz.
This VCO provides simultaneous square wave and triangular wave outputs as a function of the
input voltage. The frequency of oscillation is determined by the resistor R and capacitor C along
with the voltage Vc applied to the control terminal.

5.11 IC 565 PLL


A PLL is also available as an integrated circuit IC. IC 565 PLL can be used for FM detection.
Figure shows the circuit diagram of an FM detector using 565 PLL.

Internal Block Diagram of IC 565


The internal block diagram shows that IC 565 PLL consists of phase detector, VCO, and
amplifier. The amplifier also functions as the low pass filter. This is a 14 pin dual in line
package.

In figure, notice that PLL IC consists of two power supply pins marked Vcc. The positive
terminal of the Vcc is connected to pin number 10, and the negative (ground) terminal of Vcc is
connected to pin number 1. The output signal to the phase detector is applied to pin numbers 2
and 3. The VCO output is applied to the phase detector through pin number 5. The output of the
phase detector is internally connected to the amplifier (low-pass filter).
The output or the phase detector is low-pass filtered and amplified by the amplifier stage. The
Output or the amplifier is the control voltage that is applied to VCO to force it to track the
incoming frequency. The control voltage is also available at pin number 7. This is the output
signal. In the ease of FM demodulator, the signal at pin number 7 is the modulating signal. The
amplifier also generates an output at pin number 6for reference purposes.
The VCO gets its control voltage internally from the amplifier and its output at pin number 4.
The VCO output should be given to the phase detector through pin number 5. It is customary to
short pin numbers 4 and 5 so that the VCO output is applied directly to the phase detector. The
external resistor and capacitor can set the free-running frequency of the VCO. The resistor and
capacitor are called the timing resistor and the timing capacitor. The timing resistor is connected
at pin number 8, and the timing capacitor is connected at pin number 9.
Pin numbers 11, 12, 13, and 14 are not connected because they do not have any internal circuitry
with them. These are marked as NC in Figure (b). These pins are there because they are
connected to IC.