U6264ASA07

Automotive 8K x 8 SRAM
Features

Description

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The U6264ASA07 is a static RAM

manufactured using a CMOS process technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is

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8192 x 8 bit static CMOS RAM

70 ns Access Time
Common data inputs and outputs
Three-state outputs
Typ. operating supply current:
30 mA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges
-40 to 125 C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: SOP28 (300 mil)
SOP28 (330 mil)

available. The full CMOS data outputs have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by E2 =
L, the standby current (TTL) drops
to 150 A typ.

Pin Description

Pin Configuration

n.c.

28

VCC

A12

27

W (WE)

A7

26

E2 (CE2)

Signal Name

Signal Description

A6

25

A8

A0 - A12

Address Inputs

A5

24

A9

DQ0 - DQ7

Data In/Outputs

A4

23

A11

Chip Enable 1

E1

A3

22

G (OE)

21

A10

E2

Chip Enable 2

A2
A1

20

E1 (CE1)

Output Enable

A0

10

19

DQ7

Read/Write Enable

DQ0

11

18

DQ6

W
VCC

Power Supply Voltage

DQ1

12

17

DQ5

VSS

Ground

DQ2

13

16

DQ4

n.c.

not connected

VSS

14

15

DQ3

SOP

Top View

November 01, 2001

U6264ASA07

A3
A10

Memory Cell
Array
256 Rows x
256 Columns

DQ0
Sense Amplifier/
Write Control Logic

Address
Change
Detector

Clock
Generator

DQ1

Common Data I/O

A2

Row Decoder

A1

Column Decoder

A0

Row Address
Inputs

A4
A5
A6
A7
A8
A9
A11
A12

Column Address
Inputs

Block Diagram

DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

E2

VCC

VSS

E1

Truth Table
Operating Mode

E1

E2

DQ0 - DQ7

Standby/not
selected

High-Z

High-Z

Internal Read

High-Z

Read

Data Outputs, Low-Z

Write

Data Inputs, High-Z

* H or L

Characteristics
All voltages are referenced to V SS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times, in which cases transition is measured 200 mV from steady-state voltage.

Maximum Ratings

Symbol

Min.

Max.

Unit

VCC

-0.3

Input Voltage

VI

-0.3

VCC + 0.5

Output Voltage

VO

-0.3

VCC + 0.5

Power Dissipation

PD

Operating Temperature

Ta

-40

125

Tstg

-65

150

Power Supply Voltage

Storage Temperature

November 01, 2001

U6264ASA07
Recommended
Operating Conditions

Symbol

Conditions

Min.

Max.

Unit

Power Supply Voltage

VCC

4.5

5.5

Data Retention Voltage

VCC(DR)

2.0

Input Low Voltage*

VIL

-0.3

0.8

Input High Voltage

VIH

2.2

VCC+0.3

Min.

Max.

Unit

55

mA

mA

V
V

* -2 V at Pulse Width 10 ns

Electrical Characteristics

Symbol

Conditions

Supply Current - Operating Mode

ICC(OP)

VCC
VIL
VIH
tcW

=
=
=
=

Supply Current - Standby Mode

(TTL level)

ICC(SB)1

VCC
VE1 = V E2
or V E2

= 5.5 V
= 2.2 V
= 0.8 V

VCC
IOH

= 4.5 V
= -1.0 mA

Output High Voltage

TTL compatible
CMOS compatible

5.5 V
0.8 V
2.2 V
70 ns

VOH
VOH

2.4
0.85*VCC

Output Low Voltage

VOL

VCC
IOL

= 4.5 V
= 3.2 mA

0.4

Output High Current

IOH

-1

mA

IOL

=
=
=
=

Output Low Current

VCC
VOH
VCC
VOL

3.2

mA

30

10

-2

-2

4.5 V
2.4 V
4.5 V
0.4 V

Supply Current - Standby Mode

(CMOS level)

ICC(SB)

VCC
= 5.5 V
VE1 = VE2 = VCC - 0.2 V
= 0.2 V
or V E2

Supply Current - Data Retention Mode

ICC(DR)

VCC(DR)
VE1 = V E2
or V E2

= 3V
= VCC(DR) - 0.2 V
= 0.2 V

VCC
VIH
VCC
VIL

= 5.5 V
= 5.5 V
= 5.5 V
= 0V

VCC
VOH
VCC
VOL

= 5.5 V
= 5.5 V
= 5.5 V
= 0V

Input High Leakage Current

IIH

Input Low Leakage Current

IIL

Output Leakage Current

High at Three-State Outputs

IOHZ

Low at Three-State Outputs

IOLZ

November 01, 2001

U6264ASA07
Symbol
Switching Characteristics

Min.

Max.

Unit

tt(QX)

10

ns

tWC
tRC

tcW
tcR

70
70

ns
ns

Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid

tACE
tOE
tAA

ta(E)
ta(G)
ta(A)

70
40
70

ns
ns
ns

Pulse Widths
Write Pulse Width
Chip Enable to End of Write

tWP
tCW

tw(W)
tw(E)

50
65

ns
ns

Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time

tAS
tCW
tWP
tDS

tsu(A)
tsu(E)
tsu(W)
tsu(D)

0
65
50
35

ns
ns
ns
ns

Data Hold Time

Address Hold from End of Write

tDH
tAH

th(D)
th(A)

0
0

ns
ns

Output Hold Time from Address Change

tOH

tv(A)

ns

tHZCE

tdis(E)

25

ns

tHZWE
tHZOE

tdis(W)
tdis(G)

0
0

30
25

ns
ns

Alt.

IEC

Time to Output in Low-Z

tLZ

Cycle Time
Write Cycle Time
Read Cycle Time

E1 HIGH or E2 LOW to Output in High-Z

W LOW to Output in High-Z
G HIGH to Output in High-Z

Data Retention Mode E1-Controlled

Data Retention Mode E2-Controlled

VCC

VCC

4.5 V

4.5 V
VCC(DR) 2 V

VCC(DR) 2 V

2.2 V

2.2 V
tDR

Data Retention

trec

tDR
0.8 V

E1

Data Retention
VE2(DR) 0.2 V

E2
trec
0.8 V

0V

0V

VE2(DR) VCC(DR) - 0.2 V or VE2(DR) 0.2 V

VCC(DR) - 0.2 V VE1(DR) V CC(DR) + 0.3 V

Chip Deselect to Data Retention Time

Operating Recovery Time

tDR:
trec:

min 0 ns
min tcR

November 01, 2001

U6264ASA07
Test Configuration for Functional Check
(for TTL output levels)

VIL

1)

E1
E2
W
G

VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

960

Simultaneous measurement of all 8 output pins

VIH

Input level according to the

relevant test measurement

5V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

VO
30 pF1)
510

VSS

In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF.

Capacitance
Input Capacitance

Conditions

Symbol

VCC = 5.0 V
VI = VSS

CI

f
= 1 MHz
CO
Output
All
pins Capacitance
not under test must be connected
Ta = 25with
C ground by capacitors.

Min.

Max.

Unit

pF

10

pF

IC Code Numbers
U6264A S

Example

07

Type

Internal Code

Package
S1 = SOP28 (300 mil)

Access Time
07 = 70 ns

S = SOP28 (330 mil)

Operating Temperature Range

A = -40 to 125 C

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.

November 01, 2001

U6264ASA07
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)
tcR

Ai
DQi
Output

Addresses Valid
ta(A)
Output Data Valid

Previous Data Valid

tv(A)

Read Cycle 2 (during Read cycle: W = VIH)

tcR

Ai
E1

Addresses Valid
ta(E)

tsu(A)

tt(QX)

tdis(E)

tsu(A)

ta(E)

E2

ta(G)

G
DQi

tdis(E)

tt(QX)

tdis(G)
tt(QX)
High-Z

Output Data Valid

Output

Write Cycle 1 (W-controlled)

tcW

Ai

Addresses Valid
tsu(E)

th(A)

E1
tsu(E)

E2
W

tsu(A)

tw(W)

tsu(D)

DQi
Input

DQi

th(D)

Input Data Valid

tdis(W)

tt(QX)
High-Z

Output

November 01, 2001

U6264ASA07
Write Cycle 2 (E1-controlled)
tcW

Ai
E1

tsu(A)

E2

Addresses Valid
tw(E)

tsu(E)
tsu(W)

th(D)

tsu(D)

DQi
Input

th(A)

tt(QX)

Input Data Valid

tdis(W)

High-Z

DQi
Output

Write Cycle 3 (E2-controlled)

tcW

Ai

Addresses Valid
tsu(E)

th(A)

E1
tsu(A)

tw(E)

E2
tsu(W)

W
tsu(D)

DQi
Input
tt(QX)

th(D)
Input Data Valid

tdis(W)

DQi

High-Z

Output

L- or H-level

undefined

The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.

November 01, 2001

U6264ASA07

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured characteristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMDs warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.

November 01, 2001

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