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cm-3,
n-type Donor
+
P
group V
element
P+
electron
free
carrier
ion
B
group III
element
B+
ion
+
hole
free
carrier
do example on board
ni2 = 2.1x1020
Lecture Notes 6.2
Conduction in Semiconductors
doping provides free charge carriers, alters conductivity
conductivity, , in semic. w/ carrier densities n and p
= q(nn + pp), q electron charge, q = 1.6x10-19 [Coulombs]
n > p
resistivity, = 1/
resistance of an n+ or p+ region
R = l , A = wt
but is a function of
Temperature and Doping
Concentration
t
w
pn Junctions: Intro
What is a pn Junction?
boundaries
interface of p-type and
pn diode
n-type semiconductor
junction
junction of two materials forms a diode
p-type -
ionization of dopants
at material interface
contact
to n-side
p+
n+
depletion region
- - -
dielectric
insulator
(oxide)
n well
p-type Si wafer
p-type
In the Beginning
contact
to p-side
n-type
+
- - - + -+ - + - +
3
NA acceptors/cm
n-type
ND donors/cm
hole diffusion
hole current
electron diffusion
electron current
electric field
depletion region
p-type
3
NA acceptors/cm
immobile acceptor ions
(negative-charge)
- + ++
- + +
- +
- + +
xp
xn
n-type
ND donors/cm
immobile donor ions
(positive-charge)
Depletion Region
depletion region
- - + +
n-type
p-type
area at pn interface
+
- - - + + + ND
NA
void of free charges
- - + +
N acceptors/cm
N donors/cm
charge neutrality
x
x
immobile acceptor ions
immobile donor ions
(positive-charge)
must have equal charge on both sides (negative-charge)
W
q A xp NA = q A xn ND , A=junction area; xp, xn depth into p/n side
xp NA = xn ND
depletion region will extend further into the more lightly doped side
of the junction
3
Built-in Potential
diffusion of carriers leaves behind immobile charged ions
ions create an electric field which generates a built-in potential
NAND
0 = VT ln
2
n
i
Depletion Width
depletion region
p-type
W = xp + xn
2 (0 + VR )N D
xp =
(
)
qN
N
N
+
A
A D
NA
1
2 (0 + V R )N A
xn =
qN
N
N
+
(
)
A
D D
2 (0 + VR ) N D + N A
W =
q
N
N
D
A
NA acceptors/cm
2
immobile acceptor ions
(negative-charge)
n-type
- + ++
- + + N
D
- +
N donors/cm
- + +
3
xp
xn
N N
0 = VT ln A 2 D
ni
is the permittivity of Si
= 1.04x10-12 F/cm
= KS0, where 0 = 8.85x10-14 F/cm
and KS = 11.8 is the relative permittivity of silicon
2 (0 + V R )
if NA>>ND (p+n diode)
W xn =
qN
most of junction on n-side
D
2 (0 + VR )
most of junction on p-side W x p =
qN
A
C jo
Cj =
VR
1+
0
Junction Breakdown
qN A N D
C = A
jo
20 ( N A + N D )
C jo
Cj =
VR
3
1+
0
if reverse bias is too high (typically > 30V) can get strong reverse current flow
ECE 410, Prof. A. Mason
+ VD -
ID
ID
Vf
ID
VD
ID = IS e
VD VT
1
1
I S A
+
N
N
A
D
MOSFET Capacitor
MOSFETs move charge from drain to source underneath the gate,
if a conductive channel exists under the gate
Understanding how and why the conductive channel is produced is
important
MOSFET capacitor models the gate/oxide/substrate region
source and drain are ignored
substrate changes with applied gate voltage
D
G
gate
gate oxide
channel
Si substrate = bulk
=
B
VG >> 0
VG > 0
+++++++
+++++++++++
++++++++++
-------
p-type Si substrate
p-type Si substrate
depletion layer
depletion layer
Depletion
Inversion
In Depletion
Gate capacitance has 2 components
1) oxide capacitance
2) depletion capacitance of the substrate depletion region
Cdep = si/xd, xd = depth of depletion region into substrate
Cox
Cdep
Cgate = Cox (in series with) Cdep = Cox Cdep / (Cox+Cdep) < Cox
Cs in series add like Rs in parallel
In Inversion
free carries at the surface
Cgate = Cox
Cgate
Cox
accumulation
inversion
VG
depletion
Inversion Operation
MOSFET off unless in inversion
look more deeply at inversion operation
Surface Charge
QB = bulk charge, ion charge in depletion region under
1
the gate
2
depletion
region
QB, bulk
charge
electron
layer, Qe
Threshold Voltage
Vtn defined as gate voltage where Qe starts to form
Qe = -Cox (VG-Vtn)
Vtn is gate voltage required to
overcome material difference between silicon and oxide
establish depletion region in channel to max value/size
ECE 410, Prof. A. Mason
nMOS
source @ ground
VGS
Charge Flow
Current Flow
channel charge is
nMOS Channel Current (linear model:) assumes
constant from source to drain
VDS
n
L
I = Qc
L
I = nCox (W/L) (VG-Vtn) VDS : linear model, assumes constant charge in channel
similar analysis applies for pMOS, see textbook
ECE 410, Prof. A. Mason
assumes constant charge in channel, valid only for very small VDS
similar analysis
applies for pMOS,
see textbook
Rn =
W
(VGS Vtn )
L
1
Rp =
W
p Cox VSG Vtp
L
nCox
VD
Linear Region
I D = QI ( y )V ( y )
Qe = -Cox (VGS-Vtn)
ID = n Qe (W/L) VDS
VGS
Triode Region
ID =
[
2(V
L
n COX W
2
GS
2
Vt )V DS V DS
square law
equation
ID =
n C OX W
2
(VGS Vt )
ID =
[2(V
L
n COX W
2
GS
2
Vt )V DS V DS
Other Stuff
Transconductance
process transconductance, k = n Cox
Surface Mobility
L (drawn)
Leff = L(drawn) 2 LD X d
2 (V (VG Vt ))
X d = s D
qN
A
G
xd
LD
~xd
Leff
Lecture Notes 6.19
Corrected ID equation
ID =
Veff = VGS - Vtn
nCOX W
2
Body Effect
pMOS Equations
Analysis of nMOS applies to pMOS with
following modifications
physical
equations
other factors
Transistor Sizing
Channel Resistance
ON resistance of transistors
Rn = 1/(nCox (W/L) (VGS-Vtn) )
Rn
Rp
Vtn
VDD-|Vtp|
VG
to match resistance, Rn = Rp
adjust Wn/Wp to balance for n > p
ECE 410, Prof. A. Mason
Transistor Sizing
Channel Resistances
Rn = 1/(nCox (W/L) (VG-Vtn) )
Rp = 1/(pCox (W/L) (VG-|Vtp|) )
Rn/Rp = n/p
if Vtn = |Vtp|, (W/L)n = (W/L)p
to set Rn = Rp
Negative Impact
CGp = r CGn larger gate = higher capacitance
ECE 410, Prof. A. Mason
MOSFET RC Model
Modeling MOSFET resistance and capacitance is very
important for transient characteristics of the device
RC Model
time constant
at drain, D
D = CD Rn
Rn = 2/{n[2(VGS-Vtn)-VDS]}
Rn = 2VDS / [n (VGS-Vtn)2]
Rn = 1/[n(VDD-Vtn)]
Lecture Notes 6.24
Gate
vg
Cgs
Cgd
+
vgs
-
Cgs
Cgd
Cgb
Cdb
Csb
no Csd!
gmvgs gmbvsb
is vs
Source
Model Capacitances
Cgb
ro
Drain v
d
id
Cdb
Csb
Body (Bulk)
MOSFET Physical
Capacitances
layer overlap
pn junction
ECE 410, Prof. A. Mason
RC Model Capacitances
Why do we care?
capacitances determine switching speed
Important Notes
models developed for saturation (active) region
models presented are simplified (not detailed)
RC Model Capacitances
Source Capacitance
models capacitance at the Source node
CS = CGS + CSB
Drain Capacitance
models capacitance at the Drain node
CD = CGD + CDB What are CGS, CGD, CSB, and CDB?
ECE 410, Prof. A. Mason
CGB = 0
Bulk Capacitance
CSB (Source-Bulk) and CDB (Drain-Bulk)
pn junction capacitances
1
q N A N D 2
V
R
C jo = A
C j = C jo 1 +
(
)
2
N
+
N
D
0
0 A
ND
NA
VR
1 +
q N A
C jo =
2
0
mj
N AND
0 = VT ln
2
n
i
Cj = Cjo
Junction Capacitance
Bottom Capacitance
Cbot = Cj Abot
Abot = X W
xj
Sidewall Capacitance
Csw = Cjsw Psw
Cjsw = Cj xj [F/cm]
xj = junction depth
Gate
vg
Cgs
RC Model Capacitances
Source Capacitance
CS = CGS + CSB
Drain Capacitance
CD = CGD + CDB
Cgd
+
vgs
-
i s vs
Source
Cgb
ro
gmvgs gmbvsb
Drain v
d
id
Cdb
Csb
Body (Bulk)
Junction Areas
Note: calculations assume following design rules
poly size, L = 2
poly space to contact, 2
contact size, 2
active overlap of contact, 1
W = 4
X1 = 5, X2= 2, X3 = 6
X1
X2
much smaller!
242
Area: X3 W =
=
Perimeter: 2(X3 + W) = 20
X3
largest area!
ECE 410, Prof. A. Mason