Beruflich Dokumente
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DS3232
LE
AVAILAB
Features
Ordering Information
PART
DS3232S#
DS3232SN#
Applications
Functional
Diagrams
Utility Power
Meters
Servers
Telematics
GPS
TEMP RANGE
0C to +70C
20 SO
DS3232
20 SO
DS3232N
VCC
RPU
VCC
SCL
SDA
RST
SCL
SDA
RST
P
RPU
PUSHBUTTON
RESET
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DS3232
GND
Pin Configuration
TOP VIEW
VCC
VCC
TOP
MARK
-40C to +85C
PINPACKAGE
N.C. 1
20 SCL
N.C. 2
19 N.C.
32kHz 3
18 SCL
INT/SQW
VCC 4
32kHz
VBAT
INT/SQW 5
N.C.
N.C.
N.C.
N.C.
N.C.
17 SDA
DS3232
16 VBAT
RST 6
15 GND
N.C. 7
14 N.C.
N.C. 8
13 N.C.
N.C. 9
12 N.C.
N.C. 10
11 N.C.
SO
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxims website at www.maximintegrated.com.
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, VBAT, 32kHz, SCL, SDA, RST,
INT/SQW Relative to Ground.............................-0.3V to +6.0V
Junction-to-Ambient Thermal Resistance (JC) (Note 1)..55.1C/W
Junction-to-Case Thermal Resistance (JC) (Note 1)..........24C/W
Operating Temperature Range
(noncondensing) .............................................-40C to +85C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MIN
TYP
MAX
VCC
2.3
3.3
5.5
VBAT
2.3
3.0
5.5
VIH
0.7 x
VCC
VCC +
0.3
VIL
-0.3
+0.3 x
VCC
Supply Voltage
SYMBOL
CONDITIONS
UNITS
V
ELECTRICAL CHARACTERISTICS
(VCC = 2.3V to 5.5V, VCC = active supply (see Table 1), TA = -40C to +85C, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
Active Supply Current
SYMBOL
CONDITIONS
ICCA
ICCS
ICCSCONV
VPF
MIN
TYP
MAX
VCC = 3.3V
200
VCC = 5.5V
325
VCC = 3.3V
120
VCC = 5.5V
160
VCC = 3.3V
500
VCC = 5.5V
600
UNITS
A
2.45
2.575
2.70
A
V
ACTIVE SUPPLY (Table 1 ) (2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted) (Note 2)
Logic 1 Output, 32kHz
IOH = -1mA
IOH = -0.75mA
IOH = -0.14mA
VOH
2.0
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.3V to 5.5V, VCC = active supply (see Table 1), TA = -40C to +85C, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25C, unless otherwise noted.) (Notes 2, 3)
MAX
UNITS
PARAMETER
SYMBOL
VOL
IOL = 3mA
0.4
VOL
IOL = 1mA
0.4
ILO
+1
-1
+1
-200
+10
ILI
IOL
CONDITIONS
MIN
-1
TYP
TCXO
Output Frequency
fOUT
Duty Cycle
(Revision A3 Devices)
32.768
f/fOUT
f/V
VCC = 3.3V or
VBAT = 3.3V
-40C to 0C and
+40C to +85C
31
69
-2
+2
-3.5
+3.5
f/LSB
Specified at:
Temperature Accuracy
Temp
1
-40C
0.7
+25C
0.1
+70C
0.4
+85C
Crystal Aging
f/f0
After reflow,
not production tested
kHz
%
ppm
ppm/V
ppm
0.8
-3
+3
First year
1.0
010 years
5.0
C
ppm
ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER
Active Battery Current
(Note 5)
Timekeeping Battery Current
(Note 5)
Temperature Conversion Current
Data-Retention Current
Maxim Integrated
SYMBOL
CONDITIONS
IBATA
EOSC = 0, BBSQW = 0,
SCL = 400kHz, BB32kHz = 0
IBATT
EOSC = 0, BBSQW = 0,
SCL = SDA = 0V,
BB32kHz = 0,
CRATE0 = CRATE1 = 0
IBATTC
IBATTDR
MIN
TYP
MAX
VBAT = 3.3V
80
VBAT = 5.5V
200
VBAT = 3.4V
1.5
2.5
VBAT = 5.5V
1.5
3.0
UNITS
A
600
100
nA
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
AC ELECTRICAL CHARACTERISTICS
(Active supply (see Table 1) = 2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tHD:DAT
tSU:DAT
tSU:STA
CONDITIONS
MIN
TYP
MAX
Fast mode
100
400
Standard mode
0.04
100
Fast mode
1.3
Standard mode
4.7
Fast mode
0.6
Standard mode
4.0
Fast mode
1.3
25,000
Standard mode
4.7
25,000
Fast mode
0.6
Standard mode
4.0
0.9
0.9
100
250
Fast mode
0.6
Standard mode
4.7
Fast mode
s
s
Standard mode
Standard mode
kHz
s
Fast mode
Fast mode
UNITS
s
ns
s
300
tR
tF
tSU:STO
CB
CI/O
10
pF
tSP
30
ns
Pushbutton Debounce
tIF
tRST
Fast mode
Standard mode
20 +
0.1CB
tOSF
1000
300
20 +
0.1CB
Fast mode
0.6
Standard mode
4.7
300
250
(Note 12)
25
(Note 13)
ns
pF
ms
35
250
ms
ms
100
tCONV
ns
s
400
PBDB
Interface Timeout
Oscillator Stop Flag (OSF) Delay
Standard mode
ms
125
200
ms
TYP
MAX
UNITS
POWER-SWITCH CHARACTERISTICS
(TA = -40C to +85C)
PARAMETER
CONDITIONS
MIN
tVCCF
300
tVCCR
Recovery at Power-Up
4
SYMBOL
tREC
(Note 14)
125
300
ms
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Pushbutton Reset Timing
RST
PBDB
tRST
Power-Switch Timing
VCC
VPF(MAX)
VPF
VPF(MIN)
tVCCF
VPF
tVCCR
tREC
RST
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Data Transfer on I2C Serial Bus
SDA
tBUF
tF
tHD:STA
tLOW
tSP
SCL
tHIGH
tHD:STA
tHD:DAT
STOP
tSU:STA
tR
START
tSU:STO
tSU:DAT
REPEATED
START
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may
cause loss of data.
Limits at -40C are guaranteed by design and not production tested.
All voltages are referenced to ground.
ICCASCL clocking at max frequency = 400kHz.
Current is the averaged input current, which includes the temperature conversion current.
The RST pin has an internal 50k (nominal) pullup resistor to VCC.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 9: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT 250ns must then be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 11: CBtotal capacitance of one bus line in pF.
Note 12: Minimum operating frequency of the I2C interface is imposed by the timeout period.
Note 13: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V VCC VCC(MAX) and 2.3V VBAT 3.4V.
Note 14: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, tREC is bypassed and RST immediately
goes high.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
RST ACTIVE
50
900
850
800
750
700
2.3
2.8
3.3
3.8
4.3
4.8
5.3
2.3
2.8
3.3
3.8
4.3
4.8
VCC (V)
VBAT (V)
SUPPLY CURRENT
vs. TEMPERATURE
FREQUENCY DEVIATION
vs. TEMPERATURE vs. AGING
75
DS3232 toc03
0.900
VCC = 0V
BB32kHz = 0
VBAT = 3.4V
5.3
0.800
VBAT = 3.0V
0.700
0.600
65
55
45
DS3232 toc04
75
25
VCC = 0V
BB32kHz = 0
BBSQW = 0
BSY = 0
950
100
DS3232 toc02
1000
DS3232 toc01
150
AGING = -128
AGING = -33
35
25
15
AGING = 0
5
-5
-15
-25
-35
-45
-40
-20
0
20
40
TEMPERATURE (C)
60
80
-40
-20
0
20
40
TEMPERATURE (C)
60
80
20
-40
-60
-80
CRYSTAL
+20ppm
-20
TYPICAL CRYSTAL,
UNCOMPENSATED
-100
-120
-140
CRYSTAL
-20ppm
DS3232
ACCURACY
BAND
-40
-60
0
-20
-80
-160
-180
-100
-200
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (C)
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Block Diagram
32kHz
X1
OSCILLATOR AND
CAPACITOR ARRAY
INT/SQW
CONTROL LOGIC/
DIVIDER
X2
SQUARE-WAVE BUFFER;
INT/SQW CONTROL
VCC
VOLTAGE REFERENCE;
DEBOUNCE CIRCUIT;
PUSHBUTTON RESET
DS3232
RST
N
VCC
VBAT
POWER CONTROL
TEMPERATURE
SENSOR
GND
SRAM
SCL
I2C INTERFACE AND
ADDRESS REGISTER
DECODE
SDA
USER BUFFER
(7 BYTES)
Detailed Description
The DS3232 is a serial RTC driven by a temperaturecompensated 32kHz crystal oscillator. The TCXO provides a stable and accurate reference clock, and
maintains the RTC to within 2 minutes per year accuracy from -40C to +85C. The TCXO frequency output
is available at the 32kHz pin. The RTC is a low-power
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW provides either an interrupt signal due to
alarm conditions or a square-wave output. The clock/calendar provides seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. The internal registers are
accessible though an I2C bus interface.
A temperature-compensated voltage reference and
comparator circuit monitors the level of VCC to detect
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Pin Description
PIN
NAME
1, 2,
714, 19
FUNCTION
N.C.
32kHz
32kHz Push-Pull Output. If disabled with either EN32kHz = 0 or BB32kHz = 0, the state of the 32kHz pin
will be low.
VCC
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1F to 1.0F capacitor.
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor. It can
be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control
Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is
determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping
INT/SQW
registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the
INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms
disabled. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC. If not used, this pin can
be left unconnected.
RST
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the
VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the
RST pin is driven high impedance. The active-low, open-drain output is combined with a debounced
pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal 50k
nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the crystal
oscillator is disabled, tRST is bypassed and RST immediately goes high.
15
GND
Ground
16
VBAT
Backup Power-Supply Input. When using the device with the VBAT input as the primary power source, this
pin should be decoupled using a 0.1F to 1.0F low-leakage capacitor. When using the device with the
VBAT input as the backup power source, the capacitor is not required. If VBAT is not used, connect to
ground. The device is UL recognized to ensure against reverse charging when used with a primary lithium
battery. Go to www.maxim-ic.com/qa/info/ul.
17
SDA
Serial-Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin
requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC.
SCL
Serial-Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data
movement on the serial interface. A connection to only one of the pins is required. The other pin must be
connected to the same signal or be left unconnected. Up to 5.5V can be used for this pin, regardless of the
voltage on VCC.
18, 20
power failures and to automatically switch to the backup supply when necessary. The RST pin provides an
external pushbutton function and acts as an indicator of
a power-fail event. Also available are 236 bytes of general-purpose battery-backed SRAM.
Operation
The block diagram shows the main elements of the
DS3232. The eight blocks can be grouped into four
functional groups: TCXO, power control, pushbutton
function, and RTC. Their operations are described separately in the following sections.
Maxim Integrated
32kHz TCXO
The temperature sensor, oscillator, and control logic
form the TCXO. The controller reads the output of the
on-chip temperature sensor and uses a lookup table to
determine the capacitance required, adds the aging
correction in AGE register, and then sets the capacitance selection registers. New values, including
changes to the AGE register, are loaded only when a
change in the temperature value occurs. The temperature is read on initial application of VCC and once every
64 seconds (default, see the description for CRATE1
and CRATE0 in the control/status register) afterwards.
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Power Control
This function is provided by a temperature-compensated voltage reference and a comparator circuit that
monitors the VCC level. When VCC is greater than VPF,
the part is powered by VCC. When VCC is less than VPF
but greater than VBAT, the DS3232 is powered by VCC.
If V CC is less than V PF and is less than V BAT , the
device is powered by VBAT. See Table 1.
POWERED BY
VBAT
VCC
VCC
VCC
Real-Time Clock
To preserve the battery, the first time VBAT is applied to
the device, the oscillator does not start up and no temperature conversions take place until VCC exceeds VPF
or until a valid I2C address is written to the part. After
the first time VCC is ramped up, the oscillator starts up
and the V BAT source powers the oscillator during
power-down and keeps the oscillator running. When
the DS3232 switches to VBAT, the oscillator may be disabled by setting the EOSC bit.
VBAT Operation
There are several modes of operation that affect the
amount of VBAT current that is drawn. While the device
is powered by VBAT and the serial interface is active,
active battery current, IBATA, is drawn. When the serial
interface is inactive, timekeeping current (IBATT), which
includes the averaged temperature conversion current,
IBATTC, is used (refer to Application Note 3644: Power
Considerations for Accurate Real-Time Clocks for
details). Temperature conversion current, IBATTC, is
specified since the system must be able to support the
periodic higher current pulse and still maintain a valid
voltage level. Data retention current, IBATTDR, is the
current drawn by the part when the oscillator is
stopped (EOSC = 1). This mode can be used to minimize battery requirements for times when maintaining
time and date information is not necessary, e.g., while
the end system is waiting to be shipped to a customer.
10
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with an AM/PM indicator.
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
SRAM
The DS3232 provides 236 bytes of general-purpose
battery-backed read/write memory. The I2C address
ranges from 14h to 0FFh. The SRAM can be written or
read whenever VCC or VBAT is greater than the minimum operating voltage.
Address Map
Figure 1 shows the address map for the DS3232 timekeeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
(0FFh), it wraps around to location 00h. On an I 2C
START or address pointer incrementing to location 00h,
the current time is transferred to a second set of registers. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
I2C Interface
The I2C interface is accessible whenever either VCC or
VBAT is at a valid level. If a microcontroller connected to
the DS3232 resets because of a loss of VCC or other
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Figure 1. Address Map for DS3232 Timekeeping Registers and SRAM
ADDRESS
BIT 7
MSB
00h
10 Seconds
Seconds
Seconds
0059
01h
10 Minutes
Minutes
Minutes
0059
02h
12/24
Hour
Hours
112 + AM/PM
0023
03h
Day
17
04h
05h
Century
BIT 6
BIT 5
AM/PM
20 Hour
BIT 3
BIT 2
10 Hour
BIT 1
10 Month
BIT 0
LSB
Day
10 Date
06h
BIT 4
FUNCTION
RANGE
Date
Date
131
Month
Month/
Century
0112 +
Century
Year
Year
0099
07h
A1M1
10 Year
10 Seconds
Seconds
Alarm 1 Seconds
0059
08h
A1M2
10 Minutes
Minutes
Alarm 1 Minutes
0059
09h
A1M3
12/24
Hour
Alarm 1 Hours
112 + AM/PM
0023
0Ah
A1M4
DY/DT
Day
Alarm 1 Day
17
0Bh
A2M2
0Ch
A2M3
12/24
0Dh
A2M4
DY/DT
0Eh
EOSC
BBSQW
CONV
RS2
RS1
INTCN
A2IE
A1IE
0Fh
OSF
BB32kHz
CRATE1
CRATE0
EN32kHz
BSY
A2F
A1F
10h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
11h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
12h
DATA
DATA
13h
14h0FFh
AM/PM
20 Hour
10 Hour
10 Date
10 Minutes
AM/PM
20 Hour
Date
Alarm 1 Date
131
Minutes
Alarm 2 Minutes
0059
Hour
Alarm 2 Hours
112 + AM/PM
0023
Day
Alarm 2 Day
17
Alarm 2 Date
131
Control
Control/Status
DATA
Aging Offset
DATA
MSB of Temp
LSB of Temp
Not used
Reserved for
test
SRAM
00h0FFh
10 Hour
10 Date
Date
Note: Unless otherwise specified, the registers state is not defined when power is first applied.
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Alarms
ALARM RATE
A1M3
A1M2
A1M1
DY/DT
12
ALARM RATE
A2M4
A2M3
A2M2
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Control Register (0Eh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
EOSC
BBSQW
CONV
RS2
RS1
INTCN
A2IE
A1IE
POR*:
*POR is defined as the first application of power to the device, either VBAT or VCC.
Special-Purpose Registers
The DS3232 has two additional registers (control and
control/status) that control the real-time clock, alarms,
and square-wave output.
Maxim Integrated
RS1
SQUARE-WAVE OUTPUT
FREQUENCY
1Hz
1.024kHz
4.096kHz
8.192kHz
13
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Control/Status Register (0Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
OSF
BB32kHz
CRATE1
CRATE0
EN32kHz
BSY
A2F
A1F
POR*:
*POR is defined as the first application of power to the device, either VBAT or VCC.
14
CRATE0
Bit 3: Enable 32kHz Output (EN32kHz). This bit indicates the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin
goes low. The initial power-up state of this bit is logic 1,
and a 32.768kHz square-wave signal appears at the
32kHz pin after a power source is applied to the DS3232
(if the oscillator is running).
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the conversion is complete.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 registers. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 registers. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
SAMPLE RATE
(seconds)
64
128
256
512
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Aging Offset (10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
POR*:
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
POR*:
BIT 6
BIT 5
NAME:
BIT 4
BIT 3
DATA
DATA
POR*:
BIT 2
BIT 1
BIT 0
SRAM (14hFFh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
D7
D6
D5
D4
D3
D2
D1
D0
POR*:
*POR is defined as the first application of power to the device, either VBAT or VCC.
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
MSB FIRST
MSB
LSB
MSB
LSB
SDA
SLAVE
ADDRESS
SCL
17
IDLE
START
CONDITION
R/W
ACK
DATA
17
ACK
DATA
17
ACK/
NACK
STOP CONDITION
REPEATED START
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
<SLAVE
ADDRESS>
S
<R/W>
1101000
XXXXXXXX
<DATA (n)>
A
<DATA (n + 1)>
XXXXXXXX
S - START
SLAVE TO MASTER
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
XXXXXXXX
<DATA (n + X)
A
...
XXXXXXXX
MASTER TO SLAVE
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
<SLAVE
ADDRESS>
S
1101000
<R/W>
<DATA (n)>
XXXXXXXX
<DATA (n + 1)>
A
S - START
MASTER TO SLAVE
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
<DATA (n + 2)>
XXXXXXXX
XXXXXXXX
<DATA (n + X)>
A
...
XXXXXXXX
SLAVE TO MASTER
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
<SLAVE
ADDRESS> <R/W>
S
1101000
<DATA (n)>
XXXXXXXX
XXXXXXXX
<DATA (n + 1)>
A
XXXXXXXX
1101000
<DATA (n + 2)>
A
S - START
MASTER TO SLAVE
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
XXXXXXXX
<DATA (n + X)>
A
...
XXXXXXXX
SLAVE TO MASTER
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
Figure 5. Data Write/Read (Write Pointer, Then Read)Slave Receive and Transmit
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
17
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
The DS3232 can operate in the following two modes:
Slave receiver mode (DS3232 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3232 address,
which is 1101000, followed by the direction bit (R/W),
which is 0 for a write. After receiving and decoding
the slave address byte, the DS3232 outputs an
acknowledge on SDA. After the DS3232 acknowledges the slave address + write bit, the master
transmits a word address to the DS3232. This sets
the register pointer on the DS3232, with the DS3232
acknowledging the transfer. The master may then
transmit zero or more bytes of data, with the DS3232
acknowledging each byte received. The register
pointer increments after each data byte is transferred. The master generates a STOP condition to
terminate the data write.
Slave transmitter mode (DS3232 read mode): The
first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction
bit indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS3232
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave
address and direction bit. The slave address byte is
the first byte received after the master generates a
START condition. The slave address byte contains
the 7-bit DS3232 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a
18
Chip Information
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a +, #, or
- in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 SO
W20#H2
21-0042
90-0108
Maxim Integrated
DS3232
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Revision History
REVISION
NUMBER
REVISION
DATE
9/05
11/05
3/06
10/07
10/08
DESCRIPTION
Initial release
Corrected the supply current units from A to nA and added BSY = 0 to the Supply
Current vs. Supply Voltage graph in the Typical Operating Characteristics
17
Changed the RST pin description to indicate that the pin immediately goes high if
power is applied and the oscillator is disabled
Added a paragraph to the Pushbutton Reset Function section about how the RST output
operation does not affect the devices internal operation
10
Corrected the date register range for 04h from 0031 to 0131 in Figure 1
11
2, 9
In the Electrical Characteristics table, changed the symbols for Timekeeping Battery
Current, Temperature Conversion Current, and Data-Retention Current from I BAT, ITC,
and IBATTC to IBATT, IBATTC, and IBATTDR, respectively
Added the Delta Time and Frequency vs. Temperature graph in the Typical Operating
Characteristics section
Added the VBAT Operation section and improved some sections of text for the Aging
Offset Register and Temperature Registers (11h12h) sections
Updated the I2C timing diagrams (Figures 3, 4, and 5)
7/10
PAGES
CHANGED
Amended the VBAT capacitor representation in the Typical Operating Circuit; in the
Absolute Maximum Ratings section, added the theta-JA and theta-JC thermal
resistances and Note 1, and changed the soldering temperature to +260C; changed
the VBAT pin function description in the Pin Description table; changed the 10-hour bit
to 20-hour bit in the Clock and Calendar section and Figure 1; updated the BBSQW bit
description in the Control Register (0Eh) section; added the land pattern no. to the
Package Information table
10, 15
17
14, 6, 9, 11,
12, 13, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim Integrated
19
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.