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Abstract
Asymmetrical cascaded sub cell multilevel inverter is proposed here in order
to overcome the disadvantages faced in the symmetrical cascaded multilevel
inverter. Asymmetrically cascaded sub cell model is generated by grouping up
basic unit cells in series connections in each phase of the model. DC supply
voltages of basic unit sub cells in each phase will have an arithmetic sequence
with common difference of E. Low frequency and high frequency pulse width
modulation techniques (PWM) can be used efficiently and easily for different
operating conditions. This proposed structure reduces the number of switching
devices, no. of driver circuits, reduces installing space for the proposed model,
cost and voltage across the switches.
I. INTRODUCTION
Generally there are many multilevel inverter structures such as Diode-Clamped
multilevel inverter (Neutral Point Clamped), flying-capacitor multilevel inverter and
cascaded multilevel inverter (symmetrical cascaded or cascaded H bridge multilevel
inverter).
Among the above three multilevel inverters cascaded H-bridge is mostly used due
to the major drawbacks in the diode clamped and flying capacitor multilevel inverter.
Disadvantages in diode clamped multilevel inverter are excessive clamping diodes are
required when the number of levels is high, it is difficult to control the real power
flow of the individual converter in the multi converter systems. And the disadvantages
in the flying-capacitor inverter are an excessive number of storage capacitors is
required when the number of levels is high and high level inverters are more difficult
to package with the bulky power capacitors and are more expensive too, and the
inverter control can be very complicated, and the switching frequency and switching
losses are high for real power transmission.
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Dhanamjayulu C et al
, 2
, 2
=0
The power circuit of proposed model is shown in the fig. 2. Which is a three phase
asymmetrical cascaded n-level inverter comprised of the basic units in each leg of the
circuit connected in series fashion. No. of basic units used will be according to the no.
of output levels required.
The power circuit shown in fig. 2 require different DC sources, where the DC
voltages connected in each leg should be in arithmetic sequence of common
difference E in magnitude. Here if more the no. of voltages levels required the more
will be the DC voltage sources required. The main advantage in this model is that the
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DC voltage sources can be replaced with the renewable energy sources like
photovoltaic or fuel cells etc.
As defined above the DC voltage sources used in each leg of the inverter are as
below
1=
2=2
3=3
=
Where, n=no. of basic units.
Maximum output voltage of all basic units of one leg is,
= (1 + 2 + 3 + 4 . . + )
=
( + 1)
2
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3 = ( 1 2) +
4 = ( 2 3) +
3=
SWITCHING STATES
LINE VOLTAGES
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 Vab Vbc Vca
ON OFF ON OFF OFF ON OFF ON OFF ON OFF ON 3E
0
-3E
ON OFF ON OFF ON OFF OFF ON OFF ON OFF ON 2E
E
-3E
ON OFF ON OFF OFF ON ON OFF OFF ON OFF ON E
2E -3E
ON OFF ON OFF ON OFF ON OFF OFF ON OFF ON 0
3E -3E
OFF ON ON OFF ON OFF ON OFF OFF ON OFF ON -E
3E -2E
ON OFF OFF ON ON OFF ON OFF OFF ON OFF ON -2E
3E
-E
OFF ON OFF ON ON OFF ON OFF OFF ON OFF ON -3E
3E
0
OFF ON OFF ON ON OFF ON OFF ON OFF OFF ON -3E
2E
E
OFF ON OFF ON ON OFF ON OFF OFF ON ON OFF -3E
E
2E
OFF ON OFF ON ON OFF ON OFF ON OFF ON OFF -3E
0
3E
OFF ON OFF ON OFF ON ON OFF ON OFF ON OFF -2E
-E
3E
OFF ON OFF ON ON OFF OFF ON ON OFF ON OFF -E
-2E 3E
OFF ON OFF ON OFF ON OFF ON ON OFF ON OFF 0
-3E 3E
ON OFF OFF ON OFF ON OFF ON ON OFF ON OFF E
-3E 2E
OFF ON ON OFF OFF ON OFF ON ON OFF ON OFF 2E
-3E
E
ON OFF ON OFF OFF ON OFF ON ON OFF ON OFF 3E
-3E
0
ON OFF ON OFF OFF ON OFF ON OFF ON ON OFF 3E
-2E
-E
ON OFF ON OFF OFF ON OFF ON ON OFF OFF ON 3E
-E
-2E
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AMPLITUDE
0.5
-0.5
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
0.03
0.035
0.04
0.045
0.03
0.035
0.04
0.045
TIME (msec)
GATE PULSE (G2)
1.5
AMPLITUDE
0.5
-0.5
0.005
0.01
0.015
0.02
0.025
TIME (msec)
AMPLITUDE
0.5
-0.5
0.005
0.01
0.015
0.02
0.025
TIME (msec)
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Dhanamjayulu C et al
GATE PULSE (G4)
1.5
AMPLITUDE
0.5
-0.5
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
TIME (msec)
VOLTAGE (volts)
350
300
250
200
150
100
50
0
0.01
0.02
0.03
0.04
0.05
TIME (msec)
0.06
0.07
0.08
0.09
0.1
0.06
0.07
0.08
0.09
0.1
0.06
0.07
0.08
0.09
0.1
VOLTAGE (volts)
350
300
250
200
150
100
50
0
0.01
0.02
0.03
0.04
0.05
TIME (msec)
VOLTAGE (volts)
350
300
250
200
150
100
50
0
0.01
0.02
0.03
0.04
0.05
TIME (msec)
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VOLTAGE (volts)
200
100
0
-100
-200
-300
-400
-500
0.01
0.02
0.03
0.04
0.05
TIME (msec)
0.06
0.07
0.08
0.09
0.1
0.06
0.07
0.08
0.09
0.1
0.06
0.07
0.08
0.09
0.1
VOLTAGE (volts)
200
100
0
-100
-200
-300
-400
-500
0.01
0.02
0.03
0.04
0.05
TIME (msec)
LINE VOLTAGE (Vca)
500
400
300
VOLTAGE (volts)
200
100
0
-100
-200
-300
-400
-500
0.01
0.02
0.03
0.04
0.05
TIME (msec)
IV. CONCLUSION
The proposed three phase asymmetrical cascaded multilevel inverter was
implemented with minimum number of switches, gate driver circuits, and reduction of
voltage standing on the switches has been achieved. Due to the above reasons the cost
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and installation area has reduced for the proposed model. Low frequency PWM
techniques have been employed effectively. And the model for four level
compositions have been designed in simulink and simulated successfully.
REFERENCES
[1] HamzaBelkamel, SaadMekhilef, AmmarMasaoud, Mohsen Abdel Naeim,