The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the

TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the
Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the
Timer/Counter uses to increment (or decrement) its value.
Assembly Code Example
.def tempo=r16
.cseg
.org 0x0
ldi tempo,0b00100000
out ddrd,tempo
ldi tempo,0b01000000
sts tccr1a,tempo
ldi tempo,0b00001100
sts tccr1b,tempo
ldi tempo,high(15624)
sts ocr1ah,tempo
ldi tempo,low(15624)
sts ocr1al,tempo
fin:
rjmp fin

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risus. Cras venenatis augue ut porttitor placerat. Quisque pellentesque nisl sit amet purus feugiat, non
pharetra nunc tincidunt. Proin fermentum lorem sed nunc aliquam iaculis. Donec imperdiet leo elit.
Maecenas non rutrum velit, vitae efficitur libero. Vestibulum semper in purus at vehicula. Cras volutpat,
nunc finibus viverra porttitor, urna turpis dapibus nibh, ac aliquet arcu elit quis mauris. Proin sodales elit ac
mauris consequat facilisis. Etiam tincidunt, mauris a dictum vestibulum, dui ligula egestas mi, eu
scelerisque sem diam sit amet ex. Integer faucibus tristique orci at dapibus. Maecenas dolor erat, porta a

dolor porttitor, ullamcorper posuere diam. Quisque non est quis velit pulvinar tempus. Praesent vel turpis
sed est facilisis maximus vel quis tellus.
Assembly Code Example
.dseg
useg: .byte 1
dseg: .byte 1
umin: .byte 1
dmin: .byte 1
uhora: .byte 1
dhora: .byte 1
.cseg
.def tempo=r16
.def segundos=r17
.def uniseg=r18
.def decseg=r19
.def unimin=r20
.def decmin=r21
.def unihora=r22
.def dechora=r23
.org 0x0
rjmp inicio
.org 0x12
rjmp incrementar

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quis pretium turpis fermentum et. Etiam fringilla, nunc vitae cursus egestas, mauris leo ultrices justo, nec
hendrerit nisl magna dapibus nibh. Aliquam maximus ex ac dictum auctor. Duis rhoncus tincidunt dui eu
finibus. Nunc congue justo ut magna tincidunt facilisis. Sed feugiat sollicitudin faucibus.
Assembly Code Example
inicio:
ldi tempo,0b11111111
out ddra,tempo
out ddrc,tempo
out ddrb,tempo
ldi tempo,0b01000010
sts tccr2a,tempo
ldi tempo,0b00000111
sts tccr2b,tempo
ldi tempo,31
sts ocr2a,tempo
ldi tempo,0b00100000
sts assr,tempo
ldi tempo,0b00000010
sts timsk2,tempo
clr segundos
clr uniseg
clr decseg, sei

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ornare porttitor enim. Praesent a augue sed ante imperdiet scelerisque id nec tortor. Nullam laoreet congue
dolor. Donec et facilisis eros, quis sollicitudin urna. Suspendisse vitae nulla bibendum, porta dolor vel,
tempor enim. Proin sollicitudin tristique leo.
Assembly Code Example
lazo:
lds tempo,useg
out porta,tempo
ldi tempo,0b11011111
out portc,tempo
call retardo
ldi tempo,0b11111111
out portc,tempo
lds tempo,dseg
out porta,tempo

Its important to remark that we must repeat this sequence until 0b11011111 rotates right. For example, the
next cycle is the same but only changes ldi tempo 0b11101111.
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Sed in ultrices quam. Aliquam scelerisque fringilla libero eget euismod. Fusce hendrerit sagittis mi vitae
ornare. Sed ac dapibus urna. Donec feugiat nisi nisi, sed eleifend metus facilisis eget.

.def tempo=r16 .def frec=r17 .def aux=r18 .dseg unidad: .byte 1 decena: .byte 1 .cseg .org 0x0 rjmp inicio
.org 0x2 rjmp capturar .org 0x1a rjmp segundo inicio: ldi tempo,low(ramend) out spl,tempo ldi
tempo,high(ramend) out sph,tempo clr tempo out ddrd,tempo ser tempo out ddra,tempo out ddrc,tempo out
ddrb,tempo.
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egestas mi, eu scelerisque sem diam sit amet ex. Integer faucibus tristique orci at dapibus. Maecenas dolor
erat, porta a dolor porttitor, ullamcorper.
Nulla dapibus, nibh eget egestas vulputate, quam justo suscipit est, ut lacinia lectus libero et magna. Mauris
mollis blandit leo sed semper. Cras fermentum purus ultrices nunc eleifend condimentum. Vestibulum id
ligula ornare, venenatis felis quis, dictum felis.
ldi tempo,0b00000010 sts eicra,tempo ldi tempo,0b00000001 out eimsk,tempo ldi tempo,0b00000000 sts
tccr1a,tempo ldi tempo,0b00001100 sts tccr1b,tempo ldi tempo,high(31249) sts ocr1ah,tempo ldi
tempo,low(31259) sts ocr1al,tempo ldi tempo,0b00000010 sts timsk1,tempo ldi tempo,0b01000010 out
tccr0a,tempo ldi tempo,0b00000100 out tccr0b,tempo ldi tempo,1 out ocr0a,tempo sei.
lazo: rjmp lazo capturar: push r16 in r16,sreg push r16 inc frec pop r16 out sreg,r16 pop r16 reti segundo:
push r16 in r16,sreg push r16 subi frec,10 out ocr0a,frec ldi zl,low(tabla_equivalente<<1) ldi
zh,high(tabla_equivalente<<1) add zl,frec clr frec adc zh,frec lpm aux,z clr tempo decenas: subi aux,10
brcs seguir1 inc tempo rjmp decenas seguir1: sts decena,tempo clr tempo subi aux,-10 unidades: subi
aux,1 brcs seguir2 inc tempo rjmp unidades seguir2: sts unidad,tempo ldi zl,low(tabla<<1) ldi
zh,high(tabla<<1) lds tempo,unidad add zl,tempo clr tempo adc zh,tempo lpm tempo,z out portc,tempo ldi
zl,low(tabla<<1) ldi zh,high(tabla<<1) lds tempo,decena add zl,tempo clr tempo adc zh,tempo lpm tempo,z
out porta,tempo clr frec clr aux pop r16 out sreg,r16 pop r16 reti tabla: .db 0b00111111, 0b00000110 .db
0b01011011, 0b01001111 .db 0b01100110, 0b01101101 .db 0b01111101, 0b00000111 .db 0b01111111,
0b01101111 tabla_equivalente: .db 0,5;0,1 .db 10,15;2,3 .db 20,25;4,5 .db 30,35;6,7 .db 40,45;8,9 .db
50,55;10,11 .db 60,65;12,13 .db 70,75;14,15 .db 80,85;16,17 .db 90,95;18,19 .db 100,100.
If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode,
precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one
TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether
the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following
algorithm can be used to ensure that one TOSC1 cycle has elapsed.