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Chair of Microelectronics, Department of Microsystems Engineering - IMTEK,

University of Freiburg, Georges-Koehler-Allee 102

79110 Freiburg, Germany

Email: {Sherif.mohamed, Ortmanns, Manoli}@imtek.de

AbstractThree CMOS RF low noise amplifier circuits have

been designed and simulated. These LNAs are intended for use

in 402-405MHz Medical Implant Communication Service

transceivers. The inductively degenerated common source LNA

(CS-LNA) topology is currently popular because it achieves high

gain, low noise figure, and high linearity. In this paper cascode

LNA with inductive source degeneration, LC folded cascode

LNA topology and current reuse technique are used in a CMOS

CS-LNA with inductive source degeneration. The performance

target is to achieve a moderate gain and moderate noise figure

without overly degrading the linearity.

II.

DEGENERATION

structure is widely used in receiver design. It is easier to

achieve input matching for both the power gain and the noise

figure. The channel width of the input transistor determines

the noise performance of the LNA because the dominant noise

source in CMOS devices is the channel thermal noise [3].

Since the biasing current is fixed, an optimum channel width

can be obtained for minimum noise contribution. Fig.1 shows

a single ended cascode LNA with source inductive

degeneration. Single ended LNAs have smaller noise figures

compared to differential LNAs, they also eliminate the need

for using a balun transformer to interface the antenna to a

differential LNA input, so it consumes less power. The

transistor M 1 and M 2 are same size RF transistors, giving a

better noise isolation. The common-gate transistor

M 2 increases the reverse isolation of the LNA, and improves

the stability of the circuit by minimizing the miller effect of

the parasitic gate-drain capacitance of M 1 (Cgd 1 ) by presenting

I. INTRODUCTION

The use of Radio Frequency in medical applications has

brought numerous advantages such as increased patient safety,

comfort and mobility, for these reasons highly reliable and

ultra-low power consumption implanted wireless devices are

mostly preferred in medical industry [1]. In direct conversion

receivers, the antenna receives the signal from the implanted

device, and the LNA amplifies the weak signal. The mixer

then uses the local oscillator signal to demodulate the input

which is then down converted to the base band.

as the first stage of a Medical Implant Communications

Service (MICS) receiver to provide enough gain to overcome

the noise of subsequent stages while adding as little noise as

possible to the incoming signal. Besides, it should amplify

large signals without distortion, offer enough dynamic range

and provide input and output impedance matching [2]. LNA

design involves tradeoffs between linearity, input matching,

noise figure, and power dissipation.

Vdd

(W L)1 = 350 0.5

(W L)2 = 350 0.5

Ls = 1.6 nH

Lg = 80 nH

Ld = 14 nH

C d = 12 pF

C ex = 160 fF

VBias = 0.5V

circuit analysis and design details of the single ended cascode

LNA with inductive source degeneration. Section III

introduces the design of the folded cascode (FC) LNA.

Section IV shows the design and the advantages of an LNA

using current reuse technique (CRT). The simulation results

and discussion pertaining to S-parameters, linearity and noise

are presented in section V. Conclusions are given in section

VI.

RFout

M2

Vbias

RFin

Ld

Cd

Lg

M1

Cex

Ls

Gnd

Figure 1. Cascode LNA with inductive source degeneration

76

C. Noise Figure

A major advantage of the CS-LNA with inductive source

degeneration is that the resistive impedance is noiseless,

unlike other topologies where a noisy resistor is added in the

signal path to create a 50 termination impedance. The noise

in CS-LNA comprises three factors: channel noise, gate noise,

and correlated noise. The noise figure of the cascode LNA

with inductive degeneration can be computed as [3]:

resonance frequency is at the RF signal of 403MHz and to

provide a DC path for the bias current of both M 1 and M 2 .

When the LC-tank resonates, it functions as an impedance

with a value Rb = (1 + Q 2 ) Rind . The operation of the LC-tank is

limited by the quality factor (Q) of the tank circuit [5]. A little

current will be lost by the LC-tank for parasitic resistance

( Rind ) of the on-chip spiral inductor and a loss factor ( ) is

defined to calculate the loss current.

1 gm 2

Rb 2 + 1 gm 2

F = 1+

where = 1 + 2 c QCS

A. Input Matching

The input impedance of the common-source (CS) LNA

can be written as [5]:

g L

1

+ m1 s

j Cgs1 Cgs1

between the gate noise and the drain noise. Note that the

miller capacitance Cgd has been neglected in the interest of

simplicity. We observe that (6) contains terms which are

proportional to QCS as well as inversely proportional to QCS .

Hence, there exists an optimum quality factor that minimizes

the noise figure. Also, the cutoff frequency T of the device

should be high, the channel length should be minimized.

(2)

capacitance and the transconduactance of M 1 . The input

matching at the resonance frequency (0 ) can be achieved by

setting the real part of (1) to the source impedance ( Rs ) and the

imaginary part to zero. The matching conditions are:

Rs =

Ls gm1

1

, Lg + Ls = 2

0 Cgs1

Cgs1

D. Linearity

An important metric of linearity for LNA design is the

input third order modulation point ( IIP3 ) of the circuit.

The IIP3 of the circuit in Fig.1, assuming input matching can

be written as [6]:

(3)

resonance and the associated effective quality factor of the

input

circuit

assuming

input

matching

is

QCS = (1 20 Cgs Rs ) > 1 , the input matching can be adjusted by

input matching.

B. Gain

The effective transconductance of the CS-LNA stage

neglecting the gate resistance is:

gm1

0 Cgs1 ( Rs + T Ls )

T

0 Rs (1 + T Ls Rs )

The power consumption is an important issue for radio

frequency integrated circuit design. A FC-LNA structure is

makes a low-voltage operation possible. The commongate M 2 of the cascode LNA is folded to another biasing path.

This FC topology gives the chance of increasing the effective

bias voltage. As the effective bias voltage increases, gm1 of

M 1 increases, consequently increasing the cutoff frequency,

which results in an overall reduction in the noise figure, (6).

(4)

independent of the gm1 of the device, and is dependent on the

CMOS process parameters through the transition

frequency T . Using (4), we can calculate the following

expressions for the voltage gain assuming input matching.

A = (

T RL

)

0 2 Rs

(7)

The first term in (7) is the intrinsic IIP3 of the device, and

arises from the fact that short channel CMOS transistors

exhibit velocity saturation, which gradually linearizes the ideal

quadratic drain current equation of the long channel transistor.

The second term results from the extra voltage boost across

the Cgs due to the series tank.

Gm ,CS = gm1QCS =

(6)

g

2 2

+

(1 + QCS2 ) , m , gd 0 is

5

5

gd 0

the zero-bias drain source conductance, and are the bias

dependent coefficients of channel thermal noise and gate noise

respectively, Rl represents the series resistance of the

inductor Lg , Rg is the gate resistance of the NMOS device,

(1)

minimize the lossy current.

Zin = j ( Lg + Ls ) +

Rl Rg 0

+

+

( )

Rs Rs QCS T

Fig.2. where the CS and CG stages are folded into two paths.

At DC the supply voltage needs to bias only one transistor in

each path, which mean that the minimum supply voltage

(5)

77

Vdd

Ld

Cd

Vbias

Lg

RFin

(W L)2 = 350 0.5 Lg = 80 nH

Ld = 14 nH Cd = 12 pF

L0 = 14 nH C 0 = 12 pF

C ex = 160 fF VBias = 0.5V

M1

Fig.4 shows the LNA topology. An inverter stage

( M 1 and M 2 ) with inductive source degeneration is used to

provide more design parameters to achieve a high gain and

low NF at the same time. This configuration provides a high

transconductance necessary to achieve high gain, and low

reverse gain necessary to provide sufficient isolation and to

simplify input and output port matching. The transistor M 3 is

folded to another biasing path. The NF of the LNA neglecting

the gate-drain capacitance can be shown to be [7]:

M2

Cex

RFout

Ls

C0

Gnd

L0

F 1 + (8 2 Cgs2 Rs ) 3gm1

Gnd

specification where a large gm1 is typically needed to reduce

the noise figure.

At AC the RF signal is fed from the CS stage into the CG

stage; and actually works as a traditional cascode LNA at the

operation frequency. The ( Ld , Cd ) tank is chosen such that the

resonance frequency is at the RF signal frequency 403MHz.

At this frequency it provides a high impedance branch to force

the RF signal into the source of M 2 . In order for this

operation to be true it is required that the impedance of the

parallel LC-tank at resonance is much higher than the input

resistance seen at the source of M 2 . It can be shown that this

is satisfied by choosing the transconductance of M 2 ,

gm 2 1 Rd Qd2 where Rd and Qd are the resistance and quality

factor associated with the inductor Ld . The tuned

tank L0 , C0 circuit acts as a filter to ensure that the

specifications for center frequency, bandwidth and gain are

met.

The three designed LNAs are simulated using a

0.13 m CMOS process in the Cadence design environment.

The input signal power ranged from -40 to 0dBm. The Sparameter are used to describe the behavior of a system

working at high frequencies, where S11 represents input

reflection, S22 output reflection, S21 direct gain and S12 is the

reverse gain.

The software ASITIC [8] is then used to generate the

equivalent circuit model for spiral inductors to be included in

the simulation. These parasitic effects must be taken into

account since they have a significant effect on the overall

noise and the optimum device geometry and power.

Fig.5 shows the power gain ( S21 ) simulation results of the

three LNAs. The maximum gain is obtained from the LNA

using CRT, where a high transconductance is achieved. This

large gain gives the room to reduce the effect of noise from

the following stages. These three LNA circuits show a good

S11 (less than 25dBm ), S22 (less than 15dBm ), and input

output isolation. Furthermore, these amplifiers have a good

linearity.

V

Unlike traditional CMOS LNAs that trade off the noise

figure for input matching, the goal here is to achieve a high

transconductance gm and a cutoff frequency T = gm Cgs

necessary to achieve a high gain with less current. The current

reuse technique (CRT) topology presented in this paper is able

to simultaneously achieve a good input matching and a low

noise figure. Fig.3 (a) shows a single NMOS device that has

the aspect ratioW L with a drain current I D . Fig.3 (b) shows

two NMOS devices in parallel with each device having an

aspect ratio (1 2)W L and drain current (1 2) I D . Thus, the

transconductance of the compound device in Fig.3 (b) is the

same as the transconductance of the device in Fig.3 (a). In

Fig.3(c), a PMOS device is substituted for device M 2 in

gm

M1

gm ID

ID

(1 / 2)ID

(a)

1/2(W/L)

dd

Cd

Ld

Vbias

RFin

Lg

M2

Cex

M1

(1/ 2)I D

(W L)2 = 500 0.13 Lg = 80 nH

(W L)3 = 600 0.13 Cex = 160 fF

Ld = 14 nH Cd = 12 pF

L0 = 12 nH C 0 = 12 pF

M3

M2

(1/ 2)I D

M1

W/L

(W/L) 2

(8)

gm1 + gm2

M2

1/2(W/L)

(b)

Ls

M1

(W/L)1

(c)

C0

L0

(1/ 2)I D

Gnd

Gnd

Figure 4. Degenerated current reuse LNA

78

RFout

only one single transistor exists in each DC path which

increases the voltage swing and consequently improves the

circuit linearity. Another important figure of merit is the noise

figure; all three LNAs have a fairly low NF over a frequency

band as shown in Fig. 7. The total power dissipation for the

FC-LNA and CRT-LNA is the best due to the high

transconductance with a lower current. Table 1 summarizes

the simulation results obtained from the simulations.

3rd Order

1st Order

20

VI.

40

CONCLUSIONS

LNA with a 1-V power supply in a 0.13 m CMOS process.

These structures are based on CS-LNA with inductive source

degeneration. The proposed LC-folded cascode topology

maintains the advantages of the cascode LNA structure while

making it feasible for the input amplifier of the cascode

structure to work at a high effective voltage with a less

current. This improves the circuit linearity, increases the input

transconductance and consequently the power gain. The CRTLNA is designed to increase the transconductance of the input

stage at the same bias current to be able to achieve a high gain

with a low noise figure. As a tradeoff an additional LC-tank

circuit is used for both FC-LNA and CRT-LNA which

certainly is a major area contributor. Simulation results show

that the three LNAs designed in this work meet the MICS

requirements.

TABLE I.

Parameter

FC-LNA

16.1

18.2

23.7

Isolation (dB)

-60.2

-62.03

-40.2

S11 (dB )

-21.8

-31.78

-41.2

S 22 (dB)

-13.4

-19.5

-18.35

NF (dB )

0.65

0.60

0.62

IIP3 (dBm)

-9.38

-8.0

-10.4

1dB (dBm)

-19.02

-17.71

-25.5

Power cons.(mW)

1.0

0.8

0.8

16

S21 (dB)

NF (dB)

10

8

6

2

0

0

200

400

600

800

1000

Frequency (MHz)

REFERENCES

[1]

[2]

[5]

[6]

-10

[7]

-15

-20

-25

800

-5

600

-5

NF (Cascode)

400

-10

12

S21 (Cascode)

200

-15

NF (CRT)

NF (FC)

14

[4]

-20

18

S21(CRT)

S21 (FC)

10

-25

25

15

[3]

20

-40

-30

CRT-LNA

Gain (dB)

-20

-60

Cascode LNA

[8]

1000

Frequency (MHz)

79

Huseyin S., Ahmet Sula, Zheng Wang, Numan S., E. Arvas, MICS

transceivers: regulatory, standards and applications, IEEE Southeast

Con.2005, pp. 179-182, April 2005.

R.L. Moreno and E.C. Rodrigues, CMOS LNA for wireless

biomedical telemetry, IEE Proc. Circuits Devices and Systems, vol.

152, pp.401-406, October 2005.

Derek K. Shaeffer, and Thomas H. Lee, A 1.5-V, 1.5-GHz CMOS

Low Noise Amplifier,IEEE Journal of Solid-State Circuits, vol.32,

no.32, pp. 745-759, May 1997.

Huseyin S., Ahmet Sula, Zheng Wang, Numan S., E. Arvas, A 1-V

UHF low noise amplifier for ultralow-power applications, proc. IEEE

2006 ISCAS06, pp. 4495-4498, May 2006.

David J. Allstot, Xiaoyong Li, and Sudip Shekhar, Design

considerations for CMOS low-noise amplifiers, symp. IEEE on RFIC,

pp.97-100, June 2004

Paul Leroux, Johan Janessens, and Michiel Stayaert, A 0.8-dB NF

ESD-protected 9-mW CMOS LNA operating at 1.23 GHz, IEEE

Journal of Solid-State Circuits, vol.37, no.6, pp. 760-765, June 2002.

Andrew N. Karanicolas, A 2.7-V 900-MHz CMOS LNA and mixer,

IEEE Journal of Solid-State Circuits, vol.31, no.12, pp. 1939-1944,

December 1996.

A. M. Niknejad and R. G. Meyer, Analsis and optimization of

monolithic inductors and transformers for RF ICs, Proc. IEEE 1997

CICC, pp.375-378, May 1997.

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