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AVANTHIS St.THERESSA INSTITUTE OF ENGG &TECHNOLOGY::GARIVIDI

Vizianagaram Dist.(A.P)

AVANTHI ’ S St.THERESSA INSTITUTE OF ENGG &TECHNOLOGY::GARIVIDI Vizianagaram Dist.(A.P) DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NAME: _________________________________________ ROLL NO: ______________________________________ BRANCH: ______________________________________ LABORATORY: _______________________________

 

AVANTHIS St.THERESSA INSTITUTE OF ENGG &TECHNOLOGY::GARIVIDI

Vizianagaram Dist.(A.P)

AVANTHI ’ S St.THERESSA INSTITUTE OF ENGG &TECHNOLOGY::GARIVIDI Vizianagaram Dist.(A.P) DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

THIS IS TO CERTIFY THAT THIS IS THE BONAFIDE RECORD OF THE WORK DONE IN ………………………………………………………………………………… LABORATORY BY MR./MS. ………………………………………………………………………… BEARING REGD. NO./ROLL NO………………………………… OF ……………………… COURSE DURING …………………………………………………………………………………………………

Total Numbers of Experiments held ……………

LAB-IN-CHARGE

DEPARTMENT

Total Numbers of

Experiments done ………….

HEAD OF THE

SIGNATURE OF EXTERNAL EXAMINER

1. REALIZATION OF LOGIC GATES

AIM: To write a VHDL code logic gates and verify its functionality in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system. SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b. AND GATE:

1. REALIZATION OF LOGIC GATES AIM : To write a VHDL code logic gates and verify

OR GATE:

1. REALIZATION OF LOGIC GATES AIM : To write a VHDL code logic gates and verify

NAND GATE:

NAND GATE: NOT GATE: XOR GATE:

NOT GATE:

NAND GATE: NOT GATE: XOR GATE:

XOR GATE:

NAND GATE: NOT GATE: XOR GATE:

XNOR GATE:

XNOR GATE: PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logicgates is port

PROGRAM CODE:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logicgates is port ( a: in std_logic; b: in std_logic; y: out std_logic_vector(7 downto 0)); End logicgates;

architecture Behavioral of logicgates is begin

y(0) <= a and b; y(1) <= a or b; y(2) <= a nand b; y(3) <= a nor b; y(4) <= a xor b; y(5) <= a xnor b; y(6) <= not b; y(7) <= not a; end Behavioral;

LOGIC APPROACH:

AND GATE:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B.

OR GATE:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation.

NAND GATE:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

NOR GATE:

This

is a NOT-OR gate which is equal to an OR gate followed by a NOT

gate.

The

outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a

small circle on the output. The small circle represents inversion.

NOT GATE:

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic gates in the same way.

EXOR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both,

of its two inputs are high. An encircled plus sign

LOGIC APPROACH: AND GATE: The AND gate is an electronic circuit that gives a high output

is used to show the Ex-OR operation.

EXNOR GATE:

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents inversion.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input. The functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORM:-

EXNOR GATE: The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give

CONCLUSION:

Hence the VHDL code for the realization of logic gates has been verified and the simulation waveform has been observed.

2. PRIORITY ENCODER

AIM: To write a VHDL/Verilog HDL code for 8-3 Priority encoder and verify its functionality in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b.

CIRCUIT DIAGRAM:

2. PRIORITY ENCODER AIM : To write a VHDL/Verilog HDL code for 8-3 Priority encoder and

TRUTH TABLE:

2. PRIORITY ENCODER AIM : To write a VHDL/Verilog HDL code for 8-3 Priority encoder and

VERILOG CODE:

module pencoder(DI,CLK,DO); input [7:0] DI; input CLK; output reg [2:0] DO;

always@(posedge CLK) begin

if(DI[7]==1'b1)

DO=3'b111;

else if (DI[7]==1'b0 && DI[6]==1'b1)

DO=3'b110;

else if(DI[7:6]==2'b00 && DI[5]==1'b1)

DO=3'b101;

else if(DI[7:5]==3'b000 && DI[4]==1'b1)

DO=3'b100;

else if(DI[7:4]==4'b0000 && DI[3]==1'b1)

DO=3'b011;

else if(DI[7:3]==5'b00000 && DI[2]==1'b1)

DO=3'b010;

else if(DI[7:2]==6'b000000 && DI[1]==1'b1)

DO=3'b001;

else if(DI[7:1]==7'b0000000 && DI[0]==1'b1)

end

endmodule

DO=3'b000;

LOGIC APPROACH:-

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the original number starting from zero of the most significant input bit. They are often used to control interrupt requests by acting on the highest priority request.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the circuit is verified by observing the waveform obtained.

SIMULATION WAVEFORMS:

SIMULATION WAVEFORMS: CONCLUSION: Hence the VHDLVerilog HDL code for the Priority encoder has been verified and

CONCLUSION:

Hence the VHDLVerilog HDL code for the Priority encoder has been verified and the simulation waveform has been observed.

 

3. RANDOM COUNTER

 

AIM: To write a VHDL code for 4-bit Random counter and verify its functionality in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1 , modelsim 6.5b.

 

RANDOM COUNTER CIRCUIT DIAGRAMS AND TRUTH TABLES:

CIRCUIT DIAGRAM:

3. RANDOM COUNTER AIM : To write a VHDL code for 4-bit Random counter and verify

TRUTH TABLE:

 

Enable(en)

Clock(clk)

Clear(clr)

Q(output)

 

0

x

x

0000

0

1

1

0000

1

1

1

0001

1

1

1

0010

1

1

1

0011

1

1

1

0100

1

1

1

0101

1

1

1

0110

1

1

1

0111

1

1

1

1000

1

1

1

1001

1

1

1

1010

1

1

1

1011

1

1

1

1100

1

1

1

1101

1

1

1

1110

1

1

1

1111

VERILOG CODE:

module tff(q,t,c); output q; input t,c; reg q;

initial

begin

q=1'b1;

end

always @ (posedge c) begin

if (t==1'b0) begin q=q; end else begin q=~q; end

end

endmodule

module tff1(q,t,c); output q; input t,c; reg q; initial begin

q=1'b0;

end always @ (posedge c) begin

if (t==1'b0) begin q=q; end else begin

q=~q;

end

end endmodule module random(o,clk); output [3:0]o; input clk;

xor (t0,o[3],o[2]); assign t1=o[0]; assign t2=o[1]; assign t3=o[2];

tff u1(o[0],t0,clk); tff1 u2(o[1],t1,clk); tff1 u3(o[2],t2,clk); tff1 u4(o[3],t3,clk); endmodule

LOGIC APPROACH:

A Random counter counts from 0 to 2 N -1, where N is the number of bits/flip-flops in the counter. Each flip-flop is used to represent one bit. The flip-flop in the lowest-order position is complemented/toggled with every clock pulse and a flip-flop in any other position is complemented on the next clock pulse provided all the bits in the lower-order positions are equal to 1.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the circuit is verified by observing the waveform obtained.

SIMULATION WAVEFORMS:

SIMULATION WAVEFORMS: CONCLUSION: Hence the Verilog HDL code for the random counter has been verified and

CONCLUSION:

Hence the Verilog HDL code for the random counter has been verified and the simulation waveform has been observed.

4. SYNCHRONOUS RAM.

AIM: To write a VHDL code for 4-bit Synchronous RAM and verify its functionality in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 11.1 , modelsim 6.5b.

CIRCUIT DIAGRAM:

4. SYNCHRONOUS RAM. AIM : To write a VHDL code for 4-bit Synchronous RAM and verify

TRUTH TABLE:

4. SYNCHRONOUS RAM. AIM : To write a VHDL code for 4-bit Synchronous RAM and verify

VHDL PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity synram is

generic (DATA_WIDTH :integer := 8;

ADDR_WIDTH :integer := 8

);

Port ( clk : in address : in data : inout

STD_LOGIC; STD_LOGIC_VECTOR (7 downto 0); STD_LOGIC_VECTOR (7 downto 0);

cs : in

STD_LOGIC;

we : in

STD_LOGIC;

oe : in end synram;

STD_LOGIC);

architecture Behavioral of synram is ----------------Internal variables---------------- constant RAM_DEPTH :integer := 2**ADDR_WIDTH; signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);

type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0); signal mem : RAM (0 to RAM_DEPTH-1);

begin

-- Memory Write Block -- Write Operation : When we = 1, cs = 1 MEM_WRITE:process (clk) begin

if (rising_edge(clk)) then if (cs = '1' and we = '1') then mem(conv_integer(address)) <= data; end if; end if; end process;

-- Memory Read Block -- Read Operation : When we = 0, oe = 1, cs = 1 MEM_READ:process (clk) begin if (rising_edge(clk)) then if (cs = '1' and we = '0' and oe = '1') then data_out <= mem(conv_integer(address));

end if; end if; end process; end architecture;

LOGIC APPROACH:

Random-access memory (RAM) is a form of computer data storage. A random-access device allows stored data to be accessed directly in any random order. In contrast, other data storage media such as hard disks, CDs, DVDs and magnetic tape, as well as early primary memory types such as drum memory, read and write data only in a predetermined order, consecutively, because of mechanical design limitations. Therefore, the time to access a given data location varies significantly depending on its physical location.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORMS:

SIMULATION WAVEFORMS: CONCLUSION: Hence the VHDL code for the synchronous RAM has been verified and the

CONCLUSION:

Hence the VHDL code for the synchronous RAM has been verified and the simulation waveform has been observed.

5. ALU

AIM: To write a VHDL code for 8-bit ALU and verify its functionality in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1 , modelsim 6.5b.

CIRCUIT DIAGRAM:

5. ALU AIM : To write a VHDL code for 8-bit ALU and verify its functionality

TRUTH TABLE:

5. ALU AIM : To write a VHDL code for 8-bit ALU and verify its functionality

VHDL PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu is

Port ( S : in A : in

STD_LOGIC_VECTOR (2 downto 0); STD_LOGIC_VECTOR (7 downto 0);

B

:

in

STD_LOGIC_VECTOR (7 downto 0);

F : out

STD_LOGIC_VECTOR (7 downto 0));

end alu;

architecture Behavioral of alu is begin

PROCESS(S,A,B) BEGIN CASE S IS WHEN "000"=> ---clear

F<="00000000";

WHEN "001"=> ---subtraction F<=B-A; WHEN "010"=> ---subtraction

F<=A-B; WHEN "011"=> ---addition F<=A+B; WHEN "100"=> ---xor F<=A XOR B; WHEN "101"=> ---or F<=A OR B; WHEN "110"=> ---and F<=A AND B; WHEN OTHERS=> ---preset

F<="11111111";

END CASE; END PROCESS; end Behavioral;

LOGIC APPROACH:

An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and arithmetic micro-operations on a pair of n-bit operands (ex. A [3:0] and B [3:0]). The operations performed by an ALU are controlled by a set of function-select inputs.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input. The functionality of the circuit is verified by observing the waveform obtained.

SIMULATION WAVEFORMS:

LOGIC APPROACH: An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and

CONCLUSION:

Hence the VHDL for the ALU has been verified and the simulation waveforms have been observed

6. UART MODEL

AIM: To write a VHDL code for 8-bit UART model and verify its functionality in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b.

TRANSMITTER FSM:

6. UART MODEL AIM : To write a VHDL code for 8-bit UART model and verify

VHDL PROGRAM:

UART RX:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Ruart is

Port ( RST : in

STD_LOGIC;

CLK : in Dout : out Rx : in

STD_LOGIC;

STD_LOGIC_VECTOR (7 downto 0); STD_LOGIC;

RxRDY: out std_logic); end Ruart;

architecture Behavioral of Ruart is TYPE state_type IS (Idle, Start_Rx, Shift_Rx,Stop_Rx); signal RxFSM: state_type; signal TopRx:std_logic; signal Rx_Reg: std_logic_vector( 7 downto 0); signal RxBitCnt: integer range 0 to 10:=0; constant NDBits: integer :=8;

begin Rx_FSM: process (RST, CLK) begin

if RST='1' then Rx_Reg <= (others => '0'); Dout <=(others => '0'); RxBitCnt <= 0; RxFSM <= idle; RxRDY <= '0'; elsif rising_edge(CLK) then case RxFSM is when Idle => if Rx='0' then -- wait on start bit RxRDY <= '1'; RxFSM <= Start_Rx; else

RxRDY <= '0'; end if; when Start_Rx => -- wait on first data bit if TopRx='1' then RxFSM <= Shift_Rx; if RxBitCnt = NDbits then RxFSM <= Stop_Rx;

else RxFSM <= Shift_Rx; end if; end if; when Shift_Rx => if TopRx = '1' then RxBitCnt <= RxBitCnt + 1; -- shift right :

Rx_Reg <= Rx & Rx_Reg (Rx_Reg'high downto 1); RxFSM <= Start_Rx; end if; when Stop_Rx => -- during Stop bit if TopRx = '1' then Dout <= Rx_reg; RxFSM <= Idle; end if; end case; end if; end process; end Behavioral;

UART TX:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity suart is Port ( RST : in

STD_LOGIC;

CLK : in Din : in LoaD : in

STD_LOGIC;

STD_LOGIC_VECTOR (7 downto 0); STD_LOGIC;

TxBusy: out std_logic;

TX : out end suart;

STD_LOGIC);

architecture Behavioral of suart is TYPE state_type IS (Idle, Load_Tx, Shift_Tx,Stop_Tx); signal TxFSM: state_type; signal RegDin: std_logic_vector(7 downto 0); signal TopTx:std_logic; signal Tx_Reg: std_logic_vector( 9 downto 0); signal TxBitCnt: integer range 0 to 10:=0; constant NDBits: integer :=8;

begin TX <= Tx_Reg(0); Tx_FSM: process (RST, CLK) begin if RST='1' then Tx_Reg <= (others => '1'); TxBitCnt <= 0; TxFSM <= idle; TxBusy <= '0'; RegDin <= (others=>'0'); elsif rising_edge(CLK) then case TxFSM is when Idle => if LoaD='1' then -- latch the input data immediately. RegDin <= Din; TxBusy <= '1';

TxFSM <= Load_Tx; else TxBusy <= '0'; end if; when Load_Tx => if TopTx='1' then TxFSM <= Shift_Tx; TxBitCnt <= (NDBits + 1); -- start + data Tx_reg <= '1' & RegDin & '0'; end if; when Shift_Tx => if TopTx='1' then TxBitCnt <= TxBitCnt - 1; Tx_reg <= '1' & Tx_reg (Tx_reg'high downto 1); if TxBitCnt=1 then TxFSM <= Stop_Tx; end if; end if; when Stop_Tx => if TopTx='1' then TxFSM <= Idle; end if; when others => TxFSM <= Idle; end case; end if; end process; end Behavioral;

LOGIC APPROACH:

A Universal Asynchronous Receiver/Transmitter, abbreviated UART, is a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA, RS-232, RS- 422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable. The electric signaling levels and methods (such as differential signaling etc.) are handled by a driver circuit external to the UART.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORMS :( FOR UART RX)

RESULT ANALYSIS: SOFTWARE: In the software analysis, we are going to force the input logic condition

SIMULATION WAVEFORM :( For UART TX)

SIMULATION WAVEFORM :( For UART TX) CONCLUSION: Hence the VHDL code for the UART has been

CONCLUSION:

Hence the VHDL code for the UART has been verified and the simulation waveform has been observed.

7. FIRE DETECTION AND CONTROL SYSTEM USING COMBINATIONAL LOGIC CIRCUITS.

AIM: To write a VHSIC/Verilog HDL code for fire detection and control system using combinational logic circuits and verify its functionality in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b.

BLOCK DIAGRAM:

7. FIRE DETECTION AND CONTROL SYSTEM USING COMBINATIONAL LOGIC CIRCUITS. AIM : To write a VHSIC/Verilog

VHDL PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fire is

Port ( clk : in rst : in sensor : in alarm : out

STD_LOGIC;

STD_LOGIC;

STD_LOGIC_VECTOR (5 downto 0); STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR (7 downto 0));

actuator : out display : out

end fire;

architecture Behavioral of fire is begin

process (clk, rst) begin if (rising_edge(clk)) then if (rst = '1') then alarm<= '0'; actuator<= '0'; display<= (others => '0');

else

alarm<= s(0) and s(1) and s(2) and s(3) and s(4) and s(5) ; actuator<= s(0) and s(1) and s(2) and s(3) and s(4) and s(5) ; display<= (others => s(0) and s(1) and s(2) and s(3) and s(4) and s(5)) ; end if; end if; end process; end architecture;

LOGIC APPROACH:

An automatic fire detection and control system is designed to detect the unwanted presence of fire by monitoring environmental changes associated with combustion. In general, a fire alarm system is classified as either automatically actuated, manually actuated, or both. Automatic fire alarm systems are intended to notify the building occupants to evacuate in the event of a fire or other emergency, report the event to an off-premises location in order to summon emergency services, and to prepare the structure and associated systems to control the spread of fire and smoke.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORM:

SIMULATION WAVEFORM: CONCLUSION: Hence the VHDL code for the fire detection and control system using combinational

CONCLUSION:

Hence the VHDL code for the fire detection and control system using combinational logic circuits has been verified and the simulation waveform has been observed

8. TRAFFIC LIGHT CONTROLLER USING SEQUENTIAL LOGIC CIRCUITS

AIM: To write a VHDL code for traffic light controller using sequential logic circuitsand verify its functionality in both software simulator and hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b.

CIRCUIT DIAGRAM:

8. TRAFFIC LIGHT CONTROLLER USING SEQUENTIAL LOGIC CIRCUITS AIM : To write a VHDL code for

VHDL PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tfcontroller_code is

Port ( clk : in

STD_LOGIC;

rst : in

STD_LOGIC;

Green : out

STD_LOGIC;

Red : out

STD_LOGIC;

Yellow : out end tfcontroller_code;

STD_LOGIC);

architecture Behavioral of tfcontroller_code is

signal count:integer range 0 to 10 := 0; signal state:integer range 0 to 2 := 0; begin process(clk, rst) begin if(rst = '1') then state <= 0; Red <= '1'; Green <= '0'; Yellow <= '0'; count <= 0; elsif clk'event and clk='1' then case state is

when 0 =>

--Red Light

if(count=5) then count <= 0; state <= 1;

else

count <= (count + 1); Red <= '1'; Green <= '0'; Yellow <= '0'; end if;

when 1 =>

--Green Light

if(count=5) then count <= 0;

state <= 2;

else

count <= count + 1; Red <= '0'; Green <= '1'; Yellow <= '0'; end if;

when 2 =>

--Yellow Light

if(count=2) then count <= 0;

state <= 0;

else

count <= count + 1; Red <= '0'; Green <= '0'; Yellow <= '1'; end if;

when others => state <= 0; count <= 0; end case; end if; end process; end Behavioral;

LOGIC APPROACH:

The normal function of traffic lights control requires sophisticated control and coordination to ensure that traffic moves as smoothly and safely as possible and that pedestrians are protected when they cross the roads. A variety of different control systems are used to accomplish this, ranging from simple clockwork mechanisms to sophisticated computerized control and coordination systems that self-adjust to minimize delay to people using the road.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORM:

RESULT ANALYSIS: SOFTWARE: In the software analysis, we are going to force the input logic condition

CONCLUSION:

Hence the VHDL code for the traffic light controller using sequential circuits has been verified and the simulation waveform has been observed.

9. PATTERN DETECTION USING MOORE MACHINE

AIM: To write a VHDL code for Pattern detection using Moore machine in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b.

CIRCUIT DIAGRAM:

9. PATTERN DETECTION USING MOORE MACHINE AIM : To write a VHDL code for Pattern detection

TRUTH TABLE:

PRESENT STATE

NEXT STATE

OUTPUT (det_vld)

 

Seq=0

Seq=1

 

A

A

B

0

B

C

B

0

C

A

D

0

D

C

A

1

VHDL PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pattern1 is port(clk : in std_logic;

--clock signal

reset : in std_logic;--reset signa seq : in std_logic; --serial bit sequence// det_vld : out std_logic--A '1' indicates the pattern - --"1011" is detected in the sequence); end pattern1;

architecture Behavioral of pattern1 is

type state_type is (A,B,C,D);--Defines the type for states in --the state machine// signal state : state_type := A;--Declare the signal with the --corresponding state type//. begin

process(clk)

begin

if( reset = '1' ) then det_vld <= '0'; state <= A; elsif ( rising_edge(clk) ) then case state is when A => det_vld <= '0'; if ( seq = '0' ) then state <= A;

else state <= B; end if;

when B => if ( seq = '0' ) then state <= C;

else state <= B; end if;

when C => if ( seq = '0' ) then state <= A; else

state <= D; end if; when D => if ( seq = '0' ) then state <= C;

else

state <= A; det_vld <= '1'; end if; when others => NULL; end case; end if; end process; end Behavioral;

LOGIC APPROACH:

To detect a pattern for’’ 1011’’: When present state is A and if input sequence is 0 then

remains in same state i.e state A else state B. When present state is B and if i/p seq is 0 then it transits to next state i.e state C else remains in state B. I f present state is C and if i/p seq is 0 then it goes to State A else transits to D. If present state is D and i/p seq is 0 then it transits to state C else transits to state A.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORM:

SIMULATION WAVEFORM: CONCLUSION: Hence the VHDL code for the pattern detection using moore machine has been

CONCLUSION:

Hence the VHDL code for the pattern detection using moore machine has been verified and the simulation waveform has been observed.

10. FINITE STATE MACHINE (FSM) BASED LOGIC CIRCUIT.

AIM: To write a VHDL code for Finite state machine (FSM) based logic circuit in both Software simulator and Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b.

STATE DIAGRAM:

10. FINITE STATE MACHINE (FSM) BASED LOGIC CIRCUIT. AIM : To write a VHDL code for

TRUTH TABLE:

Present state

Next state

output

S0

S0

S1

  • 0 0

 

S1

S2

S1

  • 0 0

 

S2

S0

S3

  • 0 0

 

S3

S2

S4

  • 0 0

 

S4

S2

S1

  • 0 1

 

VHDL PROGRAM:

library ieee ; use ieee.std_logic_1164.all; entity seq_design is port(a:in std_logic; clock:in std_logic; reset:in std_logic; x:out std_logic); end seq_design;

architecture FSM of seq_design is

type state_type is (S0, S1, S2, S3); signal next_state, current_state: state_type;

begin -- cocurrent process#1: state registers state_reg: process(clock, reset) begin if (reset='1') then current_state <= S0; elsif (clock'event and clock='1') then current_state <= next_state; end if; end process;

comb_logic: process(current_state, a) begin case current_state is when S0 =>x <= '0'; if a='0' then next_state <= S0;

elsif a ='1' then next_state <= S1; end if; when S1 =>x <= '0'; if a='0' then next_state <= S1; elsif a='1' then next_state <= S2; end if; when S2 =>x <= '0'; if a='0' then next_state <= S2; elsif a='1' then next_state <= S3; end if; when S3 =>x <= '1'; if a='0' then next_state <= S3; elsif a='1' then next_state <= S0; end if; when others => x <= '0'; next_state <= S0; end case; end process; end FSM;

LOGIC APPROACH:

A finite-state a state machine, is

machine (FSM) or finite-state automaton (plural: automata), or simply a mathematical model of computation used to design both computer

programs and sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any

given time is called the current state. It can change from one state to another when initiated by a triggering event or condition; this is called a transition. A particular FSM is defined by a list of its states, and the triggering condition for each transition.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the simulation software (modelsim) and simulate the waveform for the given input . The functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORM:

RESULT ANALYSIS: SOFTWARE: In the software analysis, we are going to force the input logic condition

CONCLUSION:

Hence the

VHDL code

for the

FSM based

simulation waveform has been observed.

logic circuit

has been

verified and the