3 Voter Counter

Objective
The circuit accepts 3 inputs, and shows the number of Yes
votes on a human-readable seven-segment display. A Yes is
represented by a 1 input value. For example, if the votes are
yes, yes and no, the display must show the decimal number 2
(since there are two yes votes).

Design
We are using 2 ways to design & implement this circuit.
1. Brute Force
2. Modular

Methodology
Whenever a voter says yes, the logic state will be 1.
The 7-segment display will display the number of 1s. Lets say
when there is only 1 yes voter, the 7-segment
should display 1.
In order to do so, we need to turn on the LEDs b
and c. In other words, b and c are 1 and the rest
of the LEDs are 0. So, in order to display 2 and 3,
depending upon, how many voters are yes, we
shall make a circuit. This circuit displays the
number, how many voters say yes.

Figure P1.1

Brute Force Approach

This approach uses 2-level SOP circuit structure. It is treated
as one-multiple-input, multiple-output circuit, and implemented
each output using appropriate 2-level SOP.

Fig P1.2

Truth Table
The truth table clearly shows which segment will glow
depending upon the input. We can make then, expressions for
every segment by using 2-level SOP.
V1
0
0
0
0
1
1
1
1

V2
0
0
1
1
0
0
1
1

V3
0
1
0
1
0
1
0
1

A
1
0
0
1
0
1
1
1

B
1
1
1
1
1
1
1
1

C
1
1
1
0
1
0
0
1

D
1
0
0
1
0
1
1
1

E
1
0
0
1
0
1
1
0

F
1
0
0
0
0
0
0
0

G
0
0
0
1
0
1
1
1

Table P1.1

Expressions
In the right side of expressions, A = V1 , B = V2 & C = V3 for
convenience

1. A = BC + A(B C) +

A B C

2. B =

C+

(A B) + A(B+C) +

3. C = C A B +

A B C

4. D = BC + A(B C) +
5. E =

A B C

A B C

BC + A(B C) +

A B C

6. F = A B C
7. G = BC + A(B C)
Proteus Diagram

Figure P1.3 Inside the 3 VOTER Sub-circuit

The 3 VOTER sub-circuit is simply a combinational logic

circuit designed on the expressions for the 7-segment display
(Common Cathode). It takes 3 inputs (Votes) and displays the
number of yes on the 7-segment display.

Figure P1.4a

Figure P1.4b

Figure P1.4c

Figure P1.4d

Modular Approach
This approach uses two smaller sub-circuits interconnected
together. We divide the overall design into two sub-circuits, and
implement each sub-circuit using 2-level SOP structure. The 1 st
circuit accepts the 3 external inputs (V1, V2, V3) and produces a 2bit output (S1 and S0) representing the number of yes votes. It is
a full adder circuit. The 2nd sub-circuit accepts the S1 and S0
signals, and drives the 7 outputs to illuminate the 7-segment
display.

Figure P1.5

Truth Table (FULL ADDER)

Since, there are two sub-circuits therefore there are two
truth tables. First for the FULL ADDER and second for the 7
SEGMENT .
V1
0
0
0
0
1
1
1

V2
0
0
1
1
0
0
1

V3
0
1
0
1
0
1
0

S0
0
0
0
1
0
1
1

S1
0
1
1
0
1
0
0

Table P1.2 Full Adder Truth Table

The Full Adder circuit accepts 3 inputs and adds the total
yes. Note when only one input is 1, S1 is 1 (Just like Sum in a
Full Adder) and when only two inputs are 1, S0 is 1 but S1 is 0 (Just
like Carry Out in a Full Adder). Thats why it is called a FULL
ADDER Circuit. When all inputs are 1, both outputs are 1. In this
way we get total number of yes or 1 at the output. Now this
output needs to be processed to make it readable on a 7-segment
display.

Expressions
1. S0 = V1V2 + V1V3 + V2V3
2. S1 = V1 V2 V3

Proteus Diagram

Figure P1.6 Full Adder

Truth Table (7 SEGMENT)

S0=A

S1=A

0
0
1
1

0
1
0
1

1
0
1
1

1
1
1
1

1
1
0
1

1
0
1
1

1
0
1
0

1
0
0
0

0
0
1
1

Table P1.3 Seven Segment Sub-circuit Truth Table

The 7-SEGMENT Sub-circuit in Fig P1.5 accepts the two

outputs of the FULL ADDER Sub-circuit(S0 & S1) as inputs(A0 & A1),
and produces seven outputs, each for a single segment. The first
row of the truth table will display the number 0 on 7 segment
display because both inputs are 0. The second row displays 1
because only A1 is 1. The third row displays 2 because only A 2 is
1. The last row displays 3 on 7-segment display. Note that the A 1
is a Sum (FULL ADDER) and A0 is a Carry Out (FULL ADDER).
With the help of expressions derived from truth table, we can
make this sub-circuit and get our required results.

Expressions

1. A = S
2. B = 1

3. C = S

+ S0

+ S1

4. D = S

+ S0

5. E = S

6. F = S
7. G = S0

1
0

Proteus Diagram

Figure P1.7 Seven Segment Sub-circuit

Figure P1.8

Conclusion
Both approaches can be used to acquire the required results.
But there are some differences between them.
No.
1.
2.
3.
4.

Brute Force Approach

Uses a lot of gates
Hard to Debug
Uses SOP rule only
Convenient for Beginners

Modular Approach
Uses a few gates
Easy to Debug
Uses SOP with sub-circuits
Intermediate Level Skill

We can see clearly that Modular Approach is better than

Brute Force Approach as it uses less gates (less volume too). It is
divided into parts(sub-circuits) and therefore easy to debug. The
Brute Force Approach on the other hand, is very helpful for
beginners because only SOP rule is applied to whole truth table,
expression is obtained and simplified and that simplified

expression is implemented while The Modular Approach uses subcircuits, so one should spend time to think the appropriate logic to
acquire the required results and takes more time but when
everything is clear, designing a circuit should not be a big deal.